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authorSean V Kelley <seanvk@posteo.de>2017-02-18 15:22:23 -0800
committerSean V Kelley <seanvk@posteo.de>2017-02-18 15:22:23 -0800
commit731371d19d439228952e1e5317e3cf17afb69f90 (patch)
treeb984b0288dced1a10e04b46e68151b96fe02e535
parent05d2d25c16a52d16c3f4cee14bfa4ca8f0209ba9 (diff)
PROJECT HAS MOVEDHEADmaster
See https://github.com/01org/intel-vaapi-driver Signed-off-by: Sean V Kelley <seanvk@posteo.de>
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-rw-r--r--src/shaders/vme/vme7.inc342
-rw-r--r--src/shaders/vme/vme75.inc365
-rw-r--r--src/shaders/vme/vme75_mpeg2.inc49
-rw-r--r--src/shaders/vme/vme7_mpeg2.inc51
-rw-r--r--src/shaders/vme/vme8.inc374
-rw-r--r--src/shaders/vme/vp8_inter_frame_gen8.asm739
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-rw-r--r--src/shaders/vme/vp8_intra_frame_gen9.g9b73
-rw-r--r--src/sysdeps.h47
-rw-r--r--src/va_backend_compat.h61
-rw-r--r--src/vp8_probs.h339
-rw-r--r--src/vp9_probs.c1106
-rw-r--r--src/vp9_probs.h249
-rw-r--r--src/vpx_probs.AUTHORS0
-rw-r--r--src/vpx_probs.LICENSE0
-rw-r--r--src/vpx_probs.PATENTS0
-rw-r--r--src/wayland-drm-client-protocol.h290
-rw-r--r--src/wayland-drm.xml185
-rw-r--r--test/Makefile.am109
-rw-r--r--test/gtest/LICENSE28
-rw-r--r--test/gtest/README.md280
-rw-r--r--test/gtest/docs/AdvancedGuide.md2182
-rw-r--r--test/gtest/docs/DevGuide.md126
-rw-r--r--test/gtest/docs/Documentation.md14
-rw-r--r--test/gtest/docs/FAQ.md1087
-rw-r--r--test/gtest/docs/Primer.md502
-rw-r--r--test/gtest/docs/PumpManual.md177
-rw-r--r--test/gtest/docs/Samples.md14
-rw-r--r--test/gtest/docs/XcodeGuide.md93
-rw-r--r--test/gtest/include/gtest/gtest-death-test.h294
-rw-r--r--test/gtest/include/gtest/gtest-message.h250
-rw-r--r--test/gtest/include/gtest/gtest-param-test.h1444
-rw-r--r--test/gtest/include/gtest/gtest-param-test.h.pump510
-rw-r--r--test/gtest/include/gtest/gtest-printers.h993
-rw-r--r--test/gtest/include/gtest/gtest-spi.h232
-rw-r--r--test/gtest/include/gtest/gtest-test-part.h179
-rw-r--r--test/gtest/include/gtest/gtest-typed-test.h263
-rw-r--r--test/gtest/include/gtest/gtest.h2236
-rw-r--r--test/gtest/include/gtest/gtest_pred_impl.h358
-rw-r--r--test/gtest/include/gtest/gtest_prod.h58
-rw-r--r--test/gtest/include/gtest/internal/custom/gtest-port.h69
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-rw-r--r--test/gtest/include/gtest/internal/gtest-port-arch.h93
-rw-r--r--test/gtest/include/gtest/internal/gtest-port.h2554
-rw-r--r--test/gtest/include/gtest/internal/gtest-string.h167
-rw-r--r--test/gtest/include/gtest/internal/gtest-tuple.h1020
-rw-r--r--test/gtest/include/gtest/internal/gtest-tuple.h.pump347
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-rw-r--r--test/gtest/include/gtest/internal/gtest-type-util.h.pump297
-rw-r--r--test/gtest/src/gtest-all.cc48
-rw-r--r--test/gtest/src/gtest-death-test.cc1342
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-rw-r--r--test/gtest/src/gtest-port.cc1259
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-rw-r--r--test/gtest/src/gtest-typed-test.cc118
-rw-r--r--test/gtest/src/gtest.cc5388
-rw-r--r--test/gtest/src/gtest_main.cc38
-rw-r--r--test/i965_avcd_config_test.cpp115
-rw-r--r--test/i965_avce_config_test.cpp161
-rw-r--r--test/i965_avce_context_test.cpp257
-rw-r--r--test/i965_avce_test_common.cpp85
-rw-r--r--test/i965_avce_test_common.h39
-rw-r--r--test/i965_chipset_test.cpp104
-rw-r--r--test/i965_config_test.cpp63
-rw-r--r--test/i965_config_test.h56
-rw-r--r--test/i965_initialize_test.cpp66
-rw-r--r--test/i965_internal_decl.h78
-rw-r--r--test/i965_jpeg_decode_test.cpp299
-rw-r--r--test/i965_jpeg_encode_test.cpp530
-rw-r--r--test/i965_jpeg_test_data.cpp915
-rw-r--r--test/i965_jpeg_test_data.h475
-rw-r--r--test/i965_jpegd_config_test.cpp75
-rw-r--r--test/i965_jpege_config_test.cpp78
-rw-r--r--test/i965_streamable.h479
-rw-r--r--test/i965_surface_test.cpp120
-rw-r--r--test/i965_test_environment.cpp93
-rw-r--r--test/i965_test_environment.h100
-rw-r--r--test/i965_test_fixture.cpp157
-rw-r--r--test/i965_test_fixture.h199
-rw-r--r--test/i965_test_image_utils.cpp747
-rw-r--r--test/i965_test_image_utils.h66
-rw-r--r--test/object_heap_test.cpp244
-rw-r--r--test/test.h162
-rw-r--r--test/test_main.cpp36
-rw-r--r--test/test_utils.h78
962 files changed, 9 insertions, 321125 deletions
diff --git a/AUTHORS b/AUTHORS
deleted file mode 100644
index f296b02..0000000
--- a/AUTHORS
+++ /dev/null
@@ -1,10 +0,0 @@
-Intel Linux graphics team working on the driver:
-Chang Zhou
-Gwenole Beauchesne
-Haihao Xiang (primary author)
-Nanhai Zou
-
-Additional contributors:
-Alexander Osin
-Damien Lespiau
-Edgar Hucek
diff --git a/Android.mk b/Android.mk
deleted file mode 100644
index 5cbb9d8..0000000
--- a/Android.mk
+++ /dev/null
@@ -1,4 +0,0 @@
-# Recursive call sub-folder Android.mk
-#
-
- include $(call all-subdir-makefiles)
diff --git a/Makefile.am b/Makefile.am
deleted file mode 100644
index 37ef353..0000000
--- a/Makefile.am
+++ /dev/null
@@ -1,30 +0,0 @@
-AUTOMAKE_OPTIONS = foreign
-
-SUBDIRS = debian.upstream src
-
-if ENABLE_TESTS
-SUBDIRS += test
-endif
-
-
-# Extra clean files so that maintainer-clean removes *everything*
-MAINTAINERCLEANFILES = \
- aclocal.m4 compile config.guess config.sub \
- configure depcomp install-sh ltmain.sh \
- Makefile.in missing
-
-DEB_BUILDDIR = debian.build
-
-deb:
- @[ -d debian ] || ln -s debian.upstream debian
- dpkg-buildpackage -rfakeroot -uc -us
-
-deb.upstream: dist
- -mkdir -p $(DEB_BUILDDIR)
- cd $(DEB_BUILDDIR) && \
- rm -rf $(PACKAGE)-$(VERSION) && \
- tar zxvf ../$(PACKAGE)-$(VERSION).tar.gz && \
- cd $(PACKAGE)-$(VERSION) && \
- $(MAKE) deb -f Makefile.am
-
-EXTRA_DIST = Android.mk
diff --git a/PROJECT_HAS_MOVED b/PROJECT_HAS_MOVED
new file mode 100644
index 0000000..33004c1
--- /dev/null
+++ b/PROJECT_HAS_MOVED
@@ -0,0 +1,9 @@
+We've consolidated our VAAPI Media software projects upstream onto
+github and have been updating distributions with the new source
+locations. Changes are in flight. Next release will be on Github.
+
+Intel-vaapi-driver project has moved to https://github.com/01org/intel-vaapi-driver
+
+Use https://github.com/01org/intel-vaapi-driver/issues/new to file bugs on the
+intel-vaapi-driver github site
+
diff --git a/README b/README
deleted file mode 100644
index 0d1f42e..0000000
--- a/README
+++ /dev/null
@@ -1,57 +0,0 @@
-
- libva-intel-driver
- VA driver for Intel G45 & HD Graphics family
-
- Copyright (C) 2009-2016 Intel Corporation
-
-
-License
--------
-
-Please read the COPYING file available in this package.
-
-
-Overview
---------
-
-libva-intel-driver is the VA-API implementation for Intel G45 chipsets
-and Intel HD Graphics for Intel Core processor family.
-
-Platform definitions:
-CTG: Cantiga, Intel GMA 4500MHD (GM45)
-ILK: Ironlake, Intel HD Graphics for 2010 Intel Core processor family
-SNB: Sandybridge, Intel HD Graphics for 2011 Intel Core processor family
-IVB: Ivybridge
-HSW: Haswell
-BDW: Broadwell
-CHV/BSW: Cherryview/Braswell
-SKL: Skylake
-BXT: Broxton
-KBL: Kabylake
-
-Codecs
-------
-
-H.264 D ILK+
-H.264 E SNB+
-MPEG-2 D CTG+
-VC-1 D SNB+
-JPEG D IVB+
-JPEG E CHV+/BSW+
-VP8 D BDW+
-VP8 E CHV+/BSW+
-HEVC D CHV+/BSW+
-HEVC E SKL+
-VP9 D BXT+
-HEVC 10bit D BXT+
-VP9 10bit D KBL+
-
-Requirements
-------------
-
-libva >= 1.7.0
-
-Testing
--------
-
-Please read the TESTING file available in this package.
diff --git a/TESTING b/TESTING
deleted file mode 100644
index 7f85aca..0000000
--- a/TESTING
+++ /dev/null
@@ -1,146 +0,0 @@
-
-Overview
---------
-
-The libva-intel-driver uses the Google Test Framework (gtest) for testing the
-driver. Documentation for gtest can be found in the test/gtest/doc/
-subdirectory. The original, upstream gtest project can be found at
-https://github.com/google/googletest.
-
-Ideally, driver tests will only verify driver-specific functionality, features
-and internal utility functions and concepts.
-
-Developers are expected to write new tests for any new code that they contribute
-to the project. The project maintainers reserve the right to refuse patch
-submissions if they are not accompanied by tests, when reasonable, or if a
-submission causes existing tests to regress.
-
-
-Google Test Framework Integration
----------------------------------
-
-Google Test recommends it be custom compiled for each project that uses it.
-Therefore, the libva-intel-driver project tracks a subset copy of the Google
-Test Framework source code at release 1.8.0 (initially) in a test/gtest/
-subdirectory of the project source tree. The libva-intel-driver copy of gtest
-will only be updated to new upstream releases (or critical upstream fixes) of
-gtest, only if it is necessary. As of this writing, the last release (1.8.0)
-was August 2016, about three years after its previous release. Thus, there
-should be minimal need to update or maintain gtest within the intel-driver
-project.
-
-Libva-intel-driver tests or other project code should *not* be intermixed within
-the test/gtest/ subdirectory. The test/gtest/ subdirectory should only contain
-source from the upstream Google Test project to make upgrades simpler.
-
-
-Building Google Test Framework Library
---------------------------------------
-
-The Google Test Framework is compiled as a convenience library (libgtest.la)
-within the libva-intel-driver source tree. The rules to build libgtest.la are
-maintained in a custom makefile in the libva-intel-driver project tree
-(see test/Makefile.am). The libgtest.la library will be automatically compiled
-if the tests are enabled by configuration.
-
-
-Building Driver Tests
----------------------
-
-The --enable-tests=[yes|no] configuration option is defined in configure.ac to
-enable or disable compilation of libgtest.la and the driver test executable.
-The default is disabled. When the tests are enabled during configuration, the
-make command will compile the driver tests and link to libgtest.la and output a
-single test/test_i965_drv_video executable. Hence...
-
- "./autogen.sh --enable-tests && make"
-
-...is a minimal example of how one might build the driver and its tests.
-
-
-Writing Driver Tests
---------------------
-
-Libva-intel-driver tests are defined in the test/ subdirectory using the Google
-Test Framework. All driver tests that need a VADriverContextP, VADisplay and
-etc. should define a test fixture that inherits from the I965TestFixture class
-and then use the gtest test fixture macro (TEST_F) to define the test case. The
-I965TestFixture class handles initialization and termination of the i965 driver
-context, display, etc. It also defines various C++ operators to convert to
-these types, amongst others. Additionally, it provides an interface that wraps
-various i965 driver functions. After calling a wrapped function within a test,
-the test should check HasFailure() with the appropriate assertion macro since
-these wrapper functions may generate fatal or non-fatal test assertions.
-
-The following is a basic example of how to use the I965TestFixture class to
-write a test:
-
- #include “i965_test_fixture.h”
- #include <vector>
- class MyDriverATest : public I965TestFixture
- {
- public:
- virtual void SetUp()
- {
- I965TestFixture::SetUp();
-
- // do local test SetUp stuff
- }
- virtual void TearDown()
- {
- // do local test TearDown stuff
-
- I965TestFixture::TearDown();
- }
- };
-
- TEST_F(MyDriverATest, test_case_1)
- {
- ConfigAttribs attribs(
- 1, {type: VAConfigAttribRTFormat, value: VA_RT_FORMAT_YUV420});
-
- // call I965TestFixture wrapper for i965_CreateConfig
- VAConfigID config = this->createConfig(
- VAProfileJPEGBaseline, VAEntrypointVLD, attribs);
- ASSERT_FALSE(HasFailure()); // abort and fail if wrapper call failed
- ASSERT_ID(config); // abort and fail if config id is not valid
-
- // convert I965TestFixture to driver context
- VADriverContextP ctx(*this);
- ASSERT_PTR(ctx); // abort and fail if invalid pointer
-
- // convert I965TestFixture to display
- VADisplay display(*this);
-
- // more testing...
- }
-
-To directly test a driver function that is only declared and defined in a .c
-implementation file, an extern prototype of that function should be declared and
-wrapped in an extern “C” block. The test/i965_internal_decl.h header does some
-of this for you already.
-
-To include a driver's C header file in a C++ test file, the #include should be
-wrapped within an extern “C” block. See test/i965_internal_decl.h for an
-example.
-
-
-Validation/QA
---------------
-
-Validation and QA Teams should compile the test executable and run it directly
-from their build tree. Without any command line options, the executable will
-execute all the tests and report the result to the console. For CI frameworks,
-the --gtest_output=xml:test_result.xml command line option can be specified to
-have the test results dumped to an xml file that can be processed by the CI
-framework. There are various other predefined gtest command line options that
-may also be useful, like test shuffling, repeating, seed, etc. (see --help for
-these options).
-
-
-Distribution
-------------
-
-A libva-intel-driver source distribution is generated during `make dist` and
-includes the necessary Google Test Framework source code and makefile rules
-along with the driver test source code.
diff --git a/autogen.sh b/autogen.sh
deleted file mode 100755
index 626d213..0000000
--- a/autogen.sh
+++ /dev/null
@@ -1,14 +0,0 @@
-#! /bin/sh
-
-srcdir=`dirname "$0"`
-test -z "$srcdir" && srcdir=.
-
-ORIGDIR=`pwd`
-cd "$srcdir"
-
-autoreconf -v --install || exit 1
-cd $ORIGDIR || exit $?
-
-if test -z "$NOCONFIGURE"; then
- "$srcdir"/configure "$@"
-fi
diff --git a/build/gen_version.sh b/build/gen_version.sh
deleted file mode 100644
index 586d588..0000000
--- a/build/gen_version.sh
+++ /dev/null
@@ -1,64 +0,0 @@
-# Copyright (c) 2015 Intel Corporation. All Rights Reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sub license, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice (including the
-# next paragraph) shall be included in all copies or substantial portions
-# of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-# IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
-# ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#!/bin/sh
-
-top_srcdir="$1"
-srcdir="$2"
-
-# git version
-VERSION_FILE=".VERSION"
-OLD_VERSION_FILE=$VERSION_FILE.old
-NEW_VERSION_FILE=$VERSION_FILE.new
-PKG_VERSION_FILE=$VERSION_FILE.pkg
-HAVE_GIT=0;
-
-check_git() {
- git --version 2>&1 /dev/null
- if [ $? -eq "0" ]; then
- HAVE_GIT=1
- else
- HAVE_GIT=0;
- fi
-}
-
-gen_version() {
- echo $VERSION > $NEW_VERSION_FILE
- if [ $HAVE_GIT -eq "1" ]; then
- [ -d $top_srcdir/.git ] && \
- (cd $top_srcdir && git describe --tags) > $NEW_VERSION_FILE || :
- fi
- [ -f $srcdir/$PKG_VERSION_FILE ] && \
- cp -f $srcdir/$PKG_VERSION_FILE $NEW_VERSION_FILE || :
-}
-
-check_git;
-gen_version;
-
-OV=`[ -f $OLD_VERSION_FILE ] && cat $OLD_VERSION_FILE || :`;
-NV=`cat $NEW_VERSION_FILE`;
-if [ "$$OV" != "$$NV" -o ! -f intel_version.h ]; then
- cp -f $NEW_VERSION_FILE $OLD_VERSION_FILE;
- echo "Replace"
- sed -e "s|\@INTEL_DRIVER_GIT_VERSION\@|$NV|" \
- $srcdir/intel_version.h.in > $srcdir/intel_version.h;
-fi
diff --git a/configure.ac b/configure.ac
deleted file mode 100644
index ed3ebdf..0000000
--- a/configure.ac
+++ /dev/null
@@ -1,233 +0,0 @@
-# intel-driver package version number
-m4_define([intel_driver_major_version], [1])
-m4_define([intel_driver_minor_version], [8])
-m4_define([intel_driver_micro_version], [0])
-m4_define([intel_driver_pre_version], [1])
-m4_define([intel_driver_version],
- [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version])
-m4_if(intel_driver_pre_version, [0], [], [
-m4_append([intel_driver_version], intel_driver_pre_version, [.pre])
-])
-
-# libva minimum version requirement
-m4_define([va_api_version], [0.39.4])
-m4_define([libva_package_version], [1.7.3])
-
-# libdrm minimum version requirement
-m4_define([libdrm_version], [2.4.52])
-
-AC_PREREQ([2.57])
-AC_INIT([intel_driver], [intel_driver_version], [haihao.xiang@intel.com],
- [libva-intel-driver])
-AC_CONFIG_SRCDIR([Makefile.am])
-AM_INIT_AUTOMAKE([1.9 tar-ustar])
-
-AC_CONFIG_HEADERS([src/config.h])
-
-INTEL_DRIVER_MAJOR_VERSION=intel_driver_major_version
-INTEL_DRIVER_MINOR_VERSION=intel_driver_minor_version
-INTEL_DRIVER_MICRO_VERSION=intel_driver_micro_version
-AC_DEFINE([INTEL_DRIVER_MAJOR_VERSION], [intel_driver_major_version], [Major version of the driver])
-AC_DEFINE([INTEL_DRIVER_MINOR_VERSION], [intel_driver_minor_version], [Minor version of the driver])
-AC_DEFINE([INTEL_DRIVER_MICRO_VERSION], [intel_driver_micro_version], [Micro version of the driver])
-AC_DEFINE([INTEL_DRIVER_PRE_VERSION], [intel_driver_pre_version], [Preversion of the driver])
-
-INTEL_DRIVER_LT_LDFLAGS="-avoid-version"
-AC_SUBST(INTEL_DRIVER_LT_LDFLAGS)
-
-dnl Use pretty build output with automake >= 1.11
-m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])], [
- AM_DEFAULT_VERBOSITY=1
- AC_SUBST(AM_DEFAULT_VERBOSITY)
-])
-
-AC_ARG_ENABLE(drm,
- [AC_HELP_STRING([--enable-drm],
- [build with VA/DRM API support @<:@default=yes@:>@])],
- [], [enable_drm="yes"])
-
-AC_ARG_ENABLE(x11,
- [AC_HELP_STRING([--enable-x11],
- [build with VA/X11 API support @<:@default=yes@:>@])],
- [], [enable_x11="yes"])
-
-AC_ARG_ENABLE([wayland],
- [AC_HELP_STRING([--enable-wayland],
- [build with VA/Wayland API support @<:@default=yes@:>@])],
- [], [enable_wayland="yes"])
-
-AC_ARG_ENABLE([hybrid-codec],
- [AC_HELP_STRING([--enable-hybrid-codec],
- [build with hybrid codec support @<:@default=no@:>@])],
- [], [enable_hybrid_codec="no"])
-
-AC_ARG_ENABLE([tests],
- [AC_HELP_STRING([--enable-tests],
- [build tests @<:@default=no@:>@])],
- [], [enable_tests="no"])
-
-AC_DISABLE_STATIC
-AC_PROG_LIBTOOL
-AC_PROG_CC
-AM_PROG_CC_C_O
-AC_PROG_CXX
-AC_C_BIGENDIAN
-AC_HEADER_STDC
-AC_SYS_LARGEFILE
-AC_CHECK_LIB([m], [sin])
-AC_CHECK_FUNCS([log2f])
-AC_CHECK_PROGS([PYTHON2], [python2 python])
-
-LIBVA_PACKAGE_VERSION=libva_package_version
-AC_SUBST(LIBVA_PACKAGE_VERSION)
-
-dnl Check for recent enough DRM
-LIBDRM_VERSION=libdrm_version
-PKG_CHECK_MODULES([DRM], [libdrm >= $LIBDRM_VERSION])
-AC_SUBST(LIBDRM_VERSION)
-
-dnl Check for gen4asm
-PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.9], [gen4asm=yes], [gen4asm=no])
-AC_PATH_PROG([GEN4ASM], [intel-gen4asm])
-AS_IF([test "x$GEN4ASM" = "x" ], [AM_CONDITIONAL(HAVE_GEN4ASM, false)],
- [AM_CONDITIONAL(HAVE_GEN4ASM, [test x$gen4asm = xyes])])
-
-dnl Check for git
-AC_ARG_VAR([GIT], [Path to git program, if any])
-AC_PATH_PROG([GIT], [git])
-AM_CONDITIONAL([HAVE_GIT], [test -n "$GIT"])
-
-dnl Check for VA-API
-PKG_CHECK_MODULES(LIBVA_DEPS, [libva >= va_api_version])
-
-dnl Check for VA/DRM API
-USE_DRM="$enable_drm"
-if test "$USE_DRM" = "yes"; then
- PKG_CHECK_MODULES(LIBVA_DRM_DEPS, [libva-drm],
- [AC_DEFINE([HAVE_VA_DRM], [1], [Defined to 1 if VA/DRM API is enabled])],
- [USE_DRM="no"])
-
- # Check for <drm_fourcc.h>
- if test "$USE_DRM" = "yes"; then
- saved_CPPFLAGS="$CPPFLAGS"
- CPPFLAGS="$CPPFLAGS $DRM_CFLAGS"
- AC_CHECK_HEADERS([drm_fourcc.h], [:], [USE_DRM="no"])
- CPPFLAGS="$saved_CPPFLAGS"
- fi
-fi
-AM_CONDITIONAL(USE_DRM, test "$USE_DRM" = "yes")
-
-if test "$enable_hybrid_codec" = "yes"; then
- AC_DEFINE([HAVE_HYBRID_CODEC], [1], [Defined to 1 if hybrid codec is needed])
-fi
-
-AM_CONDITIONAL(ENABLE_TESTS, test "$enable_tests" = "yes")
-
-VA_VERSION=`$PKG_CONFIG --modversion libva`
-VA_MAJOR_VERSION=`echo "$VA_VERSION" | cut -d'.' -f1`
-VA_MINOR_VERSION=`echo "$VA_VERSION" | cut -d'.' -f2`
-VA_MICRO_VERSION=`echo "$VA_VERSION" | cut -d'.' -f3`
-VA_VERSION_STR="$VA_VERSION"
-
-va_full_version_int=`expr ${VA_MAJOR_VERSION:-0} "*" 1000000 + \
- ${VA_MINOR_VERSION:-0} "*" 10000 + \
- ${VA_MICRO_VERSION:-0} "*" 100 + \
- 0`
-VA_DRIVER_INIT_FUNC="__vaDriverInit_${VA_MAJOR_VERSION}_${VA_MINOR_VERSION}"
-AC_DEFINE_UNQUOTED([VA_DRIVER_INIT_FUNC], [$VA_DRIVER_INIT_FUNC],
- [Define driver entry-point])
-
-dnl Check for VA/DRM API
-USE_X11="$enable_x11"
-if test "$USE_X11" = "yes"; then
- PKG_CHECK_MODULES(LIBVA_X11_DEPS, [libva-x11],
- [AC_DEFINE([HAVE_VA_X11], [1], [Defined to 1 if VA/X11 API is enabled])],
- [USE_X11="no"])
-fi
-AM_CONDITIONAL(USE_X11, test "$USE_X11" = "yes")
-
-dnl Check for VA-API drivers path
-AC_ARG_VAR(LIBVA_DRIVERS_PATH, [drivers install path])
-if test -z "$LIBVA_DRIVERS_PATH"; then
- AC_MSG_CHECKING([for VA drivers path])
- LIBVA_DRIVERS_PATH=`$PKG_CONFIG libva --variable driverdir`
-fi
-if test -z "$LIBVA_DRIVERS_PATH"; then
- LIBVA_DRIVERS_PATH="${libdir}/xorg/modules/drivers"
-fi
-AC_MSG_RESULT([$LIBVA_DRIVERS_PATH])
-AC_SUBST(LIBVA_DRIVERS_PATH)
-
-# Check for EGL
-if test "$enable_wayland" = "yes"; then
- enable_egl="yes"
-fi
-
-USE_EGL="no"
-if test "$enable_egl" = "yes"; then
- PKG_CHECK_MODULES([EGL], [egl], [USE_EGL="yes"], [USE_EGL="no"])
- saved_CPPFLAGS="$CPPFLAGS"
- saved_LIBS="$LIBS"
- CPPFLAGS="$CPPFLAGS $EGL_CFLAGS"
- LIBS="$LIBS $EGL_LIBS"
- AC_CHECK_HEADERS([EGL/egl.h], [:], [USE_EGL="no"])
- AC_CHECK_LIB([EGL], [eglGetDisplay], [:], [USE_EGL="no"])
- CPPFLAGS="$saved_CPPFLAGS"
- LIBS="$saved_LIBS"
-fi
-AM_CONDITIONAL(USE_EGL, test "$USE_EGL" = "yes")
-
-# Check for Wayland
-USE_WAYLAND="no"
-if test "$enable_wayland" = "yes"; then
- PKG_CHECK_MODULES([LIBVA_WAYLAND_DEPS], [libva-wayland],
- [USE_WAYLAND="yes"], [:])
-
- if test "$USE_WAYLAND" = "yes"; then
-
- WAYLAND_PREFIX=`$PKG_CONFIG --variable=prefix wayland-client`
- AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner],,
- [${WAYLAND_PREFIX}/bin$PATH_SEPARATOR$PATH])
-
- AC_DEFINE([HAVE_VA_WAYLAND], [1],
- [Defined to 1 if VA/Wayland API is enabled])
- fi
-fi
-AM_CONDITIONAL(USE_WAYLAND, test "$USE_WAYLAND" = "yes")
-
-AC_OUTPUT([
- Makefile
- debian.upstream/Makefile
- src/Makefile
- src/shaders/Makefile
- src/shaders/h264/Makefile
- src/shaders/h264/ildb/Makefile
- src/shaders/h264/mc/Makefile
- src/shaders/mpeg2/Makefile
- src/shaders/mpeg2/vld/Makefile
- src/shaders/post_processing/Makefile
- src/shaders/post_processing/gen5_6/Makefile
- src/shaders/post_processing/gen7/Makefile
- src/shaders/post_processing/gen75/Makefile
- src/shaders/post_processing/gen8/Makefile
- src/shaders/post_processing/gen9/Makefile
- src/shaders/render/Makefile
- src/shaders/utils/Makefile
- src/shaders/vme/Makefile
- test/Makefile
-])
-
-dnl Print summary
-BACKENDS=""
-AS_IF([test "$USE_DRM" = "yes"], [BACKENDS="$BACKENDS drm"])
-AS_IF([test "$USE_X11" = "yes"], [BACKENDS="$BACKENDS x11"])
-AS_IF([test "$USE_WAYLAND" = "yes"], [BACKENDS="$BACKENDS wayland"])
-
-echo
-echo $PACKAGE configuration summary:
-echo
-echo VA-API version ................... : $VA_VERSION_STR
-echo VA-API drivers path .............. : $LIBVA_DRIVERS_PATH
-echo Windowing systems ................ : $BACKENDS
-echo Build tests ...................... : $enable_tests
-echo
diff --git a/debian.upstream/Makefile.am b/debian.upstream/Makefile.am
deleted file mode 100644
index 04a848f..0000000
--- a/debian.upstream/Makefile.am
+++ /dev/null
@@ -1,30 +0,0 @@
-DEBIANFILES = \
- changelog.in \
- compat \
- control.in \
- copyright \
- libva-intel-driver.install \
- rules \
- $(NULL)
-
-DEBIANGENFILES = \
- changelog \
- control \
- $(NULL)
-
-EXTRA_DIST = $(DEBIANFILES)
-
-dist_noinst_DATA = $(DEBIANGENFILES)
-
-DISTCLEANFILES = $(DEBIANGENFILES)
-
-# Extra clean files so that maintainer-clean removes *everything*
-MAINTAINERCLEANFILES = Makefile.in
-
-$(DEBIANGENFILES): %: %.in Makefile
- -$(AM_V_GEN)sed \
- -e 's|\@DATE\@|'"`LC_ALL=C date +'%a, %d %b %Y %X %z'`"'|' \
- -e 's|\@LIBDRM_VERSION\@|$(LIBDRM_VERSION)|' \
- -e 's|\@LIBVA_PACKAGE_VERSION\@|$(LIBVA_PACKAGE_VERSION)|' \
- -e 's|\@PACKAGE_VERSION\@|$(PACKAGE_VERSION)|' \
- $< > $@
diff --git a/debian.upstream/changelog.in b/debian.upstream/changelog.in
deleted file mode 100644
index dff4a96..0000000
--- a/debian.upstream/changelog.in
+++ /dev/null
@@ -1,5 +0,0 @@
-libva-intel-driver (@PACKAGE_VERSION@-1) unstable; urgency=low
-
- * Autogenerated package, see NEWS file for ChangeLog.
-
- -- Gwenole Beauchesne <gwenole.beauchesne@intel.com> @DATE@
diff --git a/debian.upstream/compat b/debian.upstream/compat
deleted file mode 100644
index 7ed6ff8..0000000
--- a/debian.upstream/compat
+++ /dev/null
@@ -1 +0,0 @@
-5
diff --git a/debian.upstream/control.in b/debian.upstream/control.in
deleted file mode 100644
index 08b1029..0000000
--- a/debian.upstream/control.in
+++ /dev/null
@@ -1,28 +0,0 @@
-Source: libva-intel-driver
-Section: libs
-Priority: optional
-Maintainer: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
-Build-Depends: debhelper (>= 5),
- cdbs,
- libdrm-dev (>= @LIBDRM_VERSION@),
- libva-dev (>= @LIBVA_PACKAGE_VERSION@)
-Standards-Version: 3.7.2
-
-Package: libva-intel-driver
-Section: libs
-Architecture: any
-Depends: libva1 (>= @LIBVA_PACKAGE_VERSION@),
- ${shlibs:Depends}, ${misc:Depends}
-Description: VA driver for Intel G45 & HD Graphics family
- Video decode & encode driver for Intel G45 chipsets and Intel HD
- Graphics for Intel Core processor family.
-
-Package: libva-intel-driver-dbg
-Section: libdevel
-Architecture: any
-Depends: libva-intel-driver (= ${Source-Version})
-Description: VA driver for Intel G45 & HD Graphics family (debug symbols)
- Video decode & encode driver for Intel G45 chipsets and Intel HD
- Graphics for Intel Core processor family.
- .
- This package contains the debug files.
diff --git a/debian.upstream/copyright b/debian.upstream/copyright
deleted file mode 100644
index 8f3c4c3..0000000
--- a/debian.upstream/copyright
+++ /dev/null
@@ -1,25 +0,0 @@
-This package is maintained by:
-Gwenole Beauchesne <gwenole.beauchesne@intel.com>
-
-
-License:
-
- Permission is hereby granted, free of charge, to any person obtaining a
- copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sub license, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial portions
- of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/debian.upstream/libva-intel-driver.install b/debian.upstream/libva-intel-driver.install
deleted file mode 100644
index daa01dc..0000000
--- a/debian.upstream/libva-intel-driver.install
+++ /dev/null
@@ -1 +0,0 @@
-debian/tmp/usr/lib/dri/*.so
diff --git a/debian.upstream/rules b/debian.upstream/rules
deleted file mode 100755
index 40b76be..0000000
--- a/debian.upstream/rules
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/make -f
-
-include /usr/share/cdbs/1/rules/debhelper.mk
-include /usr/share/cdbs/1/class/autotools.mk
-include /usr/share/cdbs/1/rules/utils.mk
-
-# Allow SMP build
-ifeq ($(DEBIAN_BUILD_NCPUS),)
- DEBIAN_BUILD_NCPUS = $(shell /usr/bin/getconf _NPROCESSORS_ONLN)
-endif
-ifneq ($(DEBIAN_BUILD_NCPUS),)
- EXTRA_MAKE_FLAGS += -j$(DEBIAN_BUILD_NCPUS)
-endif
-MAKE += $(EXTRA_MAKE_FLAGS)
diff --git a/src/Android.mk b/src/Android.mk
deleted file mode 100755
index ab06bb3..0000000
--- a/src/Android.mk
+++ /dev/null
@@ -1,105 +0,0 @@
-# Copyright (c) 2012 Intel Corporation. All Rights Reserved.
-#
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sub license, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice (including the
-# next paragraph) shall be included in all copies or substantial portions
-# of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-# IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
-# ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-#
-
-LOCAL_PATH:= $(call my-dir)
-
-include $(CLEAR_VARS)
-
-LOCAL_SRC_FILES := \
- dso_utils.c \
- gen6_mfc.c \
- gen6_mfc_common.c \
- gen6_mfd.c \
- gen6_vme.c \
- gen7_vme.c \
- gen7_mfc.c \
- gen7_mfd.c \
- gen75_mfd.c \
- gen75_mfc.c \
- gen8_mfc.c \
- gen8_mfd.c \
- gen8_vme.c \
- gen9_vme.c \
- gen9_mfc.c \
- gen9_mfc_hevc.c \
- gen9_mfd.c \
- gen75_picture_process.c \
- gen75_vme.c \
- gen75_vpp_gpe.c \
- gen75_vpp_vebox.c \
- gen9_post_processing.c \
- i965_avc_bsd.c \
- i965_avc_hw_scoreboard.c\
- i965_avc_ildb.c \
- i965_decoder_utils.c \
- i965_device_info.c \
- i965_drv_video.c \
- i965_encoder.c \
- i965_encoder_utils.c \
- i965_media.c \
- i965_media_h264.c \
- i965_media_mpeg2.c \
- i965_gpe_utils.c \
- i965_post_processing.c \
- gen8_post_processing.c \
- i965_render.c \
- i965_vpp_avs.c \
- gen8_render.c \
- gen9_render.c \
- intel_batchbuffer.c \
- intel_batchbuffer_dump.c\
- intel_driver.c \
- intel_memman.c \
- object_heap.c \
- intel_media_common.c \
- $(NULL)
-
-GEN := $(LOCAL_PATH)/intel_version.h
-$(GEN): SCRIPT := $(LOCAL_PATH)/../build/gen_version.sh
-$(GEN): PRIVATE_PATH := $(LOCAL_PATH)
-$(GEN): PRIVATE_CUSTOM_TOOL = sh $(SCRIPT) $(PRIVATE_PATH)/.. $(PRIVATE_PATH) > $@
-$(GEN): $(LOCAL_PATH)/%.h : $(LOCAL_PATH)/%.h.in $(SCRIPT)
- $(transform-generated-source)
-LOCAL_GENERATED_SOURCES += $(GEN)
-
-LOCAL_CFLAGS := -DLINUX -DANDROID -g -Wall -Wno-unused -fvisibility=hidden
-
-LOCAL_C_INCLUDES := \
- $(TARGET_OUT_HEADERS)/libva \
- $(TARGET_OUT_HEADERS)/libdrm
-
-LOCAL_MODULE_TAGS := optional
-LOCAL_MODULE := i965_drv_video
-
-LOCAL_SHARED_LIBRARIES := libdl libdrm libdrm_intel libcutils \
- libva libva-android libstdc++
-
-ifeq ($(strip $(DRIVER_LOG_ENABLE)),true)
-LOCAL_CFLAGS += -DDRIVER_LOG_ENABLE
-LOCAL_SHARED_LIBRARIES += liblog
-endif
-
-include $(BUILD_SHARED_LIBRARY)
-
-
diff --git a/src/Makefile.am b/src/Makefile.am
deleted file mode 100755
index 424812b..0000000
--- a/src/Makefile.am
+++ /dev/null
@@ -1,232 +0,0 @@
-# Copyright (c) 2007 Intel Corporation. All Rights Reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sub license, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice (including the
-# next paragraph) shall be included in all copies or substantial portions
-# of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-# IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
-# ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-SUBDIRS = shaders
-DIST_SUBDIRS = $(SUBDIRS)
-EXTRA_DIST =
-BUILT_SOURCES =
-
-AM_CPPFLAGS = \
- -DPTHREADS \
- $(DRM_CFLAGS) \
- $(LIBVA_DEPS_CFLAGS) \
- -DVA_DRIVERS_PATH="\"$(LIBVA_DRIVERS_PATH)\"" \
- $(NULL)
-
-driver_cflags = \
- -Wall \
- -fvisibility=hidden \
- $(NULL)
-
-driver_ldflags = \
- -avoid-version \
- -no-undefined \
- -Wl,--no-undefined \
- $(NULL)
-
-driver_libs = \
- -lpthread -lm -ldl \
- $(DRM_LIBS) -ldrm_intel \
- $(NULL)
-
-source_c = \
- dso_utils.c \
- gen6_mfc.c \
- gen6_mfc_common.c \
- gen6_mfd.c \
- gen6_vme.c \
- gen7_vme.c \
- gen7_mfc.c \
- gen7_mfd.c \
- gen75_mfd.c \
- gen75_mfc.c \
- gen8_mfc.c \
- gen8_mfd.c \
- gen8_vme.c \
- gen9_vme.c \
- gen9_mfc.c \
- gen9_mfc_hevc.c \
- gen9_mfd.c \
- gen9_vdenc.c \
- gen75_picture_process.c \
- gen75_vme.c \
- gen75_vpp_gpe.c \
- gen75_vpp_vebox.c \
- gen9_post_processing.c \
- i965_avc_bsd.c \
- i965_avc_hw_scoreboard.c\
- i965_avc_ildb.c \
- i965_decoder_utils.c \
- i965_device_info.c \
- i965_drv_video.c \
- i965_encoder.c \
- i965_encoder_utils.c \
- i965_media.c \
- i965_media_h264.c \
- i965_media_mpeg2.c \
- i965_gpe_utils.c \
- i965_post_processing.c \
- i965_yuv_coefs.c \
- gen8_post_processing.c \
- i965_render.c \
- i965_vpp_avs.c \
- gen8_render.c \
- gen9_render.c \
- intel_batchbuffer.c \
- intel_batchbuffer_dump.c\
- intel_driver.c \
- intel_memman.c \
- object_heap.c \
- intel_media_common.c \
- vp9_probs.c \
- gen9_vp9_encoder_kernels.c \
- gen9_vp9_const_def.c \
- gen9_vp9_encoder.c \
- intel_common_vpp_internal.c \
- $(NULL)
-
-source_h = \
- dso_utils.h \
- gen6_mfc.h \
- gen6_mfd.h \
- gen6_vme.h \
- gen7_mfd.h \
- gen75_picture_process.h \
- gen75_vpp_gpe.h \
- gen75_vpp_vebox.h \
- gen8_post_processing.h \
- gen9_mfd.h \
- gen9_mfc.h \
- gen9_vdenc.h \
- i965_avc_bsd.h \
- i965_avc_hw_scoreboard.h\
- i965_avc_ildb.h \
- i965_decoder.h \
- i965_decoder_utils.h \
- i965_defines.h \
- i965_drv_video.h \
- i965_encoder.h \
- i965_encoder_utils.h \
- i965_media.h \
- i965_media_h264.h \
- i965_media_mpeg2.h \
- i965_mutext.h \
- i965_gpe_utils.h \
- i965_pciids.h \
- i965_post_processing.h \
- i965_render.h \
- i965_structs.h \
- i965_vpp_avs.h \
- i965_yuv_coefs.h \
- intel_batchbuffer.h \
- intel_batchbuffer_dump.h\
- intel_compiler.h \
- intel_driver.h \
- intel_media.h \
- intel_memman.h \
- intel_version.h \
- object_heap.h \
- vp8_probs.h \
- vp9_probs.h \
- sysdeps.h \
- va_backend_compat.h \
- i965_fourcc.h \
- gen9_vp9_encoder.h \
- gen9_vp9_encapi.h \
- gen9_vp9_const_def.h \
- gen9_vp9_encoder_kernels.h \
- intel_gen_vppapi.h \
- intel_common_vpp_internal.h \
- $(NULL)
-
-# convenience library that can be linked by driver and tests
-noinst_LTLIBRARIES = libi965_drv_video.la
-libi965_drv_video_la_CFLAGS = $(driver_cflags)
-libi965_drv_video_la_LDFLAGS = $(driver_ldflags)
-libi965_drv_video_la_LIBADD = $(driver_libs)
-libi965_drv_video_la_SOURCES = $(source_c)
-
-# driver module
-i965_drv_video_la_LTLIBRARIES = i965_drv_video.la
-i965_drv_video_ladir = $(LIBVA_DRIVERS_PATH)
-i965_drv_video_la_CFLAGS = $(driver_cflags)
-i965_drv_video_la_LDFLAGS = -module $(driver_ldflags)
-i965_drv_video_la_LIBADD = libi965_drv_video.la $(driver_libs)
-i965_drv_video_la_SOURCES =
-
-noinst_HEADERS = $(source_h)
-
-if USE_X11
-source_c += i965_output_dri.c
-source_h += i965_output_dri.h
-endif
-
-if USE_WAYLAND
-source_c += i965_output_wayland.c
-source_h += i965_output_wayland.h
-source_h += $(protocol_source_h)
-driver_cflags += $(WAYLAND_CFLAGS)
-endif
-
-# git version
-VERSION_FILE = .VERSION
-OLD_VERSION_FILE = $(VERSION_FILE).old
-NEW_VERSION_FILE = $(VERSION_FILE).new
-PKG_VERSION_FILE = $(VERSION_FILE).pkg
-
-intel_version.h: gen-version
- $(AM_V_GEN) \
- OV=`[ -f $(OLD_VERSION_FILE) ] && cat $(OLD_VERSION_FILE) || :`; \
- NV=`cat $(NEW_VERSION_FILE)`; \
- if [ "$$OV" != "$$NV" -o ! -f intel_version.h ]; then \
- cp -f $(NEW_VERSION_FILE) $(OLD_VERSION_FILE); \
- $(SED) -e "s|\@INTEL_DRIVER_GIT_VERSION\@|$${NV}|" \
- $(srcdir)/intel_version.h.in > intel_version.h; \
- fi
-
-gen-version:
- @echo $(VERSION) > $(NEW_VERSION_FILE)
-if HAVE_GIT
- @[ -d $(top_srcdir)/.git ] && \
- (cd $(top_srcdir) && $(GIT) describe --tags) > $(NEW_VERSION_FILE) || :
-endif
- @[ -f $(srcdir)/$(PKG_VERSION_FILE) ] && \
- cp -f $(srcdir)/$(PKG_VERSION_FILE) $(NEW_VERSION_FILE) || :
-
-$(PKG_VERSION_FILE): $(NEW_VERSION_FILE)
- @cp -f $< $@
-
-BUILT_SOURCES += intel_version.h
-EXTRA_DIST += Android.mk intel_version.h.in $(PKG_VERSION_FILE)
-
-# Wayland protocol
-protocol_source_h = wayland-drm-client-protocol.h
-i965_output_wayland.c: $(protocol_source_h)
-%-client-protocol.h : %.xml
- $(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
-
-EXTRA_DIST += \
- wayland-drm.xml \
- $(NULL)
-
-# Extra clean files so that maintainer-clean removes *everything*
-MAINTAINERCLEANFILES = Makefile.in config.h.in
diff --git a/src/config_android.h b/src/config_android.h
deleted file mode 100644
index f3ecb92..0000000
--- a/src/config_android.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* src/config.h. Generated from config.h.in by configure. */
-/* src/config.h.in. Generated from configure.ac by autoheader. */
-/* NOTE: THIS VERSION IS FOR ANDROID ONLY and manually adjusted */
-
-/* Define if building universal (internal helper macro) */
-/* #undef AC_APPLE_UNIVERSAL_BUILD */
-
-/* Define to 1 if you have the <dlfcn.h> header file. */
-#define HAVE_DLFCN_H 1
-
-/* Define to 1 if you have the <inttypes.h> header file. */
-#define HAVE_INTTYPES_H 1
-
-/* Defined to 1 if VA-API exposes JPEG decoding */
-#define HAVE_JPEG_DECODING 1
-
-/* Define to 1 if you have the <memory.h> header file. */
-#define HAVE_MEMORY_H 1
-
-/* Define to 1 if you have the <stdint.h> header file. */
-#define HAVE_STDINT_H 1
-
-/* Define to 1 if you have the <stdlib.h> header file. */
-#define HAVE_STDLIB_H 1
-
-/* Define to 1 if you have the <strings.h> header file. */
-#define HAVE_STRINGS_H 1
-
-/* Define to 1 if you have the <string.h> header file. */
-#define HAVE_STRING_H 1
-
-/* Define to 1 if you have the <sys/stat.h> header file. */
-#define HAVE_SYS_STAT_H 1
-
-/* Define to 1 if you have the <sys/types.h> header file. */
-#define HAVE_SYS_TYPES_H 1
-
-/* Define to 1 if you have the <unistd.h> header file. */
-#define HAVE_UNISTD_H 1
-
-/* Major version of the driver */
-#define INTEL_DRIVER_MAJOR_VERSION 1
-
-/* Micro version of the driver */
-#define INTEL_DRIVER_MICRO_VERSION 16
-
-/* Minor version of the driver */
-#define INTEL_DRIVER_MINOR_VERSION 0
-
-/* Preversion of the driver */
-#define INTEL_DRIVER_PRE_VERSION 1
-
-/* Define to the sub-directory in which libtool stores uninstalled libraries.
- */
-#define LT_OBJDIR ".libs/"
-
-/* Define to 1 if your C compiler doesn't accept -c and -o together. */
-/* #undef NO_MINUS_C_MINUS_O */
-
-/* Name of package */
-#define PACKAGE "libva-driver-intel"
-
-/* Define to the address where bug reports for this package should be sent. */
-#define PACKAGE_BUGREPORT "haihao.xiang@intel.com"
-
-/* Define to the full name of this package. */
-#define PACKAGE_NAME "intel_driver"
-
-/* Define to the full name and version of this package. */
-#define PACKAGE_STRING "intel_driver 1.0.16.pre1"
-
-/* Define to the one symbol short name of this package. */
-#define PACKAGE_TARNAME "libva-driver-intel"
-
-/* Define to the home page for this package. */
-#define PACKAGE_URL ""
-
-/* Define to the version of this package. */
-#define PACKAGE_VERSION "1.0.16.pre1"
-
-/* Define to 1 if you have the ANSI C header files. */
-#define STDC_HEADERS 1
-
-/* Define driver entry-point */
-#define VA_DRIVER_INIT_FUNC __vaDriverInit_0_33
-
-/* Version number of package */
-#define VERSION "1.0.16.pre1"
-
-/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
- significant byte first (like Motorola and SPARC, unlike Intel). */
-#if defined AC_APPLE_UNIVERSAL_BUILD
-# if defined __BIG_ENDIAN__
-# define WORDS_BIGENDIAN 1
-# endif
-#else
-# ifndef WORDS_BIGENDIAN
-/* # undef WORDS_BIGENDIAN */
-# endif
-#endif
-
-/* Number of bits in a file offset, on hosts where this is settable. */
-/* #undef _FILE_OFFSET_BITS */
-
-/* Define for large files, on AIX-style hosts. */
-/* #undef _LARGE_FILES */
-#ifdef ANDROID
-#define Drawable unsigned int
-#endif
diff --git a/src/dso_utils.c b/src/dso_utils.c
deleted file mode 100644
index 8fdea11..0000000
--- a/src/dso_utils.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (C) 2012 Intel Corporation. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#define _GNU_SOURCE 1
-#include <stdio.h>
-#include <stdlib.h>
-#include <dlfcn.h>
-#include "dso_utils.h"
-
-struct dso_handle {
- void *handle;
-};
-
-/* Opens the named shared library */
-struct dso_handle *
-dso_open(const char *path)
-{
- struct dso_handle *h;
-
- h = calloc(1, sizeof(*h));
- if (!h)
- return NULL;
-
- if (path) {
- h->handle = dlopen(path, RTLD_LAZY|RTLD_LOCAL);
- if (!h->handle)
- goto error;
- }
- else
- h->handle = RTLD_DEFAULT;
- return h;
-
-error:
- dso_close(h);
- return NULL;
-}
-
-/* Closes and disposed any allocated data */
-void
-dso_close(struct dso_handle *h)
-{
- if (!h)
- return;
-
- if (h->handle) {
- if (h->handle != RTLD_DEFAULT)
- dlclose(h->handle);
- h->handle = NULL;
- }
- free(h);
-}
-
-/* Load symbol into the supplied location */
-static bool
-get_symbol(struct dso_handle *h, void *func_vptr, const char *name)
-{
- dso_generic_func func, * const func_ptr = func_vptr;
- const char *error;
-
- dlerror();
- func = (dso_generic_func)dlsym(h->handle, name);
- error = dlerror();
- if (error) {
- fprintf(stderr, "error: failed to resolve %s(): %s\n", name, error);
- return false;
- }
- *func_ptr = func;
- return true;
-}
-
-/* Loads symbols into the supplied vtable */
-bool
-dso_get_symbols(
- struct dso_handle *h,
- void *vtable,
- unsigned int vtable_length,
- const struct dso_symbol *symbols
-)
-{
- const struct dso_symbol *s;
-
- for (s = symbols; s->name != NULL; s++) {
- if (s->offset + sizeof(dso_generic_func) > vtable_length)
- return false;
- if (!get_symbol(h, ((char *)vtable) + s->offset, s->name))
- return false;
- }
- return true;
-}
diff --git a/src/dso_utils.h b/src/dso_utils.h
deleted file mode 100644
index 9b8eba7..0000000
--- a/src/dso_utils.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2012 Intel Corporation. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef DSO_UTILS_H
-#define DSO_UTILS_H
-
-#include <stdbool.h>
-
-/** Generic pointer to function. */
-typedef void (*dso_generic_func)(void);
-
-/** Library handle (opaque). */
-struct dso_handle;
-
-/** Symbol lookup table. */
-struct dso_symbol {
- /** Symbol name */
- const char *name;
- /** Offset into the supplied vtable where symbol is to be loaded. */
- unsigned int offset;
-};
-
-/**
- * Opens the named shared library.
- *
- * @param[in] path the library name, or NULL to lookup into loaded libraries
- * @return the newly allocated library handle
- */
-struct dso_handle *
-dso_open(const char *path);
-
-/** Closes and disposed any allocated data. */
-void
-dso_close(struct dso_handle *h);
-
-/**
- * Loads symbols into the supplied vtable.
- *
- * @param[in] handle the DSO handle
- * @param[in] vtable the function table to fill in
- * @param[in] vtable_length the size (in bytes) of the function table
- * @param[in] symbols the NULL terminated array of symbols to lookup
- * @return true on success, false otherwise
- **/
-bool
-dso_get_symbols(
- struct dso_handle *h,
- void *vtable,
- unsigned int vtable_length,
- const struct dso_symbol *symbols
-);
-
-#endif /* DSO_UTILS_H */
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
deleted file mode 100644
index 1765530..0000000
--- a/src/gen6_mfc.c
+++ /dev/null
@@ -1,1514 +0,0 @@
-/*
- * Copyright © 2010-2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Zhou Chang <chang.zhou@intel.com>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include <math.h>
-
-#include "intel_batchbuffer.h"
-#include "i965_defines.h"
-#include "i965_structs.h"
-#include "i965_drv_video.h"
-#include "i965_encoder.h"
-#include "i965_encoder_utils.h"
-#include "gen6_mfc.h"
-#include "gen6_vme.h"
-#include "intel_media.h"
-
-#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
-#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
-#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
-
-static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
-#include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
-};
-
-static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
-#include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
-};
-
-static struct i965_kernel gen6_mfc_kernels[] = {
- {
- "MFC AVC INTRA BATCHBUFFER ",
- MFC_BATCHBUFFER_AVC_INTRA,
- gen6_mfc_batchbuffer_avc_intra,
- sizeof(gen6_mfc_batchbuffer_avc_intra),
- NULL
- },
-
- {
- "MFC AVC INTER BATCHBUFFER ",
- MFC_BATCHBUFFER_AVC_INTER,
- gen6_mfc_batchbuffer_avc_inter,
- sizeof(gen6_mfc_batchbuffer_avc_inter),
- NULL
- },
-};
-
-static void
-gen6_mfc_pipe_mode_select(VADriverContextP ctx,
- int standard_select,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- assert(standard_select == MFX_FORMAT_AVC);
-
- BEGIN_BCS_BATCH(batch, 4);
-
- OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
- OUT_BCS_BATCH(batch,
- (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
- ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
- ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
- (0 << 7) | /* disable TLB prefectch */
- (0 << 5) | /* not in stitch mode */
- (1 << 4) | /* encoding mode */
- (2 << 0)); /* Standard Select: AVC */
- OUT_BCS_BATCH(batch,
- (0 << 20) | /* round flag in PB slice */
- (0 << 19) | /* round flag in Intra8x8 */
- (0 << 7) | /* expand NOA bus flag */
- (1 << 6) | /* must be 1 */
- (0 << 5) | /* disable clock gating for NOA */
- (0 << 4) | /* terminate if AVC motion and POC table error occurs */
- (0 << 3) | /* terminate if AVC mbdata error occurs */
- (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
- (0 << 1) | /* AVC long field motion vector */
- (0 << 0)); /* always calculate AVC ILDB boundary strength */
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- BEGIN_BCS_BATCH(batch, 6);
-
- OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- ((mfc_context->surface_state.height - 1) << 19) |
- ((mfc_context->surface_state.width - 1) << 6));
- OUT_BCS_BATCH(batch,
- (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
- (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
- (0 << 22) | /* surface object control state, FIXME??? */
- ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
- (0 << 2) | /* must be 0 for interleave U/V */
- (1 << 1) | /* must be y-tiled */
- (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* must be 0 for interleave U/V */
- (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-void
-gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int i;
-
- BEGIN_BCS_BATCH(batch, 24);
-
- OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
-
- if (mfc_context->pre_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0); /* pre output addr */
-
- if (mfc_context->post_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* post output addr */
- else
- OUT_BCS_BATCH(batch, 0);
-
- OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* uncompressed data */
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* StreamOut data*/
- OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- /* 7..22 Reference pictures*/
- for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
- if ( mfc_context->reference_surfaces[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- }
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* Macroblock status buffer*/
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
-
- BEGIN_BCS_BATCH(batch, 11);
-
- OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /* MFX Indirect MV Object Base Address */
- OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- mfc_context->mfc_indirect_pak_bse_object.end_offset);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-void
-gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- BEGIN_BCS_BATCH(batch, 4);
-
- OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
- OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
-
- BEGIN_BCS_BATCH(batch, 13);
- OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
- OUT_BCS_BATCH(batch,
- ((width_in_mbs * height_in_mbs) & 0xFFFF));
- OUT_BCS_BATCH(batch,
- (height_in_mbs << 16) |
- (width_in_mbs << 0));
- OUT_BCS_BATCH(batch,
- (0 << 24) | /*Second Chroma QP Offset*/
- (0 << 16) | /*Chroma QP Offset*/
- (0 << 14) | /*Max-bit conformance Intra flag*/
- (0 << 13) | /*Max Macroblock size conformance Inter flag*/
- (1 << 12) | /*Should always be written as "1" */
- (0 << 10) | /*QM Preset FLag */
- (0 << 8) | /*Image Structure*/
- (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
- OUT_BCS_BATCH(batch,
- (400 << 16) | /*Mininum Frame size*/
- (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
- (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
- (0 << 13) | /*CABAC 0 word insertion test enable*/
- (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
- (1 << 10) | /*Chroma Format IDC, 4:2:0*/
- (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
- (0 << 6) | /*Only valid for VLD decoding mode*/
- (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
- (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
- (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
- (1 << 2) | /*Frame MB only flag*/
- (0 << 1) | /*MBAFF mode is in active*/
- (0 << 0) ); /*Field picture flag*/
- OUT_BCS_BATCH(batch,
- (1<<16) | /*Frame Size Rate Control Flag*/
- (1<<12) |
- (1<<9) | /*MB level Rate Control Enabling Flag*/
- (1 << 3) | /*FrameBitRateMinReportMask*/
- (1 << 2) | /*FrameBitRateMaxReportMask*/
- (1 << 1) | /*InterMBMaxSizeReportMask*/
- (1 << 0) ); /*IntraMBMaxSizeReportMask*/
- OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
- (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
- (0x0800) ); /*IntraMbMaxSz 256 Byte*/
- OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
- OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
- OUT_BCS_BATCH(batch, 0xFEFDFCFB);
- OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
- OUT_BCS_BATCH(batch, 0x00800001);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- int i;
-
- BEGIN_BCS_BATCH(batch, 69);
-
- OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
-
- /* Reference frames and Current frames */
- for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
- if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- }
-
- /* POL list */
- for(i = 0; i < 32; i++) {
- OUT_BCS_BATCH(batch, i/2);
- }
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_avc_slice_state(VADriverContextP ctx,
- VAEncPictureParameterBufferH264 *pic_param,
- VAEncSliceParameterBufferH264 *slice_param,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int rate_control_enable,
- int qp,
- struct intel_batchbuffer *batch)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int beginmb = slice_param->macroblock_address;
- int endmb = beginmb + slice_param->num_macroblocks;
- int beginx = beginmb % width_in_mbs;
- int beginy = beginmb / width_in_mbs;
- int nextx = endmb % width_in_mbs;
- int nexty = endmb / width_in_mbs;
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
- int last_slice = (endmb == (width_in_mbs * height_in_mbs));
- int maxQpN, maxQpP;
- unsigned char correct[6], grow, shrink;
- int i;
- int weighted_pred_idc = 0;
- unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
- unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
- int num_ref_l0 = 0, num_ref_l1 = 0;
-
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- if (slice_type == SLICE_TYPE_I) {
- luma_log2_weight_denom = 0;
- chroma_log2_weight_denom = 0;
- } else if (slice_type == SLICE_TYPE_P) {
- weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
- num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
-
- if (slice_param->num_ref_idx_active_override_flag)
- num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- } else if (slice_type == SLICE_TYPE_B) {
- weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
- num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
-
- if (slice_param->num_ref_idx_active_override_flag) {
- num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
- }
-
- if (weighted_pred_idc == 2) {
- /* 8.4.3 - Derivation process for prediction weights (8-279) */
- luma_log2_weight_denom = 5;
- chroma_log2_weight_denom = 5;
- }
- }
-
- maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
- maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
-
- for (i = 0; i < 6; i++)
- correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
-
- grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
- (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
- shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
- (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
-
- BEGIN_BCS_BATCH(batch, 11);;
-
- OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
- OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
-
- OUT_BCS_BATCH(batch,
- (num_ref_l0 << 16) |
- (num_ref_l1 << 24) |
- (chroma_log2_weight_denom << 8) |
- (luma_log2_weight_denom << 0));
-
- OUT_BCS_BATCH(batch,
- (weighted_pred_idc << 30) |
- (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
- (slice_param->disable_deblocking_filter_idc << 27) |
- (slice_param->cabac_init_idc << 24) |
- (qp<<16) | /*Slice Quantization Parameter*/
- ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
- ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
- OUT_BCS_BATCH(batch,
- (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
- (beginx << 16) |
- slice_param->macroblock_address );
- OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
- OUT_BCS_BATCH(batch,
- (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
- (1 << 30) | /*ResetRateControlCounter*/
- (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
- (4 << 24) | /*RC Stable Tolerance, middle level*/
- (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
- (0 << 22) | /*QP mode, don't modfiy CBP*/
- (0 << 21) | /*MB Type Direct Conversion Enabled*/
- (0 << 20) | /*MB Type Skip Conversion Enabled*/
- (last_slice << 19) | /*IsLastSlice*/
- (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
- (1 << 17) | /*HeaderPresentFlag*/
- (1 << 16) | /*SliceData PresentFlag*/
- (1 << 15) | /*TailPresentFlag*/
- (1 << 13) | /*RBSP NAL TYPE*/
- (0 << 12) ); /*CabacZeroWordInsertionEnable*/
- OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
- OUT_BCS_BATCH(batch,
- (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
- (maxQpP << 16) | /*Target QP + 20 is highest QP*/
- (shrink << 8) |
- (grow << 0));
- OUT_BCS_BATCH(batch,
- (correct[5] << 20) |
- (correct[4] << 16) |
- (correct[3] << 12) |
- (correct[2] << 8) |
- (correct[1] << 4) |
- (correct[0] << 0));
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- int i;
-
- BEGIN_BCS_BATCH(batch, 58);
-
- OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
- OUT_BCS_BATCH(batch, 0xFF ) ;
- for( i = 0; i < 56; i++) {
- OUT_BCS_BATCH(batch, 0x10101010);
- }
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- int i;
-
- BEGIN_BCS_BATCH(batch, 113);
- OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
-
- for(i = 0; i < 112;i++) {
- OUT_BCS_BATCH(batch, 0x10001000);
- }
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
- unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
- int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
- struct intel_batchbuffer *batch)
-{
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
-
- OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
-
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* always start at offset 0 */
- (data_bits_in_last_dw << 8) |
- (skip_emul_byte_count << 4) |
- (!!emulation_flag << 3) |
- ((!!is_last_header) << 2) |
- ((!!is_end_of_slice) << 1) |
- (0 << 0)); /* FIXME: ??? */
-
- intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
- ADVANCE_BCS_BATCH(batch);
-}
-
-void
-gen6_mfc_init(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- dri_bo *bo;
- int i;
- int width_in_mbs = 0;
- int height_in_mbs = 0;
- int slice_batchbuffer_size;
-
- if (encoder_context->codec == CODEC_H264) {
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- } else {
- VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
-
- assert(encoder_context->codec == CODEC_MPEG2);
-
- width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
- height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
- }
-
- slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
- (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
-
- /*Encode common setup for MFC*/
- dri_bo_unreference(mfc_context->post_deblocking_output.bo);
- mfc_context->post_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
- mfc_context->pre_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
- mfc_context->uncompressed_picture_source.bo = NULL;
-
- dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
- mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
-
- for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
- if (mfc_context->direct_mv_buffers[i].bo != NULL)
- dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
- mfc_context->direct_mv_buffers[i].bo = NULL;
- }
-
- for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
- if (mfc_context->reference_surfaces[i].bo != NULL)
- dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
- mfc_context->reference_surfaces[i].bo = NULL;
- }
-
- dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- width_in_mbs * 64,
- 64);
- assert(bo);
- mfc_context->intra_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- width_in_mbs * height_in_mbs * 16,
- 64);
- assert(bo);
- mfc_context->macroblock_status_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
- 64);
- assert(bo);
- mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
- 0x1000);
- assert(bo);
- mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
- mfc_context->mfc_batchbuffer_surface.bo = NULL;
-
- dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->aux_batchbuffer_surface.bo = NULL;
-
- if (mfc_context->aux_batchbuffer)
- intel_batchbuffer_free(mfc_context->aux_batchbuffer);
-
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
- slice_batchbuffer_size);
- mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
- dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->aux_batchbuffer_surface.pitch = 16;
- mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
- mfc_context->aux_batchbuffer_surface.size_block = 16;
-
- i965_gpe_context_init(ctx, &mfc_context->gpe_context);
-}
-
-static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
- mfc_context->set_surface_state(ctx, encoder_context);
- mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
- gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
- gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
- mfc_context->avc_img_state(ctx, encode_state, encoder_context);
- mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
- mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
- gen6_mfc_avc_directmode_state(ctx, encoder_context);
- intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
-}
-
-
-VAStatus
-gen6_mfc_run(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
-
- intel_batchbuffer_flush(batch); //run the pipeline
-
- return VA_STATUS_SUCCESS;
-}
-
-VAStatus
-gen6_mfc_stop(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int *encoded_bits_size)
-{
- VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VACodedBufferSegment *coded_buffer_segment;
-
- vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
- assert(vaStatus == VA_STATUS_SUCCESS);
- *encoded_bits_size = coded_buffer_segment->size * 8;
- i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
-
- return VA_STATUS_SUCCESS;
-}
-
-
-static int
-gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
- struct intel_encoder_context *encoder_context,
- unsigned char target_mb_size, unsigned char max_mb_size,
- struct intel_batchbuffer *batch)
-{
- int len_in_dwords = 11;
-
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, len_in_dwords);
-
- OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- (0 << 24) | /* PackedMvNum, Debug*/
- (0 << 20) | /* No motion vector */
- (1 << 19) | /* CbpDcY */
- (1 << 18) | /* CbpDcU */
- (1 << 17) | /* CbpDcV */
- (msg[0] & 0xFFFF) );
-
- OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
- OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
-
- /*Stuff for Intra MB*/
- OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
- OUT_BCS_BATCH(batch, msg[2]);
- OUT_BCS_BATCH(batch, msg[3]&0xFC);
-
- /*MaxSizeInWord and TargetSzieInWord*/
- OUT_BCS_BATCH(batch, (max_mb_size << 24) |
- (target_mb_size << 16) );
-
- ADVANCE_BCS_BATCH(batch);
-
- return len_in_dwords;
-}
-
-static int
-gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
- unsigned int *msg, unsigned int offset,
- struct intel_encoder_context *encoder_context,
- unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
- struct intel_batchbuffer *batch)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- int len_in_dwords = 11;
-
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, len_in_dwords);
-
- OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
-
- OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
- OUT_BCS_BATCH(batch, offset);
-
- OUT_BCS_BATCH(batch, msg[0]);
-
- OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
-#if 0
- if ( slice_type == SLICE_TYPE_B) {
- OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
- } else {
- OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
- }
-#else
- OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
-#endif
-
-
- /*Stuff for Inter MB*/
- OUT_BCS_BATCH(batch, msg[1]);
- OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
- OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
-
- /*MaxSizeInWord and TargetSzieInWord*/
- OUT_BCS_BATCH(batch, (max_mb_size << 24) |
- (target_mb_size << 16) );
-
- ADVANCE_BCS_BATCH(batch);
-
- return len_in_dwords;
-}
-
-static void
-gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- struct intel_batchbuffer *slice_batch)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
- unsigned int *msg = NULL, offset = 0;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
- int i,x,y;
- int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- unsigned int tail_data[] = { 0x0, 0x0 };
- int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int is_intra = slice_type == SLICE_TYPE_I;
- int qp_slice;
- int qp_mb;
-
- qp_slice = qp;
- if (rate_control_mode != VA_RC_CQP) {
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
- if (encode_state->slice_header_index[slice_index] == 0) {
- pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
- qp_slice = qp;
- }
- }
-
- /* only support for 8-bit pixel bit-depth */
- assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
- assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
- assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
- assert(qp >= 0 && qp < 52);
-
- gen6_mfc_avc_slice_state(ctx,
- pPicParameter,
- pSliceParameter,
- encode_state, encoder_context,
- (rate_control_mode != VA_RC_CQP), qp_slice, slice_batch);
-
- if ( slice_index == 0)
- intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
-
- intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
-
- dri_bo_map(vme_context->vme_output.bo , 1);
- msg = (unsigned int *)vme_context->vme_output.bo->virtual;
-
- if (is_intra) {
- msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
- } else {
- msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
- msg += 32; /* the first 32 DWs are MVs */
- offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
- }
-
- for (i = pSliceParameter->macroblock_address;
- i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
- int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
- x = i % width_in_mbs;
- y = i / width_in_mbs;
-
- if (vme_context->roi_enabled) {
- qp_mb = *(vme_context->qp_per_mb + i);
- } else {
- qp_mb = qp;
- }
-
- if (is_intra) {
- assert(msg);
- gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
- msg += INTRA_VME_OUTPUT_IN_DWS;
- } else {
- if (msg[0] & INTRA_MB_FLAG_MASK) {
- gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
- } else {
- gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb,
- msg, offset, encoder_context,
- 0, 0, slice_type, slice_batch);
- }
-
- msg += INTER_VME_OUTPUT_IN_DWS;
- offset += INTER_VME_OUTPUT_IN_BYTES;
- }
- }
-
- dri_bo_unmap(vme_context->vme_output.bo);
-
- if ( last_slice ) {
- mfc_context->insert_object(ctx, encoder_context,
- tail_data, 2, 8,
- 2, 1, 1, 0, slice_batch);
- } else {
- mfc_context->insert_object(ctx, encoder_context,
- tail_data, 1, 8,
- 1, 1, 1, 0, slice_batch);
- }
-
-
-}
-
-static dri_bo *
-gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *batch;;
- dri_bo *batch_bo;
- int i;
-
- batch = mfc_context->aux_batchbuffer;
- batch_bo = batch->buffer;
-
- for (i = 0; i < encode_state->num_slice_params_ext; i++) {
- gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
- }
-
- intel_batchbuffer_align(batch, 8);
-
- BEGIN_BCS_BATCH(batch, 2);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
- ADVANCE_BCS_BATCH(batch);
-
- dri_bo_reference(batch_bo);
-
- intel_batchbuffer_free(batch);
- mfc_context->aux_batchbuffer = NULL;
-
- return batch_bo;
-}
-
-
-static void
-gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- assert(vme_context->vme_output.bo);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &vme_context->vme_output,
- BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
- SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
- assert(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &mfc_context->aux_batchbuffer_surface,
- BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
- SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
-}
-
-static void
-gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
- mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
- mfc_context->mfc_batchbuffer_surface.pitch = 16;
- mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
- "MFC batchbuffer",
- mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
- 0x1000);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &mfc_context->mfc_batchbuffer_surface,
- BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
- SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
-}
-
-static void
-gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
- gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
-}
-
-static void
-gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_interface_descriptor_data *desc;
- int i;
- dri_bo *bo;
-
- bo = mfc_context->gpe_context.idrt.bo;
- dri_bo_map(bo, 1);
- assert(bo->virtual);
- desc = bo->virtual;
-
- for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
- struct i965_kernel *kernel;
-
- kernel = &mfc_context->gpe_context.kernels[i];
- assert(sizeof(*desc) == 32);
-
- /*Setup the descritor table*/
- memset(desc, 0, sizeof(*desc));
- desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
- desc->desc2.sampler_count = 0;
- desc->desc2.sampler_state_pointer = 0;
- desc->desc3.binding_table_entry_count = 2;
- desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
- desc->desc4.constant_urb_entry_read_offset = 0;
- desc->desc4.constant_urb_entry_read_length = 4;
-
- /*kernel start*/
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
- kernel->bo);
- desc++;
- }
-
- dri_bo_unmap(bo);
-}
-
-static void
-gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- (void)mfc_context;
-}
-
-static void
-gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
- int index,
- int head_offset,
- int batchbuffer_offset,
- int head_size,
- int tail_size,
- int number_mb_cmds,
- int first_object,
- int last_object,
- int last_slice,
- int mb_x,
- int mb_y,
- int width_in_mbs,
- int qp,
- unsigned int ref_index[2])
-{
- BEGIN_BATCH(batch, 14);
-
- OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
- OUT_BATCH(batch, index);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
-
- /*inline data */
- OUT_BATCH(batch, head_offset);
- OUT_BATCH(batch, batchbuffer_offset);
- OUT_BATCH(batch,
- head_size << 16 |
- tail_size);
- OUT_BATCH(batch,
- number_mb_cmds << 16 |
- first_object << 2 |
- last_object << 1 |
- last_slice);
- OUT_BATCH(batch,
- mb_y << 8 |
- mb_x);
- OUT_BATCH(batch,
- qp << 16 |
- width_in_mbs);
- OUT_BATCH(batch, ref_index[0]);
- OUT_BATCH(batch, ref_index[1]);
-
- ADVANCE_BATCH(batch);
-}
-
-static void
-gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context,
- VAEncSliceParameterBufferH264 *slice_param,
- int head_offset,
- unsigned short head_size,
- unsigned short tail_size,
- int batchbuffer_offset,
- int qp,
- int last_slice)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int total_mbs = slice_param->num_macroblocks;
- int number_mb_cmds = 128;
- int starting_mb = 0;
- int last_object = 0;
- int first_object = 1;
- int i;
- int mb_x, mb_y;
- int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
-
- for (i = 0; i < total_mbs / number_mb_cmds; i++) {
- last_object = (total_mbs - starting_mb) == number_mb_cmds;
- mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
- mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
- assert(mb_x <= 255 && mb_y <= 255);
-
- starting_mb += number_mb_cmds;
-
- gen6_mfc_batchbuffer_emit_object_command(batch,
- index,
- head_offset,
- batchbuffer_offset,
- head_size,
- tail_size,
- number_mb_cmds,
- first_object,
- last_object,
- last_slice,
- mb_x,
- mb_y,
- width_in_mbs,
- qp,
- vme_context->ref_index_in_mb);
-
- if (first_object) {
- head_offset += head_size;
- batchbuffer_offset += head_size;
- }
-
- if (last_object) {
- head_offset += tail_size;
- batchbuffer_offset += tail_size;
- }
-
- batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
-
- first_object = 0;
- }
-
- if (!last_object) {
- last_object = 1;
- number_mb_cmds = total_mbs % number_mb_cmds;
- mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
- mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
- assert(mb_x <= 255 && mb_y <= 255);
- starting_mb += number_mb_cmds;
-
- gen6_mfc_batchbuffer_emit_object_command(batch,
- index,
- head_offset,
- batchbuffer_offset,
- head_size,
- tail_size,
- number_mb_cmds,
- first_object,
- last_object,
- last_slice,
- mb_x,
- mb_y,
- width_in_mbs,
- qp,
- vme_context->ref_index_in_mb);
- }
-}
-
-/*
- * return size in Owords (16bytes)
- */
-static int
-gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- int batchbuffer_offset)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
- int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- unsigned int tail_data[] = { 0x0, 0x0 };
- long head_offset;
- int old_used = intel_batchbuffer_used_size(slice_batch), used;
- unsigned short head_size, tail_size;
- int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int qp_slice;
-
- qp_slice = qp;
- if (rate_control_mode != VA_RC_CQP) {
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
- if (encode_state->slice_header_index[slice_index] == 0) {
- pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
- /* Use the adjusted qp when slice_header is generated by driver */
- qp_slice = qp;
- }
- }
-
- /* only support for 8-bit pixel bit-depth */
- assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
- assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
- assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
- assert(qp >= 0 && qp < 52);
-
- head_offset = old_used / 16;
- gen6_mfc_avc_slice_state(ctx,
- pPicParameter,
- pSliceParameter,
- encode_state,
- encoder_context,
- (rate_control_mode != VA_RC_CQP),
- qp_slice,
- slice_batch);
-
- if (slice_index == 0)
- intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
-
- intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
-
- intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- used = intel_batchbuffer_used_size(slice_batch);
- head_size = (used - old_used) / 16;
- old_used = used;
-
- /* tail */
- if (last_slice) {
- mfc_context->insert_object(ctx,
- encoder_context,
- tail_data,
- 2,
- 8,
- 2,
- 1,
- 1,
- 0,
- slice_batch);
- } else {
- mfc_context->insert_object(ctx,
- encoder_context,
- tail_data,
- 1,
- 8,
- 1,
- 1,
- 1,
- 0,
- slice_batch);
- }
-
- intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- used = intel_batchbuffer_used_size(slice_batch);
- tail_size = (used - old_used) / 16;
-
-
- gen6_mfc_avc_batchbuffer_slice_command(ctx,
- encoder_context,
- pSliceParameter,
- head_offset,
- head_size,
- tail_size,
- batchbuffer_offset,
- qp,
- last_slice);
-
- return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
-}
-
-static void
-gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- int i, size, offset = 0;
- intel_batchbuffer_start_atomic(batch, 0x4000);
- gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
-
- for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
- size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
- offset += size;
- }
-
- intel_batchbuffer_end_atomic(batch);
- intel_batchbuffer_flush(batch);
-}
-
-static void
-gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
- gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
- gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
- gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
-}
-
-static dri_bo *
-gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
- dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
-
- return mfc_context->mfc_batchbuffer_surface.bo;
-}
-
-
-
-static void
-gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- dri_bo *slice_batch_bo;
-
- if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
- fprintf(stderr, "Current VA driver don't support interlace mode!\n");
- assert(0);
- return;
- }
-
- if (encoder_context->soft_batch_force)
- slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
- else
- slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
-
- // begin programing
- intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
- intel_batchbuffer_emit_mi_flush(batch);
-
- // picture level programing
- gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
-
- BEGIN_BCS_BATCH(batch, 2);
- OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
- OUT_BCS_RELOC(batch,
- slice_batch_bo,
- I915_GEM_DOMAIN_COMMAND, 0,
- 0);
- ADVANCE_BCS_BATCH(batch);
-
- // end programing
- intel_batchbuffer_end_atomic(batch);
-
- dri_bo_unreference(slice_batch_bo);
-}
-
-VAStatus
-gen6_mfc_avc_encode_picture(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- int current_frame_bits_size;
- int sts;
-
- for (;;) {
- gen6_mfc_init(ctx, encode_state, encoder_context);
- intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
- /*Programing bcs pipeline*/
- gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
- gen6_mfc_run(ctx, encode_state, encoder_context);
- if (rate_control_mode == VA_RC_CBR || rate_control_mode == VA_RC_VBR) {
- gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
- sts = intel_mfc_brc_postpack(encode_state, encoder_context, current_frame_bits_size);
- if (sts == BRC_NO_HRD_VIOLATION) {
- intel_mfc_hrd_context_update(encode_state, mfc_context);
- break;
- }
- else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
- if (!mfc_context->hrd.violation_noted) {
- fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
- mfc_context->hrd.violation_noted = 1;
- }
- return VA_STATUS_SUCCESS;
- }
- } else {
- break;
- }
- }
-
- return VA_STATUS_SUCCESS;
-}
-
-VAStatus
-gen6_mfc_pipeline(VADriverContextP ctx,
- VAProfile profile,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- VAStatus vaStatus;
-
- switch (profile) {
- case VAProfileH264ConstrainedBaseline:
- case VAProfileH264Main:
- case VAProfileH264High:
- vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
- break;
-
- /* FIXME: add for other profile */
- default:
- vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
- break;
- }
-
- return vaStatus;
-}
-
-void
-gen6_mfc_context_destroy(void *context)
-{
- struct gen6_mfc_context *mfc_context = context;
- int i;
-
- dri_bo_unreference(mfc_context->post_deblocking_output.bo);
- mfc_context->post_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
- mfc_context->pre_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
- mfc_context->uncompressed_picture_source.bo = NULL;
-
- dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
- mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
-
- for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
- dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
- mfc_context->direct_mv_buffers[i].bo = NULL;
- }
-
- dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
- mfc_context->intra_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
- mfc_context->macroblock_status_buffer.bo = NULL;
-
- dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
- mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
- mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
-
-
- for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
- dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
- mfc_context->reference_surfaces[i].bo = NULL;
- }
-
- i965_gpe_context_destroy(&mfc_context->gpe_context);
-
- dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
- mfc_context->mfc_batchbuffer_surface.bo = NULL;
-
- dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->aux_batchbuffer_surface.bo = NULL;
-
- if (mfc_context->aux_batchbuffer)
- intel_batchbuffer_free(mfc_context->aux_batchbuffer);
-
- mfc_context->aux_batchbuffer = NULL;
-
- free(mfc_context);
-}
-
-Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
-
- if (!mfc_context)
- return False;
-
- mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
-
- mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
- mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
-
- mfc_context->gpe_context.curbe.length = 32 * 4;
-
- mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
- mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
- mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
- mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
- mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
-
- i965_gpe_load_kernels(ctx,
- &mfc_context->gpe_context,
- gen6_mfc_kernels,
- NUM_MFC_KERNEL);
-
- mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
- mfc_context->set_surface_state = gen6_mfc_surface_state;
- mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
- mfc_context->avc_img_state = gen6_mfc_avc_img_state;
- mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
- mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
- mfc_context->insert_object = gen6_mfc_avc_insert_object;
- mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
-
- encoder_context->mfc_context = mfc_context;
- encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
- encoder_context->mfc_pipeline = gen6_mfc_pipeline;
- encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
-
- return True;
-}
diff --git a/src/gen6_mfc.h b/src/gen6_mfc.h
deleted file mode 100644
index 7a5d940..0000000
--- a/src/gen6_mfc.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Copyright © 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Zhou Chang <chang.zhou@intel.com>
- *
- */
-
-#ifndef _GEN6_MFC_H_
-#define _GEN6_MFC_H_
-
-#include <drm.h>
-#include <i915_drm.h>
-#include <intel_bufmgr.h>
-
-#include "i965_encoder.h"
-#include "i965_gpe_utils.h"
-
-struct encode_state;
-
-#define MAX_MFC_REFERENCE_SURFACES 16
-#define NUM_MFC_DMV_BUFFERS 34
-
-#define INTRA_MB_FLAG_MASK 0x00002000
-
-/* The space required for slice header SLICE_STATE + header.
- * Is it enough? */
-#define SLICE_HEADER 80
-
-/* the space required for slice tail. */
-#define SLICE_TAIL 16
-
-
-#define MFC_BATCHBUFFER_AVC_INTRA 0
-#define MFC_BATCHBUFFER_AVC_INTER 1
-#define NUM_MFC_KERNEL 2
-
-#define BIND_IDX_VME_OUTPUT 0
-#define BIND_IDX_MFC_SLICE_HEADER 1
-#define BIND_IDX_MFC_BATCHBUFFER 2
-
-#define CMD_LEN_IN_OWORD 4
-
-#define BRC_CLIP(x, min, max) \
- { \
- x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
- }
-
-#define BRC_P_B_QP_DIFF 4
-#define BRC_I_P_QP_DIFF 2
-#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
-
-#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
-#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
-
-#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
-#define BRC_CY 0.1 /* weight for */
-#define BRC_CX_UNDERFLOW 5.
-#define BRC_CX_OVERFLOW -4.
-
-#define BRC_PI_0_5 1.5707963267948966192313216916398
-
-typedef enum {
- VME_V_PRED = 0,
- VME_H_PRED = 1,
- VME_DC_PRED = 2,
- VME_PL_PRED = 3,
-
- VME_MB_INTRA_MODE_COUNT
-} VME_MB_INTRA_PRED_MODE;
-
-typedef enum {
- PAK_DC_PRED = 0,
- PAK_V_PRED = 1,
- PAK_H_PRED = 2,
- PAK_TM_PRED = 3,
-
- PAK_MB_INTRA_MODE_COUNT
-} VP8_PAK_MB_INTRA_PRED_MODE;
-
-typedef enum
-{
- VME_B_V_PRED = 0,
- VME_B_H_PRED = 1,
- VME_B_DC_PRED = 2,
- VME_B_DL_PRED = 3,
- VME_B_DR_PRED = 4,
- VME_B_VR_PRED = 5,
- VME_B_HD_PRED = 6,
- VME_B_VL_PRED = 7,
- VME_B_HU_PRED = 8,
-
- VME_B_INTRA_MODE_COUNT
-} VME_BLOCK_INTRA_PRED_MODE;
-
-typedef enum
-{
- PAK_B_DC_PRED = 0,
- PAK_B_TM_PRED = 1,
- PAK_B_VE_PRED = 2,
- PAK_B_HE_PRED = 3,
- PAK_B_LD_PRED = 4,
- PAK_B_RD_PRED = 5,
- PAK_B_VR_PRED = 6,
- PAK_B_VL_PRED = 7,
- PAK_B_HD_PRED = 8,
- PAK_B_HU_PRED = 9,
-
- PAK_B_INTRA_MODE_COUNT
-} VP8_PAK_BLOCK_INTRA_PRED_MODE;
-
-typedef struct
-{
- int vme_intra_mb_mode;
- int vp8_pak_intra_mb_mode;
-} vp8_intra_mb_mode_map_t;
-
-typedef struct
-{
- int vme_intra_block_mode;
- int vp8_pak_intra_block_mode;
-} vp8_intra_block_mode_map_t;
-
-typedef enum _gen6_brc_status
-{
- BRC_NO_HRD_VIOLATION = 0,
- BRC_UNDERFLOW = 1,
- BRC_OVERFLOW = 2,
- BRC_UNDERFLOW_WITH_MAX_QP = 3,
- BRC_OVERFLOW_WITH_MIN_QP = 4,
-} gen6_brc_status;
-
-struct gen6_mfc_avc_surface_aux
-{
- dri_bo *dmv_top;
- dri_bo *dmv_bottom;
-};
-
-struct gen6_mfc_context
-{
- struct {
- unsigned int width;
- unsigned int height;
- unsigned int w_pitch;
- unsigned int h_pitch;
- } surface_state;
-
- //MFX_PIPE_BUF_ADDR_STATE
- struct {
- dri_bo *bo;
- } post_deblocking_output; //OUTPUT: reconstructed picture
-
- struct {
- dri_bo *bo;
- } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked
-
- struct {
- dri_bo *bo;
- } uncompressed_picture_source; //INPUT: original compressed image
-
- struct {
- dri_bo *bo;
- } intra_row_store_scratch_buffer; //INTERNAL:
-
- struct {
- dri_bo *bo;
- } macroblock_status_buffer; //INTERNAL:
-
- struct {
- dri_bo *bo;
- } deblocking_filter_row_store_scratch_buffer; //INTERNAL:
-
- struct {
- dri_bo *bo;
- } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces
-
- //MFX_IND_OBJ_BASE_ADDR_STATE
- struct{
- dri_bo *bo;
- } mfc_indirect_mv_object; //INPUT: the blocks' mv info
-
- struct {
- dri_bo *bo;
- int offset;
- int end_offset;
- } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
-
- //MFX_BSP_BUF_BASE_ADDR_STATE
- struct {
- dri_bo *bo;
- } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
-
- //MFX_AVC_DIRECTMODE_STATE
- struct {
- dri_bo *bo;
- } direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output
-
- //Bit rate tracking context
- struct {
- unsigned int MaxQpNegModifier;
- unsigned int MaxQpPosModifier;
- unsigned char Correct[6];
- unsigned char GrowInit;
- unsigned char GrowResistance;
- unsigned char ShrinkInit;
- unsigned char ShrinkResistance;
- } bit_rate_control_context[3]; //INTERNAL: for I, P, B frames
-
- struct {
- int mode;
- int gop_nums[MAX_MFC_REFERENCE_SURFACES][3];
- int target_frame_size[MAX_TEMPORAL_LAYERS][3]; // I,P,B
- int qp_prime_y[MAX_TEMPORAL_LAYERS][3];
- double bits_per_frame[MAX_TEMPORAL_LAYERS];
- double qpf_rounding_accumulator[MAX_TEMPORAL_LAYERS];
- int bits_prev_frame[MAX_TEMPORAL_LAYERS];
- int prev_slice_type[MAX_TEMPORAL_LAYERS];
- } brc;
-
- struct {
- double current_buffer_fullness[MAX_TEMPORAL_LAYERS];
- double target_buffer_fullness[MAX_TEMPORAL_LAYERS];
- double buffer_capacity[MAX_TEMPORAL_LAYERS];
- unsigned int buffer_size[MAX_TEMPORAL_LAYERS];
- unsigned int violation_noted;
- } hrd;
-
- //HRD control context
- struct {
- int i_bit_rate_value;
-
- int i_initial_cpb_removal_delay;
- int i_cpb_removal_delay;
-
- int i_frame_number;
-
- int i_initial_cpb_removal_delay_length;
- int i_cpb_removal_delay_length;
- int i_dpb_output_delay_length;
- }vui_hrd;
-
- struct {
- unsigned char *vp8_frame_header;
- unsigned int frame_header_bit_count;
- unsigned int frame_header_qindex_update_pos;
- unsigned int frame_header_lf_update_pos;
- unsigned int frame_header_token_update_pos;
- unsigned int frame_header_bin_mv_upate_pos;
-
- unsigned int intermediate_partition_offset[8];
- unsigned int intermediate_buffer_max_size;
- unsigned int final_frame_byte_offset;
-
- unsigned char mb_segment_tree_probs[3];
- unsigned char y_mode_probs[4];
- unsigned char uv_mode_probs[3];
- unsigned char mv_probs[2][19];
-
- unsigned char prob_skip_false;
- unsigned char prob_intra;
- unsigned char prob_last;
- unsigned char prob_gf;
-
- dri_bo *frame_header_bo;
- dri_bo *intermediate_bo;
- dri_bo *final_frame_bo;
- dri_bo *stream_out_bo;
- dri_bo *coeff_probs_stream_in_bo;
- dri_bo *token_statistics_bo;
- dri_bo *mpc_row_store_bo;
- }vp8_state;
-
- //"buffered_QMatrix" will be used to buffer the QMatrix if the app sends one.
- // Or else, we will load a default QMatrix from the driver for JPEG encode.
- VAQMatrixBufferJPEG buffered_qmatrix;
- struct i965_gpe_context gpe_context;
- struct i965_buffer_surface mfc_batchbuffer_surface;
- struct intel_batchbuffer *aux_batchbuffer;
- struct i965_buffer_surface aux_batchbuffer_surface;
-
- void (*pipe_mode_select)(VADriverContextP ctx,
- int standard_select,
- struct intel_encoder_context *encoder_context);
- void (*set_surface_state)(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context);
- void (*ind_obj_base_addr_state)(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context);
- void (*avc_img_state)(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
- void (*avc_qm_state)(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
- void (*avc_fqm_state)(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
- void (*insert_object)(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context,
- unsigned int *insert_data,
- int lenght_in_dws, int data_bits_in_last_dw,
- int skip_emul_byte_count,
- int is_last_header, int is_end_of_slice,
- int emulation_flag,
- struct intel_batchbuffer *batch);
- void (*buffer_suface_setup)(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_buffer_surface *buffer_surface,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset);
-};
-
-VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
- VAProfile profile,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-void gen6_mfc_context_destroy(void *context);
-
-extern
-Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern
-Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern
-Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-
-extern int intel_mfc_update_hrd(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits);
-
-extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits);
-
-extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
- struct gen6_mfc_context *mfc_context);
-
-extern int intel_mfc_interlace_check(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- struct intel_batchbuffer *slice_batch);
-
-extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern int intel_avc_enc_slice_type_fixup(int type);
-
-extern void
-intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern
-Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern void
-intel_avc_slice_insert_packed_data(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- struct intel_batchbuffer *slice_batch);
-
-extern
-Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-#endif /* _GEN6_MFC_BCS_H_ */
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
deleted file mode 100644
index 0d21a11..0000000
--- a/src/gen6_mfc_common.c
+++ /dev/null
@@ -1,2394 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Xiang Haihao <haihao.xiang@intel.com>
- * Zhao Yakui <yakui.zhao@intel.com>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include <math.h>
-
-#include "intel_batchbuffer.h"
-#include "i965_defines.h"
-#include "i965_structs.h"
-#include "i965_drv_video.h"
-#include "i965_encoder.h"
-#include "i965_encoder_utils.h"
-#include "gen6_mfc.h"
-#include "gen6_vme.h"
-#include "gen9_mfc.h"
-#include "intel_media.h"
-
-#ifndef HAVE_LOG2F
-#define log2f(x) (logf(x)/(float)M_LN2)
-#endif
-
-int intel_avc_enc_slice_type_fixup(int slice_type)
-{
- if (slice_type == SLICE_TYPE_SP ||
- slice_type == SLICE_TYPE_P)
- slice_type = SLICE_TYPE_P;
- else if (slice_type == SLICE_TYPE_SI ||
- slice_type == SLICE_TYPE_I)
- slice_type = SLICE_TYPE_I;
- else {
- if (slice_type != SLICE_TYPE_B)
- WARN_ONCE("Invalid slice type for H.264 encoding!\n");
-
- slice_type = SLICE_TYPE_B;
- }
-
- return slice_type;
-}
-
-static void
-intel_mfc_bit_rate_control_context_init(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int i;
-
- for(i = 0 ; i < 3; i++) {
- mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6;
- mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6;
- mfc_context->bit_rate_control_context[i].GrowInit = 6;
- mfc_context->bit_rate_control_context[i].GrowResistance = 4;
- mfc_context->bit_rate_control_context[i].ShrinkInit = 6;
- mfc_context->bit_rate_control_context[i].ShrinkResistance = 4;
-
- mfc_context->bit_rate_control_context[i].Correct[0] = 8;
- mfc_context->bit_rate_control_context[i].Correct[1] = 4;
- mfc_context->bit_rate_control_context[i].Correct[2] = 2;
- mfc_context->bit_rate_control_context[i].Correct[3] = 2;
- mfc_context->bit_rate_control_context[i].Correct[4] = 4;
- mfc_context->bit_rate_control_context[i].Correct[5] = 8;
- }
-}
-
-static void intel_mfc_brc_init(struct encode_state *encode_state,
- struct intel_encoder_context* encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- double bitrate, framerate;
- double frame_per_bits = 8 * 3 * encoder_context->frame_width_in_pixel * encoder_context->frame_height_in_pixel / 2;
- double qp1_size = 0.1 * frame_per_bits;
- double qp51_size = 0.001 * frame_per_bits;
- int min_qp = MAX(1, encoder_context->brc.min_qp);
- double bpf, factor, hrd_factor;
- int inum = encoder_context->brc.num_iframes_in_gop,
- pnum = encoder_context->brc.num_pframes_in_gop,
- bnum = encoder_context->brc.num_bframes_in_gop; /* Gop structure: number of I, P, B frames in the Gop. */
- int intra_period = encoder_context->brc.gop_size;
- int i;
-
- if (encoder_context->layer.num_layers > 1)
- qp1_size = 0.15 * frame_per_bits;
-
- mfc_context->brc.mode = encoder_context->rate_control_mode;
-
- mfc_context->hrd.violation_noted = 0;
-
- for (i = 0; i < encoder_context->layer.num_layers; i++) {
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_I] = 26;
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P] = 26;
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_B] = 26;
-
- if (i == 0) {
- bitrate = encoder_context->brc.bits_per_second[0];
- framerate = (double)encoder_context->brc.framerate[0].num / (double)encoder_context->brc.framerate[0].den;
- } else {
- bitrate = (encoder_context->brc.bits_per_second[i] - encoder_context->brc.bits_per_second[i - 1]);
- framerate = ((double)encoder_context->brc.framerate[i].num / (double)encoder_context->brc.framerate[i].den) -
- ((double)encoder_context->brc.framerate[i - 1].num / (double)encoder_context->brc.framerate[i - 1].den);
- }
-
- if (mfc_context->brc.mode == VA_RC_VBR && encoder_context->brc.target_percentage[i])
- bitrate = bitrate * encoder_context->brc.target_percentage[i] / 100;
-
- if (i == encoder_context->layer.num_layers - 1)
- factor = 1.0;
- else {
- factor = ((double)encoder_context->brc.framerate[i].num / (double)encoder_context->brc.framerate[i].den) /
- ((double)encoder_context->brc.framerate[i - 1].num / (double)encoder_context->brc.framerate[i - 1].den);
- }
-
- hrd_factor = (double)bitrate / encoder_context->brc.bits_per_second[encoder_context->layer.num_layers - 1];
-
- mfc_context->hrd.buffer_size[i] = (unsigned int)(encoder_context->brc.hrd_buffer_size * hrd_factor);
- mfc_context->hrd.current_buffer_fullness[i] =
- (double)(encoder_context->brc.hrd_initial_buffer_fullness < encoder_context->brc.hrd_buffer_size) ?
- encoder_context->brc.hrd_initial_buffer_fullness : encoder_context->brc.hrd_buffer_size / 2.;
- mfc_context->hrd.current_buffer_fullness[i] *= hrd_factor;
- mfc_context->hrd.target_buffer_fullness[i] = (double)encoder_context->brc.hrd_buffer_size * hrd_factor / 2.;
- mfc_context->hrd.buffer_capacity[i] = (double)encoder_context->brc.hrd_buffer_size * hrd_factor / qp1_size;
-
- if (encoder_context->layer.num_layers > 1) {
- if (i == 0) {
- intra_period = (int)(encoder_context->brc.gop_size * factor);
- inum = 1;
- pnum = (int)(encoder_context->brc.num_pframes_in_gop * factor);
- bnum = intra_period - inum - pnum;
- } else {
- intra_period = (int)(encoder_context->brc.gop_size * factor) - intra_period;
- inum = 0;
- pnum = (int)(encoder_context->brc.num_pframes_in_gop * factor) - pnum;
- bnum = intra_period - inum - pnum;
- }
- }
-
- mfc_context->brc.gop_nums[i][SLICE_TYPE_I] = inum;
- mfc_context->brc.gop_nums[i][SLICE_TYPE_P] = pnum;
- mfc_context->brc.gop_nums[i][SLICE_TYPE_B] = bnum;
-
- mfc_context->brc.target_frame_size[i][SLICE_TYPE_I] = (int)((double)((bitrate * intra_period)/framerate) /
- (double)(inum + BRC_PWEIGHT * pnum + BRC_BWEIGHT * bnum));
- mfc_context->brc.target_frame_size[i][SLICE_TYPE_P] = BRC_PWEIGHT * mfc_context->brc.target_frame_size[i][SLICE_TYPE_I];
- mfc_context->brc.target_frame_size[i][SLICE_TYPE_B] = BRC_BWEIGHT * mfc_context->brc.target_frame_size[i][SLICE_TYPE_I];
-
- bpf = mfc_context->brc.bits_per_frame[i] = bitrate/framerate;
-
- if (encoder_context->brc.initial_qp) {
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_I] = encoder_context->brc.initial_qp;
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P] = encoder_context->brc.initial_qp;
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_B] = encoder_context->brc.initial_qp;
- } else {
- if ((bpf > qp51_size) && (bpf < qp1_size)) {
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P] = 51 - 50*(bpf - qp51_size)/(qp1_size - qp51_size);
- }
- else if (bpf >= qp1_size)
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P] = 1;
- else if (bpf <= qp51_size)
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P] = 51;
-
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_I] = mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P];
- mfc_context->brc.qp_prime_y[i][SLICE_TYPE_B] = mfc_context->brc.qp_prime_y[i][SLICE_TYPE_I];
- }
-
- BRC_CLIP(mfc_context->brc.qp_prime_y[i][SLICE_TYPE_I], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[i][SLICE_TYPE_P], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[i][SLICE_TYPE_B], min_qp, 51);
- }
-}
-
-int intel_mfc_update_hrd(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int layer_id = encoder_context->layer.curr_frame_layer_id;
- double prev_bf = mfc_context->hrd.current_buffer_fullness[layer_id];
-
- mfc_context->hrd.current_buffer_fullness[layer_id] -= frame_bits;
-
- if (mfc_context->hrd.buffer_size[layer_id] > 0 && mfc_context->hrd.current_buffer_fullness[layer_id] <= 0.) {
- mfc_context->hrd.current_buffer_fullness[layer_id] = prev_bf;
- return BRC_UNDERFLOW;
- }
-
- mfc_context->hrd.current_buffer_fullness[layer_id] += mfc_context->brc.bits_per_frame[layer_id];
- if (mfc_context->hrd.buffer_size[layer_id] > 0 && mfc_context->hrd.current_buffer_fullness[layer_id] > mfc_context->hrd.buffer_size[layer_id]) {
- if (mfc_context->brc.mode == VA_RC_VBR)
- mfc_context->hrd.current_buffer_fullness[layer_id] = mfc_context->hrd.buffer_size[layer_id];
- else {
- mfc_context->hrd.current_buffer_fullness[layer_id] = prev_bf;
- return BRC_OVERFLOW;
- }
- }
- return BRC_NO_HRD_VIOLATION;
-}
-
-static int intel_mfc_brc_postpack_cbr(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- gen6_brc_status sts = BRC_NO_HRD_VIOLATION;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int slicetype = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int curr_frame_layer_id, next_frame_layer_id;
- int qpi, qpp, qpb;
- int qp; // quantizer of previously encoded slice of current type
- int qpn; // predicted quantizer for next frame of current type in integer format
- double qpf; // predicted quantizer for next frame of current type in float format
- double delta_qp; // QP correction
- int min_qp = MAX(1, encoder_context->brc.min_qp);
- int target_frame_size, frame_size_next;
- /* Notes:
- * x - how far we are from HRD buffer borders
- * y - how far we are from target HRD buffer fullness
- */
- double x, y;
- double frame_size_alpha;
-
- if (encoder_context->layer.num_layers < 2 || encoder_context->layer.size_frame_layer_ids == 0) {
- curr_frame_layer_id = 0;
- next_frame_layer_id = 0;
- } else {
- curr_frame_layer_id = encoder_context->layer.curr_frame_layer_id;
- next_frame_layer_id = encoder_context->layer.frame_layer_ids[encoder_context->num_frames_in_sequence % encoder_context->layer.size_frame_layer_ids];
- }
-
- /* checking wthether HRD compliance first */
- sts = intel_mfc_update_hrd(encode_state, encoder_context, frame_bits);
-
- if (sts == BRC_NO_HRD_VIOLATION) { // no HRD violation
- /* nothing */
- } else {
- next_frame_layer_id = curr_frame_layer_id;
- }
-
- mfc_context->brc.bits_prev_frame[curr_frame_layer_id] = frame_bits;
- frame_bits = mfc_context->brc.bits_prev_frame[next_frame_layer_id];
-
- mfc_context->brc.prev_slice_type[curr_frame_layer_id] = slicetype;
- slicetype = mfc_context->brc.prev_slice_type[next_frame_layer_id];
-
- /* 0 means the next frame is the first frame of next layer */
- if (frame_bits == 0)
- return sts;
-
- qpi = mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_I];
- qpp = mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_P];
- qpb = mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_B];
-
- qp = mfc_context->brc.qp_prime_y[next_frame_layer_id][slicetype];
-
- target_frame_size = mfc_context->brc.target_frame_size[next_frame_layer_id][slicetype];
- if (mfc_context->hrd.buffer_capacity[next_frame_layer_id] < 5)
- frame_size_alpha = 0;
- else
- frame_size_alpha = (double)mfc_context->brc.gop_nums[next_frame_layer_id][slicetype];
- if (frame_size_alpha > 30) frame_size_alpha = 30;
- frame_size_next = target_frame_size + (double)(target_frame_size - frame_bits) /
- (double)(frame_size_alpha + 1.);
-
- /* frame_size_next: avoiding negative number and too small value */
- if ((double)frame_size_next < (double)(target_frame_size * 0.25))
- frame_size_next = (int)((double)target_frame_size * 0.25);
-
- qpf = (double)qp * target_frame_size / frame_size_next;
- qpn = (int)(qpf + 0.5);
-
- if (qpn == qp) {
- /* setting qpn we round qpf making mistakes: now we are trying to compensate this */
- mfc_context->brc.qpf_rounding_accumulator[next_frame_layer_id] += qpf - qpn;
- if (mfc_context->brc.qpf_rounding_accumulator[next_frame_layer_id] > 1.0) {
- qpn++;
- mfc_context->brc.qpf_rounding_accumulator[next_frame_layer_id] = 0.;
- } else if (mfc_context->brc.qpf_rounding_accumulator[next_frame_layer_id] < -1.0) {
- qpn--;
- mfc_context->brc.qpf_rounding_accumulator[next_frame_layer_id] = 0.;
- }
- }
- /* making sure that QP is not changing too fast */
- if ((qpn - qp) > BRC_QP_MAX_CHANGE) qpn = qp + BRC_QP_MAX_CHANGE;
- else if ((qpn - qp) < -BRC_QP_MAX_CHANGE) qpn = qp - BRC_QP_MAX_CHANGE;
- /* making sure that with QP predictions we did do not leave QPs range */
- BRC_CLIP(qpn, 1, 51);
-
- /* calculating QP delta as some function*/
- x = mfc_context->hrd.target_buffer_fullness[next_frame_layer_id] - mfc_context->hrd.current_buffer_fullness[next_frame_layer_id];
- if (x > 0) {
- x /= mfc_context->hrd.target_buffer_fullness[next_frame_layer_id];
- y = mfc_context->hrd.current_buffer_fullness[next_frame_layer_id];
- }
- else {
- x /= (mfc_context->hrd.buffer_size[next_frame_layer_id] - mfc_context->hrd.target_buffer_fullness[next_frame_layer_id]);
- y = mfc_context->hrd.buffer_size[next_frame_layer_id] - mfc_context->hrd.current_buffer_fullness[next_frame_layer_id];
- }
- if (y < 0.01) y = 0.01;
- if (x > 1) x = 1;
- else if (x < -1) x = -1;
-
- delta_qp = BRC_QP_MAX_CHANGE*exp(-1/y)*sin(BRC_PI_0_5 * x);
- qpn = (int)(qpn + delta_qp + 0.5);
-
- /* making sure that with QP predictions we did do not leave QPs range */
- BRC_CLIP(qpn, min_qp, 51);
-
- if (sts == BRC_NO_HRD_VIOLATION) { // no HRD violation
- /* correcting QPs of slices of other types */
- if (slicetype == SLICE_TYPE_P) {
- if (abs(qpn + BRC_P_B_QP_DIFF - qpb) > 2)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_B] += (qpn + BRC_P_B_QP_DIFF - qpb) >> 1;
- if (abs(qpn - BRC_I_P_QP_DIFF - qpi) > 2)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_I] += (qpn - BRC_I_P_QP_DIFF - qpi) >> 1;
- } else if (slicetype == SLICE_TYPE_I) {
- if (abs(qpn + BRC_I_B_QP_DIFF - qpb) > 4)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_B] += (qpn + BRC_I_B_QP_DIFF - qpb) >> 2;
- if (abs(qpn + BRC_I_P_QP_DIFF - qpp) > 2)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_P] += (qpn + BRC_I_P_QP_DIFF - qpp) >> 2;
- } else { // SLICE_TYPE_B
- if (abs(qpn - BRC_P_B_QP_DIFF - qpp) > 2)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_P] += (qpn - BRC_P_B_QP_DIFF - qpp) >> 1;
- if (abs(qpn - BRC_I_B_QP_DIFF - qpi) > 4)
- mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_I] += (qpn - BRC_I_B_QP_DIFF - qpi) >> 2;
- }
- BRC_CLIP(mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_I], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_P], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[next_frame_layer_id][SLICE_TYPE_B], min_qp, 51);
- } else if (sts == BRC_UNDERFLOW) { // underflow
- if (qpn <= qp) qpn = qp + 1;
- if (qpn > 51) {
- qpn = 51;
- sts = BRC_UNDERFLOW_WITH_MAX_QP; //underflow with maxQP
- }
- } else if (sts == BRC_OVERFLOW) {
- if (qpn >= qp) qpn = qp - 1;
- if (qpn < min_qp) { // overflow with minQP
- qpn = min_qp;
- sts = BRC_OVERFLOW_WITH_MIN_QP; // bit stuffing to be done
- }
- }
-
- mfc_context->brc.qp_prime_y[next_frame_layer_id][slicetype] = qpn;
-
- return sts;
-}
-
-static int intel_mfc_brc_postpack_vbr(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- gen6_brc_status sts;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int *qp = mfc_context->brc.qp_prime_y[0];
- int min_qp = MAX(1, encoder_context->brc.min_qp);
- int qp_delta, large_frame_adjustment;
-
- // This implements a simple reactive VBR rate control mode for single-layer H.264. The primary
- // aim here is to avoid the problematic behaviour that the CBR rate controller displays on
- // scene changes, where the QP can get pushed up by a large amount in a short period and
- // compromise the quality of following frames to a very visible degree.
- // The main idea, then, is to try to keep the HRD buffering above the target level most of the
- // time, so that when a large frame is generated (on a scene change or when the stream
- // complexity increases) we have plenty of slack to be able to encode the more difficult region
- // without compromising quality immediately on the following frames. It is optimistic about
- // the complexity of future frames, so even after generating one or more large frames on a
- // significant change it will try to keep the QP at its current level until the HRD buffer
- // bounds force a change to maintain the intended rate.
-
- sts = intel_mfc_update_hrd(encode_state, encoder_context, frame_bits);
-
- // This adjustment is applied to increase the QP by more than we normally would if a very
- // large frame is encountered and we are in danger of running out of slack.
- large_frame_adjustment = rint(2.0 * log(frame_bits / mfc_context->brc.target_frame_size[0][slice_type]));
-
- if (sts == BRC_UNDERFLOW) {
- // The frame is far too big and we don't have the bits available to send it, so it will
- // have to be re-encoded at a higher QP.
- qp_delta = +2;
- if (frame_bits > mfc_context->brc.target_frame_size[0][slice_type])
- qp_delta += large_frame_adjustment;
- } else if (sts == BRC_OVERFLOW) {
- // The frame is very small and we are now overflowing the HRD buffer. Currently this case
- // does not occur because we ignore overflow in VBR mode.
- assert(0 && "Overflow in VBR mode");
- } else if (frame_bits <= mfc_context->brc.target_frame_size[0][slice_type]) {
- // The frame is smaller than the average size expected for this frame type.
- if (mfc_context->hrd.current_buffer_fullness[0] >
- (mfc_context->hrd.target_buffer_fullness[0] + mfc_context->hrd.buffer_size[0]) / 2.0) {
- // We currently have lots of bits available, so decrease the QP slightly for the next
- // frame.
- qp_delta = -1;
- } else {
- // The HRD buffer fullness is increasing, so do nothing. (We may be under the target
- // level here, but are moving in the right direction.)
- qp_delta = 0;
- }
- } else {
- // The frame is larger than the average size expected for this frame type.
- if (mfc_context->hrd.current_buffer_fullness[0] > mfc_context->hrd.target_buffer_fullness[0]) {
- // We are currently over the target level, so do nothing.
- qp_delta = 0;
- } else if (mfc_context->hrd.current_buffer_fullness[0] > mfc_context->hrd.target_buffer_fullness[0] / 2.0) {
- // We are under the target level, but not critically. Increase the QP by one step if
- // continuing like this would underflow soon (currently within one second).
- if (mfc_context->hrd.current_buffer_fullness[0] /
- (double)(frame_bits - mfc_context->brc.target_frame_size[0][slice_type] + 1) <
- ((double)encoder_context->brc.framerate[0].num / (double)encoder_context->brc.framerate[0].den))
- qp_delta = +1;
- else
- qp_delta = 0;
- } else {
- // We are a long way under the target level. Always increase the QP, possibly by a
- // larger amount dependent on how big the frame we just made actually was.
- qp_delta = +1 + large_frame_adjustment;
- }
- }
-
- switch (slice_type) {
- case SLICE_TYPE_I:
- qp[SLICE_TYPE_I] += qp_delta;
- qp[SLICE_TYPE_P] = qp[SLICE_TYPE_I] + BRC_I_P_QP_DIFF;
- qp[SLICE_TYPE_B] = qp[SLICE_TYPE_I] + BRC_I_B_QP_DIFF;
- break;
- case SLICE_TYPE_P:
- qp[SLICE_TYPE_P] += qp_delta;
- qp[SLICE_TYPE_I] = qp[SLICE_TYPE_P] - BRC_I_P_QP_DIFF;
- qp[SLICE_TYPE_B] = qp[SLICE_TYPE_P] + BRC_P_B_QP_DIFF;
- break;
- case SLICE_TYPE_B:
- qp[SLICE_TYPE_B] += qp_delta;
- qp[SLICE_TYPE_I] = qp[SLICE_TYPE_B] - BRC_I_B_QP_DIFF;
- qp[SLICE_TYPE_P] = qp[SLICE_TYPE_B] - BRC_P_B_QP_DIFF;
- break;
- }
- BRC_CLIP(mfc_context->brc.qp_prime_y[0][SLICE_TYPE_I], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[0][SLICE_TYPE_P], min_qp, 51);
- BRC_CLIP(mfc_context->brc.qp_prime_y[0][SLICE_TYPE_B], min_qp, 51);
-
- if (sts == BRC_UNDERFLOW && qp[slice_type] == 51)
- sts = BRC_UNDERFLOW_WITH_MAX_QP;
- if (sts == BRC_OVERFLOW && qp[slice_type] == min_qp)
- sts = BRC_OVERFLOW_WITH_MIN_QP;
-
- return sts;
-}
-
-int intel_mfc_brc_postpack(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int frame_bits)
-{
- switch (encoder_context->rate_control_mode) {
- case VA_RC_CBR:
- return intel_mfc_brc_postpack_cbr(encode_state, encoder_context, frame_bits);
- case VA_RC_VBR:
- return intel_mfc_brc_postpack_vbr(encode_state, encoder_context, frame_bits);
- }
- assert(0 && "Invalid RC mode");
-}
-
-static void intel_mfc_hrd_context_init(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- int target_bit_rate = encoder_context->brc.bits_per_second[encoder_context->layer.num_layers - 1];
-
- // current we only support CBR mode.
- if (rate_control_mode == VA_RC_CBR) {
- mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10;
- mfc_context->vui_hrd.i_initial_cpb_removal_delay = ((target_bit_rate * 8) >> 10) * 0.5 * 1024 / target_bit_rate * 90000;
- mfc_context->vui_hrd.i_cpb_removal_delay = 2;
- mfc_context->vui_hrd.i_frame_number = 0;
-
- mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24;
- mfc_context->vui_hrd.i_cpb_removal_delay_length = 24;
- mfc_context->vui_hrd.i_dpb_output_delay_length = 24;
- }
-
-}
-
-void
-intel_mfc_hrd_context_update(struct encode_state *encode_state,
- struct gen6_mfc_context *mfc_context)
-{
- mfc_context->vui_hrd.i_frame_number++;
-}
-
-int intel_mfc_interlace_check(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncSliceParameterBufferH264 *pSliceParameter;
- int i;
- int mbCount = 0;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
-
- for (i = 0; i < encode_state->num_slice_params_ext; i++) {
- pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[i]->buffer;
- mbCount += pSliceParameter->num_macroblocks;
- }
-
- if ( mbCount == ( width_in_mbs * height_in_mbs ) )
- return 0;
-
- return 1;
-}
-
-void intel_mfc_brc_prepare(struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
-
- if (encoder_context->codec != CODEC_H264 &&
- encoder_context->codec != CODEC_H264_MVC)
- return;
-
- if (rate_control_mode != VA_RC_CQP) {
- /*Programing bit rate control */
- if (encoder_context->brc.need_reset) {
- intel_mfc_bit_rate_control_context_init(encode_state, encoder_context);
- intel_mfc_brc_init(encode_state, encoder_context);
- }
-
- /*Programing HRD control */
- if (encoder_context->brc.need_reset)
- intel_mfc_hrd_context_init(encode_state, encoder_context);
- }
-}
-
-void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- struct intel_batchbuffer *slice_batch)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- unsigned int skip_emul_byte_cnt;
-
- if (encode_state->packed_header_data[idx]) {
- VAEncPackedHeaderParameterBuffer *param = NULL;
- unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
- unsigned int length_in_bits;
-
- assert(encode_state->packed_header_param[idx]);
- param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
- length_in_bits = param->bit_length;
-
- skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
- mfc_context->insert_object(ctx,
- encoder_context,
- header_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- skip_emul_byte_cnt,
- 0,
- 0,
- !param->has_emulation_bytes,
- slice_batch);
- }
-
- idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
-
- if (encode_state->packed_header_data[idx]) {
- VAEncPackedHeaderParameterBuffer *param = NULL;
- unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
- unsigned int length_in_bits;
-
- assert(encode_state->packed_header_param[idx]);
- param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
- length_in_bits = param->bit_length;
-
- skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
-
- mfc_context->insert_object(ctx,
- encoder_context,
- header_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- skip_emul_byte_cnt,
- 0,
- 0,
- !param->has_emulation_bytes,
- slice_batch);
- }
-
- idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
-
- if (encode_state->packed_header_data[idx]) {
- VAEncPackedHeaderParameterBuffer *param = NULL;
- unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
- unsigned int length_in_bits;
-
- assert(encode_state->packed_header_param[idx]);
- param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
- length_in_bits = param->bit_length;
-
- skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
- mfc_context->insert_object(ctx,
- encoder_context,
- header_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- skip_emul_byte_cnt,
- 0,
- 0,
- !param->has_emulation_bytes,
- slice_batch);
- } else if (rate_control_mode == VA_RC_CBR) {
- // this is frist AU
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- unsigned char *sei_data = NULL;
-
- int length_in_bits = build_avc_sei_buffer_timing(
- mfc_context->vui_hrd.i_initial_cpb_removal_delay_length,
- mfc_context->vui_hrd.i_initial_cpb_removal_delay,
- 0,
- mfc_context->vui_hrd.i_cpb_removal_delay_length, mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number,
- mfc_context->vui_hrd.i_dpb_output_delay_length,
- 0,
- &sei_data);
- mfc_context->insert_object(ctx,
- encoder_context,
- (unsigned int *)sei_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- 5,
- 0,
- 0,
- 1,
- slice_batch);
- free(sei_data);
- }
-}
-
-VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct object_surface *obj_surface;
- struct object_buffer *obj_buffer;
- GenAvcSurface *gen6_avc_surface;
- dri_bo *bo;
- VAStatus vaStatus = VA_STATUS_SUCCESS;
- int i, j, enable_avc_ildb = 0;
- VAEncSliceParameterBufferH264 *slice_param;
- struct i965_coded_buffer_segment *coded_buffer_segment;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
-
- if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
- }
-
- for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
- assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
- slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
-
- for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
- assert((slice_param->slice_type == SLICE_TYPE_I) ||
- (slice_param->slice_type == SLICE_TYPE_SI) ||
- (slice_param->slice_type == SLICE_TYPE_P) ||
- (slice_param->slice_type == SLICE_TYPE_SP) ||
- (slice_param->slice_type == SLICE_TYPE_B));
-
- if (slice_param->disable_deblocking_filter_idc != 1) {
- enable_avc_ildb = 1;
- break;
- }
-
- slice_param++;
- }
- }
-
- /*Setup all the input&output object*/
-
- /* Setup current frame and current direct mv buffer*/
- obj_surface = encode_state->reconstructed_object;
- i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
-
- if ( obj_surface->private_data == NULL) {
- gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
- assert(gen6_avc_surface);
- gen6_avc_surface->dmv_top =
- dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 68 * width_in_mbs * height_in_mbs,
- 64);
- gen6_avc_surface->dmv_bottom =
- dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 68 * width_in_mbs * height_in_mbs,
- 64);
- assert(gen6_avc_surface->dmv_top);
- assert(gen6_avc_surface->dmv_bottom);
- obj_surface->private_data = (void *)gen6_avc_surface;
- obj_surface->free_private_data = (void *)gen_free_avc_surface;
- }
- gen6_avc_surface = (GenAvcSurface *) obj_surface->private_data;
- mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
- mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
- dri_bo_reference(gen6_avc_surface->dmv_top);
- dri_bo_reference(gen6_avc_surface->dmv_bottom);
-
- if (enable_avc_ildb) {
- mfc_context->post_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(mfc_context->post_deblocking_output.bo);
- } else {
- mfc_context->pre_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(mfc_context->pre_deblocking_output.bo);
- }
-
- mfc_context->surface_state.width = obj_surface->orig_width;
- mfc_context->surface_state.height = obj_surface->orig_height;
- mfc_context->surface_state.w_pitch = obj_surface->width;
- mfc_context->surface_state.h_pitch = obj_surface->height;
-
- /* Setup reference frames and direct mv buffers*/
- for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
- obj_surface = encode_state->reference_objects[i];
-
- if (obj_surface && obj_surface->bo) {
- mfc_context->reference_surfaces[i].bo = obj_surface->bo;
- dri_bo_reference(obj_surface->bo);
-
- /* Check DMV buffer */
- if ( obj_surface->private_data == NULL) {
-
- gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
- assert(gen6_avc_surface);
- gen6_avc_surface->dmv_top =
- dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 68 * width_in_mbs * height_in_mbs,
- 64);
- gen6_avc_surface->dmv_bottom =
- dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 68 * width_in_mbs * height_in_mbs,
- 64);
- assert(gen6_avc_surface->dmv_top);
- assert(gen6_avc_surface->dmv_bottom);
- obj_surface->private_data = gen6_avc_surface;
- obj_surface->free_private_data = gen_free_avc_surface;
- }
-
- gen6_avc_surface = (GenAvcSurface *) obj_surface->private_data;
- /* Setup DMV buffer */
- mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
- mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
- dri_bo_reference(gen6_avc_surface->dmv_top);
- dri_bo_reference(gen6_avc_surface->dmv_bottom);
- } else {
- break;
- }
- }
-
- mfc_context->uncompressed_picture_source.bo = encode_state->input_yuv_object->bo;
- dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
-
- obj_buffer = encode_state->coded_buf_object;
- bo = obj_buffer->buffer_store->bo;
- mfc_context->mfc_indirect_pak_bse_object.bo = bo;
- mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE;
- mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
- dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
-
- dri_bo_map(bo, 1);
- coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
- coded_buffer_segment->mapped = 0;
- coded_buffer_segment->codec = encoder_context->codec;
- dri_bo_unmap(bo);
-
- return vaStatus;
-}
-/*
- * The LUT uses the pair of 4-bit units: (shift, base) structure.
- * 2^K * X = value .
- * So it is necessary to convert one cost into the nearest LUT format.
- * The derivation is:
- * 2^K *x = 2^n * (1 + deltaX)
- * k + log2(x) = n + log2(1 + deltaX)
- * log2(x) = n - k + log2(1 + deltaX)
- * As X is in the range of [1, 15]
- * 4 > n - k + log2(1 + deltaX) >= 0
- * => n + log2(1 + deltaX) >= k > n - 4 + log2(1 + deltaX)
- * Then we can derive the corresponding K and get the nearest LUT format.
- */
-int intel_format_lutvalue(int value, int max)
-{
- int ret;
- int logvalue, temp1, temp2;
-
- if (value <= 0)
- return 0;
-
- logvalue = (int)(log2f((float)value));
- if (logvalue < 4) {
- ret = value;
- } else {
- int error, temp_value, base, j, temp_err;
- error = value;
- j = logvalue - 4 + 1;
- ret = -1;
- for(; j <= logvalue; j++) {
- if (j == 0) {
- base = value >> j;
- } else {
- base = (value + (1 << (j - 1)) - 1) >> j;
- }
- if (base >= 16)
- continue;
-
- temp_value = base << j;
- temp_err = abs(value - temp_value);
- if (temp_err < error) {
- error = temp_err;
- ret = (j << 4) | base;
- if (temp_err == 0)
- break;
- }
- }
- }
- temp1 = (ret & 0xf) << ((ret & 0xf0) >> 4);
- temp2 = (max & 0xf) << ((max & 0xf0) >> 4);
- if (temp1 > temp2)
- ret = max;
- return ret;
-
-}
-
-
-#define QP_MAX 52
-#define VP8_QP_MAX 128
-
-
-static float intel_lambda_qp(int qp)
-{
- float value, lambdaf;
- value = qp;
- value = value / 6 - 2;
- if (value < 0)
- value = 0;
- lambdaf = roundf(powf(2, value));
- return lambdaf;
-}
-
-static
-void intel_h264_calc_mbmvcost_qp(int qp,
- int slice_type,
- uint8_t *vme_state_message)
-{
- int m_cost, j, mv_count;
- float lambda, m_costf;
-
- assert(qp <= QP_MAX);
- lambda = intel_lambda_qp(qp);
-
- m_cost = lambda;
- vme_state_message[MODE_CHROMA_INTRA] = 0;
- vme_state_message[MODE_REFID_COST] = intel_format_lutvalue(m_cost, 0x8f);
-
- if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
- } else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f);
- mv_count++;
- }
-
- if (qp <= 25) {
- vme_state_message[MODE_INTRA_16X16] = 0x4a;
- vme_state_message[MODE_INTRA_8X8] = 0x4a;
- vme_state_message[MODE_INTRA_4X4] = 0x4a;
- vme_state_message[MODE_INTRA_NONPRED] = 0x4a;
- vme_state_message[MODE_INTER_16X16] = 0x4a;
- vme_state_message[MODE_INTER_16X8] = 0x4a;
- vme_state_message[MODE_INTER_8X8] = 0x4a;
- vme_state_message[MODE_INTER_8X4] = 0x4a;
- vme_state_message[MODE_INTER_4X4] = 0x4a;
- vme_state_message[MODE_INTER_BWD] = 0x2a;
- return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
- if (slice_type == SLICE_TYPE_P) {
- m_costf = lambda * 2.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 4;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 1.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 3;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f);
- /* BWD is not used in P-frame */
- vme_state_message[MODE_INTER_BWD] = 0;
- } else {
- m_costf = lambda * 2.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 5.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 5.0;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 6.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 1.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f);
- }
- }
- return;
-}
-
-void intel_vme_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int qp;
- uint8_t *vme_state_message = (uint8_t *)(vme_context->vme_state_message);
-
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
- if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
- else
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
-
- if (vme_state_message == NULL)
- return;
-
- intel_h264_calc_mbmvcost_qp(qp, slice_type, vme_state_message);
-}
-
-void intel_vme_vp8_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
- VAQMatrixBufferVP8 *q_matrix = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
- int qp, m_cost, j, mv_count;
- uint8_t *vme_state_message = (uint8_t *)(vme_context->vme_state_message);
- float lambda, m_costf;
-
- int is_key_frame = !pic_param->pic_flags.bits.frame_type;
- int slice_type = (is_key_frame ? SLICE_TYPE_I : SLICE_TYPE_P);
-
- if (vme_state_message == NULL)
- return;
-
- if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = q_matrix->quantization_index[0];
- else
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
-
- lambda = intel_lambda_qp(qp * QP_MAX / VP8_QP_MAX);
-
- m_cost = lambda;
- vme_state_message[MODE_CHROMA_INTRA] = intel_format_lutvalue(m_cost, 0x8f);
-
- if (is_key_frame) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
- } else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f);
- mv_count++;
- }
-
- if (qp < 92 ) {
- vme_state_message[MODE_INTRA_16X16] = 0x4a;
- vme_state_message[MODE_INTRA_4X4] = 0x4a;
- vme_state_message[MODE_INTRA_NONPRED] = 0x4a;
- vme_state_message[MODE_INTER_16X16] = 0x4a;
- vme_state_message[MODE_INTER_16X8] = 0x4a;
- vme_state_message[MODE_INTER_8X8] = 0x4a;
- vme_state_message[MODE_INTER_4X4] = 0x4a;
- vme_state_message[MODE_INTER_BWD] = 0;
- return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
-
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
-
- m_costf = lambda * 2.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 4;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 1.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f);
- /* BWD is not used in P-frame */
- vme_state_message[MODE_INTER_BWD] = 0;
- }
-}
-
-#define MB_SCOREBOARD_A (1 << 0)
-#define MB_SCOREBOARD_B (1 << 1)
-#define MB_SCOREBOARD_C (1 << 2)
-void
-gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_context)
-{
- vme_context->gpe_context.vfe_desc5.scoreboard0.enable = 1;
- vme_context->gpe_context.vfe_desc5.scoreboard0.type = SCOREBOARD_STALLING;
- vme_context->gpe_context.vfe_desc5.scoreboard0.mask = (MB_SCOREBOARD_A |
- MB_SCOREBOARD_B |
- MB_SCOREBOARD_C);
-
- /* In VME prediction the current mb depends on the neighbour
- * A/B/C macroblock. So the left/up/up-right dependency should
- * be considered.
- */
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x0 = -1;
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y0 = 0;
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x1 = 0;
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y1 = -1;
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x2 = 1;
- vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y2 = -1;
-
- vme_context->gpe_context.vfe_desc7.dword = 0;
- return;
-}
-
-/* check whether the mb of (x_index, y_index) is out of bound */
-static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height)
-{
- int mb_index;
- if (x_index < 0 || x_index >= mb_width)
- return -1;
- if (y_index < 0 || y_index >= mb_height)
- return -1;
-
- mb_index = y_index * mb_width + x_index;
- if (mb_index < first_mb || mb_index > (first_mb + num_mb))
- return -1;
- return 0;
-}
-
-void
-gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_width, int mb_height,
- int kernel,
- int transform_8x8_mode_flag,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- int mb_row;
- int s;
- unsigned int *command_ptr;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int qp,qp_mb,qp_index;
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
- if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
- else
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
-
-#define USE_SCOREBOARD (1 << 21)
-
- dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
- command_ptr = vme_context->vme_batchbuffer.bo->virtual;
-
- for (s = 0; s < encode_state->num_slice_params_ext; s++) {
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
- int first_mb = pSliceParameter->macroblock_address;
- int num_mb = pSliceParameter->num_macroblocks;
- unsigned int mb_intra_ub, score_dep;
- int x_outer, y_outer, x_inner, y_inner;
- int xtemp_outer = 0;
-
- x_outer = first_mb % mb_width;
- y_outer = first_mb / mb_width;
- mb_row = y_outer;
-
- for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
- x_inner = x_outer;
- y_inner = y_outer;
- for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
- mb_intra_ub = 0;
- score_dep = 0;
- if (x_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
- score_dep |= MB_SCOREBOARD_A;
- }
- if (y_inner != mb_row) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
- score_dep |= MB_SCOREBOARD_B;
- if (x_inner != 0)
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
- if (x_inner != (mb_width -1)) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
- score_dep |= MB_SCOREBOARD_C;
- }
- }
-
- *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
- *command_ptr++ = kernel;
- *command_ptr++ = USE_SCOREBOARD;
- /* Indirect data */
- *command_ptr++ = 0;
- /* the (X, Y) term of scoreboard */
- *command_ptr++ = ((y_inner << 16) | x_inner);
- *command_ptr++ = score_dep;
- /*inline data */
- *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
- *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
- /* QP occupies one byte */
- if (vme_context->roi_enabled) {
- qp_index = y_inner * mb_width + x_inner;
- qp_mb = *(vme_context->qp_per_mb + qp_index);
- } else
- qp_mb = qp;
- *command_ptr++ = qp_mb;
- x_inner -= 2;
- y_inner += 1;
- }
- x_outer += 1;
- }
-
- xtemp_outer = mb_width - 2;
- if (xtemp_outer < 0)
- xtemp_outer = 0;
- x_outer = xtemp_outer;
- y_outer = first_mb / mb_width;
- for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
- y_inner = y_outer;
- x_inner = x_outer;
- for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
- mb_intra_ub = 0;
- score_dep = 0;
- if (x_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
- score_dep |= MB_SCOREBOARD_A;
- }
- if (y_inner != mb_row) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
- score_dep |= MB_SCOREBOARD_B;
- if (x_inner != 0)
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
-
- if (x_inner != (mb_width -1)) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
- score_dep |= MB_SCOREBOARD_C;
- }
- }
-
- *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
- *command_ptr++ = kernel;
- *command_ptr++ = USE_SCOREBOARD;
- /* Indirect data */
- *command_ptr++ = 0;
- /* the (X, Y) term of scoreboard */
- *command_ptr++ = ((y_inner << 16) | x_inner);
- *command_ptr++ = score_dep;
- /*inline data */
- *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
- *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
- /* qp occupies one byte */
- if (vme_context->roi_enabled) {
- qp_index = y_inner * mb_width + x_inner;
- qp_mb = *(vme_context->qp_per_mb + qp_index);
- } else
- qp_mb = qp;
- *command_ptr++ = qp_mb;
-
- x_inner -= 2;
- y_inner += 1;
- }
- x_outer++;
- if (x_outer >= mb_width) {
- y_outer += 1;
- x_outer = xtemp_outer;
- }
- }
- }
-
- *command_ptr++ = 0;
- *command_ptr++ = MI_BATCH_BUFFER_END;
-
- dri_bo_unmap(vme_context->vme_batchbuffer.bo);
-}
-
-static uint8_t
-intel_get_ref_idx_state_1(VAPictureH264 *va_pic, unsigned int frame_store_id)
-{
- unsigned int is_long_term =
- !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE);
- unsigned int is_top_field =
- !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD);
- unsigned int is_bottom_field =
- !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
-
- return ((is_long_term << 6) |
- ((is_top_field ^ is_bottom_field ^ 1) << 5) |
- (frame_store_id << 1) |
- ((is_top_field ^ 1) & is_bottom_field));
-}
-
-void
-intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- int slice_type;
- struct object_surface *obj_surface;
- unsigned int fref_entry, bref_entry;
- int frame_index, i;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
-
- fref_entry = 0x80808080;
- bref_entry = 0x80808080;
- slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
- if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) {
- int ref_idx_l0 = (vme_context->ref_index_in_mb[0] & 0xff);
-
- if (ref_idx_l0 > 3) {
- WARN_ONCE("ref_idx_l0 is out of range\n");
- ref_idx_l0 = 0;
- }
-
- obj_surface = vme_context->used_reference_objects[0];
- frame_index = -1;
- for (i = 0; i < 16; i++) {
- if (obj_surface &&
- obj_surface == encode_state->reference_objects[i]) {
- frame_index = i;
- break;
- }
- }
- if (frame_index == -1) {
- WARN_ONCE("RefPicList0 is not found in DPB!\n");
- } else {
- int ref_idx_l0_shift = ref_idx_l0 * 8;
- fref_entry &= ~(0xFF << ref_idx_l0_shift);
- fref_entry += (intel_get_ref_idx_state_1(vme_context->used_references[0], frame_index) << ref_idx_l0_shift);
- }
- }
-
- if (slice_type == SLICE_TYPE_B) {
- int ref_idx_l1 = (vme_context->ref_index_in_mb[1] & 0xff);
-
- if (ref_idx_l1 > 3) {
- WARN_ONCE("ref_idx_l1 is out of range\n");
- ref_idx_l1 = 0;
- }
-
- obj_surface = vme_context->used_reference_objects[1];
- frame_index = -1;
- for (i = 0; i < 16; i++) {
- if (obj_surface &&
- obj_surface == encode_state->reference_objects[i]) {
- frame_index = i;
- break;
- }
- }
- if (frame_index == -1) {
- WARN_ONCE("RefPicList1 is not found in DPB!\n");
- } else {
- int ref_idx_l1_shift = ref_idx_l1 * 8;
- bref_entry &= ~(0xFF << ref_idx_l1_shift);
- bref_entry += (intel_get_ref_idx_state_1(vme_context->used_references[1], frame_index) << ref_idx_l1_shift);
- }
- }
-
- BEGIN_BCS_BATCH(batch, 10);
- OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
- OUT_BCS_BATCH(batch, 0); //Select L0
- OUT_BCS_BATCH(batch, fref_entry); //Only 1 reference
- for(i = 0; i < 7; i++) {
- OUT_BCS_BATCH(batch, 0x80808080);
- }
- ADVANCE_BCS_BATCH(batch);
-
- BEGIN_BCS_BATCH(batch, 10);
- OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
- OUT_BCS_BATCH(batch, 1); //Select L1
- OUT_BCS_BATCH(batch, bref_entry); //Only 1 reference
- for(i = 0; i < 7; i++) {
- OUT_BCS_BATCH(batch, 0x80808080);
- }
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-void intel_vme_mpeg2_state_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- uint32_t *vme_state_message = (uint32_t *)(vme_context->vme_state_message);
- VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
- int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
- uint32_t mv_x, mv_y;
- VAEncSliceParameterBufferMPEG2 *slice_param = NULL;
- VAEncPictureParameterBufferMPEG2 *pic_param = NULL;
- slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
-
- if (vme_context->mpeg2_level == MPEG2_LEVEL_LOW) {
- mv_x = 512;
- mv_y = 64;
- } else if (vme_context->mpeg2_level == MPEG2_LEVEL_MAIN) {
- mv_x = 1024;
- mv_y = 128;
- } else if (vme_context->mpeg2_level == MPEG2_LEVEL_HIGH) {
- mv_x = 2048;
- mv_y = 128;
- } else {
- WARN_ONCE("Incorrect Mpeg2 level setting!\n");
- mv_x = 512;
- mv_y = 64;
- }
-
- pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
- if (pic_param->picture_type != VAEncPictureTypeIntra) {
- int qp, m_cost, j, mv_count;
- float lambda, m_costf;
- slice_param = (VAEncSliceParameterBufferMPEG2 *)
- encode_state->slice_params_ext[0]->buffer;
- qp = slice_param->quantiser_scale_code;
- lambda = intel_lambda_qp(qp);
- /* No Intra prediction. So it is zero */
- vme_state_message[MODE_INTRA_8X8] = 0;
- vme_state_message[MODE_INTRA_4X4] = 0;
- vme_state_message[MODE_INTER_MV0] = 0;
- for (j = 1; j < 3; j++) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + mv_count] =
- intel_format_lutvalue(m_cost, 0x6f);
- mv_count++;
- }
- m_cost = lambda;
- /* It can only perform the 16x16 search. So mode cost can be ignored for
- * the other mode. for example: 16x8/8x8
- */
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
-
- vme_state_message[MODE_INTER_16X8] = 0;
- vme_state_message[MODE_INTER_8X8] = 0;
- vme_state_message[MODE_INTER_8X4] = 0;
- vme_state_message[MODE_INTER_4X4] = 0;
- vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f);
-
- }
- vme_state_message[MPEG2_MV_RANGE] = (mv_y << 16) | (mv_x);
-
- vme_state_message[MPEG2_PIC_WIDTH_HEIGHT] = (height_in_mbs << 16) |
- width_in_mbs;
-}
-
-void
-gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_width, int mb_height,
- int kernel,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- unsigned int *command_ptr;
-
-#define MPEG2_SCOREBOARD (1 << 21)
-
- dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
- command_ptr = vme_context->vme_batchbuffer.bo->virtual;
-
- {
- unsigned int mb_intra_ub, score_dep;
- int x_outer, y_outer, x_inner, y_inner;
- int xtemp_outer = 0;
- int first_mb = 0;
- int num_mb = mb_width * mb_height;
-
- x_outer = 0;
- y_outer = 0;
-
-
- for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
- x_inner = x_outer;
- y_inner = y_outer;
- for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
- mb_intra_ub = 0;
- score_dep = 0;
- if (x_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
- score_dep |= MB_SCOREBOARD_A;
- }
- if (y_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
- score_dep |= MB_SCOREBOARD_B;
-
- if (x_inner != 0)
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
-
- if (x_inner != (mb_width -1)) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
- score_dep |= MB_SCOREBOARD_C;
- }
- }
-
- *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
- *command_ptr++ = kernel;
- *command_ptr++ = MPEG2_SCOREBOARD;
- /* Indirect data */
- *command_ptr++ = 0;
- /* the (X, Y) term of scoreboard */
- *command_ptr++ = ((y_inner << 16) | x_inner);
- *command_ptr++ = score_dep;
- /*inline data */
- *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
- *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
- x_inner -= 2;
- y_inner += 1;
- }
- x_outer += 1;
- }
-
- xtemp_outer = mb_width - 2;
- if (xtemp_outer < 0)
- xtemp_outer = 0;
- x_outer = xtemp_outer;
- y_outer = 0;
- for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
- y_inner = y_outer;
- x_inner = x_outer;
- for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
- mb_intra_ub = 0;
- score_dep = 0;
- if (x_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
- score_dep |= MB_SCOREBOARD_A;
- }
- if (y_inner != 0) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
- score_dep |= MB_SCOREBOARD_B;
-
- if (x_inner != 0)
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
-
- if (x_inner != (mb_width -1)) {
- mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
- score_dep |= MB_SCOREBOARD_C;
- }
- }
-
- *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
- *command_ptr++ = kernel;
- *command_ptr++ = MPEG2_SCOREBOARD;
- /* Indirect data */
- *command_ptr++ = 0;
- /* the (X, Y) term of scoreboard */
- *command_ptr++ = ((y_inner << 16) | x_inner);
- *command_ptr++ = score_dep;
- /*inline data */
- *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
- *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
-
- x_inner -= 2;
- y_inner += 1;
- }
- x_outer++;
- if (x_outer >= mb_width) {
- y_outer += 1;
- x_outer = xtemp_outer;
- }
- }
- }
-
- *command_ptr++ = 0;
- *command_ptr++ = MI_BATCH_BUFFER_END;
-
- dri_bo_unmap(vme_context->vme_batchbuffer.bo);
- return;
-}
-
-static int
-avc_temporal_find_surface(VAPictureH264 *curr_pic,
- VAPictureH264 *ref_list,
- int num_pictures,
- int dir)
-{
- int i, found = -1, min = 0x7FFFFFFF;
-
- for (i = 0; i < num_pictures; i++) {
- int tmp;
-
- if ((ref_list[i].flags & VA_PICTURE_H264_INVALID) ||
- (ref_list[i].picture_id == VA_INVALID_SURFACE))
- break;
-
- tmp = curr_pic->TopFieldOrderCnt - ref_list[i].TopFieldOrderCnt;
-
- if (dir)
- tmp = -tmp;
-
- if (tmp > 0 && tmp < min) {
- min = tmp;
- found = i;
- }
- }
-
- return found;
-}
-
-void
-intel_avc_vme_reference_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int list_index,
- int surface_index,
- void (* vme_source_surface_state)(
- VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context))
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct object_surface *obj_surface = NULL;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- VASurfaceID ref_surface_id;
- VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int max_num_references;
- VAPictureH264 *curr_pic;
- VAPictureH264 *ref_list;
- int ref_idx;
-
- if (list_index == 0) {
- max_num_references = pic_param->num_ref_idx_l0_active_minus1 + 1;
- ref_list = slice_param->RefPicList0;
- } else {
- max_num_references = pic_param->num_ref_idx_l1_active_minus1 + 1;
- ref_list = slice_param->RefPicList1;
- }
-
- if (max_num_references == 1) {
- if (list_index == 0) {
- ref_surface_id = slice_param->RefPicList0[0].picture_id;
- vme_context->used_references[0] = &slice_param->RefPicList0[0];
- } else {
- ref_surface_id = slice_param->RefPicList1[0].picture_id;
- vme_context->used_references[1] = &slice_param->RefPicList1[0];
- }
-
- if (ref_surface_id != VA_INVALID_SURFACE)
- obj_surface = SURFACE(ref_surface_id);
-
- if (!obj_surface ||
- !obj_surface->bo) {
- obj_surface = encode_state->reference_objects[list_index];
- vme_context->used_references[list_index] = &pic_param->ReferenceFrames[list_index];
- }
-
- ref_idx = 0;
- } else {
- curr_pic = &pic_param->CurrPic;
-
- /* select the reference frame in temporal space */
- ref_idx = avc_temporal_find_surface(curr_pic, ref_list, max_num_references, list_index == 1);
- ref_surface_id = ref_list[ref_idx].picture_id;
-
- if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
- obj_surface = SURFACE(ref_surface_id);
-
- vme_context->used_reference_objects[list_index] = obj_surface;
- vme_context->used_references[list_index] = &ref_list[ref_idx];
- }
-
- if (obj_surface &&
- obj_surface->bo) {
- assert(ref_idx >= 0);
- vme_context->used_reference_objects[list_index] = obj_surface;
- vme_source_surface_state(ctx, surface_index, obj_surface, encoder_context);
- vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
- ref_idx << 16 |
- ref_idx << 8 |
- ref_idx);
- } else {
- vme_context->used_reference_objects[list_index] = NULL;
- vme_context->used_references[list_index] = NULL;
- vme_context->ref_index_in_mb[list_index] = 0;
- }
-}
-
-void intel_avc_slice_insert_packed_data(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- struct intel_batchbuffer *slice_batch)
-{
- int count, i, start_index;
- unsigned int length_in_bits;
- VAEncPackedHeaderParameterBuffer *param = NULL;
- unsigned int *header_data = NULL;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int slice_header_index;
-
- if (encode_state->slice_header_index[slice_index] == 0)
- slice_header_index = -1;
- else
- slice_header_index = (encode_state->slice_header_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
-
- count = encode_state->slice_rawdata_count[slice_index];
- start_index = (encode_state->slice_rawdata_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
-
- for (i = 0; i < count; i++) {
- unsigned int skip_emul_byte_cnt;
-
- header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;
-
- param = (VAEncPackedHeaderParameterBuffer *)
- (encode_state->packed_header_params_ext[start_index + i]->buffer);
-
- /* skip the slice header packed data type as it is lastly inserted */
- if (param->type == VAEncPackedHeaderSlice)
- continue;
-
- length_in_bits = param->bit_length;
-
- skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
-
- /* as the slice header is still required, the last header flag is set to
- * zero.
- */
- mfc_context->insert_object(ctx,
- encoder_context,
- header_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- skip_emul_byte_cnt,
- 0,
- 0,
- !param->has_emulation_bytes,
- slice_batch);
- }
-
- if (slice_header_index == -1) {
- unsigned char *slice_header = NULL;
- int slice_header_length_in_bits = 0;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
-
- /* No slice header data is passed. And the driver needs to generate it */
- /* For the Normal H264 */
- slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter,
- pPicParameter,
- pSliceParameter,
- &slice_header);
- mfc_context->insert_object(ctx, encoder_context,
- (unsigned int *)slice_header,
- ALIGN(slice_header_length_in_bits, 32) >> 5,
- slice_header_length_in_bits & 0x1f,
- 5, /* first 5 bytes are start code + nal unit type */
- 1, 0, 1, slice_batch);
-
- free(slice_header);
- } else {
- unsigned int skip_emul_byte_cnt;
-
- header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;
-
- param = (VAEncPackedHeaderParameterBuffer *)
- (encode_state->packed_header_params_ext[slice_header_index]->buffer);
- length_in_bits = param->bit_length;
-
- /* as the slice header is the last header data for one slice,
- * the last header flag is set to one.
- */
- skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
-
- mfc_context->insert_object(ctx,
- encoder_context,
- header_data,
- ALIGN(length_in_bits, 32) >> 5,
- length_in_bits & 0x1f,
- skip_emul_byte_cnt,
- 1,
- 0,
- !param->has_emulation_bytes,
- slice_batch);
- }
-
- return;
-}
-
-void
-intel_h264_initialize_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int qp;
- dri_bo *bo;
- uint8_t *cost_table;
-
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
-
- if (slice_type == SLICE_TYPE_I) {
- if (vme_context->i_qp_cost_table)
- return;
- } else if (slice_type == SLICE_TYPE_P) {
- if (vme_context->p_qp_cost_table)
- return;
- } else {
- if (vme_context->b_qp_cost_table)
- return;
- }
-
- /* It is enough to allocate 32 bytes for each qp. */
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "cost_table ",
- QP_MAX * 32,
- 64);
-
- dri_bo_map(bo, 1);
- assert(bo->virtual);
- cost_table = (uint8_t *)(bo->virtual);
- for (qp = 0; qp < QP_MAX; qp++) {
- intel_h264_calc_mbmvcost_qp(qp, slice_type, cost_table);
- cost_table += 32;
- }
-
- dri_bo_unmap(bo);
-
- if (slice_type == SLICE_TYPE_I) {
- vme_context->i_qp_cost_table = bo;
- } else if (slice_type == SLICE_TYPE_P) {
- vme_context->p_qp_cost_table = bo;
- } else {
- vme_context->b_qp_cost_table = bo;
- }
-
- vme_context->cost_table_size = QP_MAX * 32;
- return;
-}
-
-extern void
-intel_h264_setup_cost_surface(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- dri_bo *bo;
-
-
- struct i965_buffer_surface cost_table;
-
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
-
- if (slice_type == SLICE_TYPE_I) {
- bo = vme_context->i_qp_cost_table;
- } else if (slice_type == SLICE_TYPE_P) {
- bo = vme_context->p_qp_cost_table;
- } else {
- bo = vme_context->b_qp_cost_table;
- }
-
- cost_table.bo = bo;
- cost_table.num_blocks = QP_MAX;
- cost_table.pitch = 16;
- cost_table.size_block = 32;
-
- vme_context->vme_buffer_suface_setup(ctx,
- &vme_context->gpe_context,
- &cost_table,
- binding_table_offset,
- surface_state_offset);
-}
-
-/*
- * the idea of conversion between qp and qstep comes from scaling process
- * of transform coeff for Luma component in H264 spec.
- * 2^(Qpy / 6 - 6)
- * In order to avoid too small qstep, it is multiplied by 16.
- */
-static float intel_h264_qp_qstep(int qp)
-{
- float value, qstep;
- value = qp;
- value = value / 6 - 2;
- qstep = powf(2, value);
- return qstep;
-}
-
-static int intel_h264_qstep_qp(float qstep)
-{
- float qp;
-
- qp = 12.0f + 6.0f * log2f(qstep);
-
- return floorf(qp);
-}
-
-/*
- * Currently it is based on the following assumption:
- * SUM(roi_area * 1 / roi_qstep) + non_area * 1 / nonroi_qstep =
- * total_aread * 1 / baseqp_qstep
- *
- * qstep is the linearized quantizer of H264 quantizer
- */
-typedef struct {
- int row_start_in_mb;
- int row_end_in_mb;
- int col_start_in_mb;
- int col_end_in_mb;
-
- int width_mbs;
- int height_mbs;
-
- int roi_qp;
-} ROIRegionParam;
-
-static VAStatus
-intel_h264_enc_roi_cbr(VADriverContextP ctx,
- int base_qp,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- int nonroi_qp;
- int min_qp = MAX(1, encoder_context->brc.min_qp);
- bool quickfill = 0;
-
- ROIRegionParam param_regions[I965_MAX_NUM_ROI_REGIONS];
- int num_roi = 0;
- int i,j;
-
- float temp;
- float qstep_nonroi, qstep_base;
- float roi_area, total_area, nonroi_area;
- float sum_roi;
-
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- int mbs_in_picture = width_in_mbs * height_in_mbs;
-
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAStatus vaStatus = VA_STATUS_SUCCESS;
-
- /* currently roi_value_is_qp_delta is the only supported mode of priority.
- *
- * qp_delta set by user is added to base_qp, which is then clapped by
- * [base_qp-min_delta, base_qp+max_delta].
- */
- ASSERT_RET(encoder_context->brc.roi_value_is_qp_delta, VA_STATUS_ERROR_INVALID_PARAMETER);
-
- num_roi = encoder_context->brc.num_roi;
-
- /* when the base_qp is lower than 12, the quality is quite good based
- * on the H264 test experience.
- * In such case it is unnecessary to adjust the quality for ROI region.
- */
- if (base_qp <= 12) {
- nonroi_qp = base_qp;
- quickfill = 1;
- goto qp_fill;
- }
-
- sum_roi = 0.0f;
- roi_area = 0;
- for (i = 0; i < num_roi; i++) {
- int row_start, row_end, col_start, col_end;
- int roi_width_mbs, roi_height_mbs;
- int mbs_in_roi;
- int roi_qp;
- float qstep_roi;
-
- col_start = encoder_context->brc.roi[i].left;
- col_end = encoder_context->brc.roi[i].right;
- row_start = encoder_context->brc.roi[i].top;
- row_end = encoder_context->brc.roi[i].bottom;
-
- col_start = col_start / 16;
- col_end = (col_end + 15) / 16;
- row_start = row_start / 16;
- row_end = (row_end + 15) / 16;
-
- roi_width_mbs = col_end - col_start;
- roi_height_mbs = row_end - row_start;
- mbs_in_roi = roi_width_mbs * roi_height_mbs;
-
- param_regions[i].row_start_in_mb = row_start;
- param_regions[i].row_end_in_mb = row_end;
- param_regions[i].col_start_in_mb = col_start;
- param_regions[i].col_end_in_mb = col_end;
- param_regions[i].width_mbs = roi_width_mbs;
- param_regions[i].height_mbs = roi_height_mbs;
-
- roi_qp = base_qp + encoder_context->brc.roi[i].value;
- BRC_CLIP(roi_qp, min_qp, 51);
-
- param_regions[i].roi_qp = roi_qp;
- qstep_roi = intel_h264_qp_qstep(roi_qp);
-
- roi_area += mbs_in_roi;
- sum_roi += mbs_in_roi / qstep_roi;
- }
-
- total_area = mbs_in_picture;
- nonroi_area = total_area - roi_area;
-
- qstep_base = intel_h264_qp_qstep(base_qp);
- temp = (total_area / qstep_base - sum_roi);
-
- if (temp < 0) {
- nonroi_qp = 51;
- } else {
- qstep_nonroi = nonroi_area / temp;
- nonroi_qp = intel_h264_qstep_qp(qstep_nonroi);
- }
-
- BRC_CLIP(nonroi_qp, min_qp, 51);
-
-qp_fill:
- memset(vme_context->qp_per_mb, nonroi_qp, mbs_in_picture);
- if (!quickfill) {
- char *qp_ptr;
-
- for (i = 0; i < num_roi; i++) {
- for (j = param_regions[i].row_start_in_mb; j < param_regions[i].row_end_in_mb; j++) {
- qp_ptr = vme_context->qp_per_mb + (j * width_in_mbs) + param_regions[i].col_start_in_mb;
- memset(qp_ptr, param_regions[i].roi_qp, param_regions[i].width_mbs);
- }
- }
- }
- return vaStatus;
-}
-
-extern void
-intel_h264_enc_roi_config(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- char *qp_ptr;
- int i, j;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
-
- int row_start, row_end, col_start, col_end;
- int num_roi = 0;
-
- vme_context->roi_enabled = 0;
- /* Restriction: Disable ROI when multi-slice is enabled */
- if (!encoder_context->context_roi || (encode_state->num_slice_params_ext > 1))
- return;
-
- vme_context->roi_enabled = !!encoder_context->brc.num_roi;
-
- if (!vme_context->roi_enabled)
- return;
-
- if ((vme_context->saved_width_mbs != width_in_mbs) ||
- (vme_context->saved_height_mbs != height_in_mbs)) {
- free(vme_context->qp_per_mb);
- vme_context->qp_per_mb = calloc(1, width_in_mbs * height_in_mbs);
-
- vme_context->saved_width_mbs = width_in_mbs;
- vme_context->saved_height_mbs = height_in_mbs;
- assert(vme_context->qp_per_mb);
- }
- if (encoder_context->rate_control_mode == VA_RC_CBR) {
- /*
- * TODO: More complex Qp adjust needs to be added.
- * Currently it is initialized to slice_qp.
- */
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int qp;
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
-
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
- intel_h264_enc_roi_cbr(ctx, qp, encode_state, encoder_context);
-
- } else if (encoder_context->rate_control_mode == VA_RC_CQP){
- VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int qp;
- int min_qp = MAX(1, encoder_context->brc.min_qp);
-
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
- memset(vme_context->qp_per_mb, qp, width_in_mbs * height_in_mbs);
-
-
- for (j = num_roi; j ; j--) {
- int qp_delta, qp_clip;
-
- col_start = encoder_context->brc.roi[i].left;
- col_end = encoder_context->brc.roi[i].right;
- row_start = encoder_context->brc.roi[i].top;
- row_end = encoder_context->brc.roi[i].bottom;
-
- col_start = col_start / 16;
- col_end = (col_end + 15) / 16;
- row_start = row_start / 16;
- row_end = (row_end + 15) / 16;
-
- qp_delta = encoder_context->brc.roi[i].value;
- qp_clip = qp + qp_delta;
-
- BRC_CLIP(qp_clip, min_qp, 51);
-
- for (i = row_start; i < row_end; i++) {
- qp_ptr = vme_context->qp_per_mb + (i * width_in_mbs) + col_start;
- memset(qp_ptr, qp_clip, (col_end - col_start));
- }
- }
- } else {
- /*
- * TODO: Disable it for non CBR-CQP.
- */
- vme_context->roi_enabled = 0;
- }
-
- if (vme_context->roi_enabled && IS_GEN7(i965->intel.device_info))
- encoder_context->soft_batch_force = 1;
-
- return;
-}
-
-/* HEVC */
-static int
-hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
- VAPictureHEVC *ref_list,
- int num_pictures,
- int dir)
-{
- int i, found = -1, min = 0x7FFFFFFF;
-
- for (i = 0; i < num_pictures; i++) {
- int tmp;
-
- if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
- (ref_list[i].picture_id == VA_INVALID_SURFACE))
- break;
-
- tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
-
- if (dir)
- tmp = -tmp;
-
- if (tmp > 0 && tmp < min) {
- min = tmp;
- found = i;
- }
- }
-
- return found;
-}
-void
-intel_hevc_vme_reference_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int list_index,
- int surface_index,
- void (* vme_source_surface_state)(
- VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context))
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct object_surface *obj_surface = NULL;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- VASurfaceID ref_surface_id;
- VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferHEVC *pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferHEVC *slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
- int max_num_references;
- VAPictureHEVC *curr_pic;
- VAPictureHEVC *ref_list;
- int ref_idx;
- unsigned int is_hevc10 = 0;
- GenHevcSurface *hevc_encoder_surface = NULL;
-
- if((pSequenceParameter->seq_fields.bits.bit_depth_luma_minus8 > 0)
- || (pSequenceParameter->seq_fields.bits.bit_depth_chroma_minus8 > 0))
- is_hevc10 = 1;
-
- if (list_index == 0) {
- max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 + 1;
- ref_list = slice_param->ref_pic_list0;
- } else {
- max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 + 1;
- ref_list = slice_param->ref_pic_list1;
- }
-
- if (max_num_references == 1) {
- if (list_index == 0) {
- ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
- vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
- } else {
- ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
- vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
- }
-
- if (ref_surface_id != VA_INVALID_SURFACE)
- obj_surface = SURFACE(ref_surface_id);
-
- if (!obj_surface ||
- !obj_surface->bo) {
- obj_surface = encode_state->reference_objects[list_index];
- vme_context->used_references[list_index] = &pic_param->reference_frames[list_index];
- }
-
- ref_idx = 0;
- } else {
- curr_pic = &pic_param->decoded_curr_pic;
-
- /* select the reference frame in temporal space */
- ref_idx = hevc_temporal_find_surface(curr_pic, ref_list, max_num_references, list_index == 1);
- ref_surface_id = ref_list[ref_idx].picture_id;
-
- if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
- obj_surface = SURFACE(ref_surface_id);
-
- vme_context->used_reference_objects[list_index] = obj_surface;
- vme_context->used_references[list_index] = &ref_list[ref_idx];
- }
-
- if (obj_surface &&
- obj_surface->bo) {
- assert(ref_idx >= 0);
- vme_context->used_reference_objects[list_index] = obj_surface;
-
- if(is_hevc10){
- hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
- assert(hevc_encoder_surface);
- obj_surface = hevc_encoder_surface->nv12_surface_obj;
- }
- vme_source_surface_state(ctx, surface_index, obj_surface, encoder_context);
- vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
- ref_idx << 16 |
- ref_idx << 8 |
- ref_idx);
- } else {
- vme_context->used_reference_objects[list_index] = NULL;
- vme_context->used_references[list_index] = NULL;
- vme_context->ref_index_in_mb[list_index] = 0;
- }
-}
-
-void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncPictureParameterBufferHEVC *pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferHEVC *slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
- VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
- int qp, m_cost, j, mv_count;
- uint8_t *vme_state_message = (uint8_t *)(vme_context->vme_state_message);
- float lambda, m_costf;
-
- /* here no SI SP slice for HEVC, do not need slice fixup */
- int slice_type = slice_param->slice_type;
-
-
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
-
- if(encoder_context->rate_control_mode == VA_RC_CBR)
- {
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
- if(slice_type == HEVC_SLICE_B) {
- if(pSequenceParameter->ip_period == 1)
- {
- slice_type = HEVC_SLICE_P;
- qp = mfc_context->bit_rate_control_context[HEVC_SLICE_P].QpPrimeY;
-
- }else if(mfc_context->vui_hrd.i_frame_number % pSequenceParameter->ip_period == 1){
- slice_type = HEVC_SLICE_P;
- qp = mfc_context->bit_rate_control_context[HEVC_SLICE_P].QpPrimeY;
- }
- }
-
- }
-
- if (vme_state_message == NULL)
- return;
-
- assert(qp <= QP_MAX);
- lambda = intel_lambda_qp(qp);
- if (slice_type == HEVC_SLICE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
- } else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
- m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
- m_cost = (int)m_costf;
- vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f);
- mv_count++;
- }
-
- if (qp <= 25) {
- vme_state_message[MODE_INTRA_16X16] = 0x4a;
- vme_state_message[MODE_INTRA_8X8] = 0x4a;
- vme_state_message[MODE_INTRA_4X4] = 0x4a;
- vme_state_message[MODE_INTRA_NONPRED] = 0x4a;
- vme_state_message[MODE_INTER_16X16] = 0x4a;
- vme_state_message[MODE_INTER_16X8] = 0x4a;
- vme_state_message[MODE_INTER_8X8] = 0x4a;
- vme_state_message[MODE_INTER_8X4] = 0x4a;
- vme_state_message[MODE_INTER_4X4] = 0x4a;
- vme_state_message[MODE_INTER_BWD] = 0x2a;
- return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f);
- if (slice_type == HEVC_SLICE_P) {
- m_costf = lambda * 2.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 4;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 1.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 3;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f);
- /* BWD is not used in P-frame */
- vme_state_message[MODE_INTER_BWD] = 0;
- } else {
- m_costf = lambda * 2.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 5.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 5.0;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 6.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f);
- m_costf = lambda * 1.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f);
- }
- }
-}
diff --git a/src/gen6_mfd.c b/src/gen6_mfd.c
deleted file mode 100755
index ed4829c..0000000
--- a/src/gen6_mfd.c
+++ /dev/null
@@ -1,1877 +0,0 @@
-/*
- * Copyright 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Xiang Haihao <haihao.xiang@intel.com>
- *
- */
-
-#include "sysdeps.h"
-#include "intel_batchbuffer.h"
-#include "intel_driver.h"
-#include "i965_defines.h"
-#include "i965_drv_video.h"
-#include "i965_decoder_utils.h"
-
-#include "gen6_mfd.h"
-#include "intel_media.h"
-
-static const uint32_t zigzag_direct[64] = {
- 0, 1, 8, 16, 9, 2, 3, 10,
- 17, 24, 32, 25, 18, 11, 4, 5,
- 12, 19, 26, 33, 40, 48, 41, 34,
- 27, 20, 13, 6, 7, 14, 21, 28,
- 35, 42, 49, 56, 57, 50, 43, 36,
- 29, 22, 15, 23, 30, 37, 44, 51,
- 58, 59, 52, 45, 38, 31, 39, 46,
- 53, 60, 61, 54, 47, 55, 62, 63
-};
-
-static void
-gen6_mfd_init_avc_surface(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- struct object_surface *obj_surface)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
- int height_in_mbs;
-
- obj_surface->free_private_data = gen_free_avc_surface;
- height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
-
- if (!gen6_avc_surface) {
- gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
- assert(gen6_avc_surface);
- gen6_avc_surface->base.frame_store_id = -1;
- assert((obj_surface->size & 0x3f) == 0);
- obj_surface->private_data = gen6_avc_surface;
- }
-
- gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
- !pic_param->seq_fields.bits.direct_8x8_inference_flag);
-
- if (gen6_avc_surface->dmv_top == NULL) {
- gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
- "direct mv w/r buffer",
- 128 * height_in_mbs * 64, /* scalable with frame height */
- 0x1000);
- }
-
- if (gen6_avc_surface->dmv_bottom_flag &&
- gen6_avc_surface->dmv_bottom == NULL) {
- gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
- "direct mv w/r buffer",
- 128 * height_in_mbs * 64, /* scalable with frame height */
- 0x1000);
- }
-}
-
-static void
-gen6_mfd_pipe_mode_select(VADriverContextP ctx,
- struct decode_state *decode_state,
- int standard_select,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
-
- assert(standard_select == MFX_FORMAT_MPEG2 ||
- standard_select == MFX_FORMAT_AVC ||
- standard_select == MFX_FORMAT_VC1);
-
- BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
- OUT_BCS_BATCH(batch,
- (MFD_MODE_VLD << 16) | /* VLD mode */
- (0 << 10) | /* disable Stream-Out */
- (gen6_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
- (gen6_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
- (0 << 7) | /* disable TLB prefectch */
- (0 << 5) | /* not in stitch mode */
- (MFX_CODEC_DECODE << 4) | /* decoding mode */
- (standard_select << 0));
- OUT_BCS_BATCH(batch,
- (0 << 20) | /* round flag in PB slice */
- (0 << 19) | /* round flag in Intra8x8 */
- (0 << 7) | /* expand NOA bus flag */
- (1 << 6) | /* must be 1 */
- (0 << 5) | /* disable clock gating for NOA */
- (0 << 4) | /* terminate if AVC motion and POC table error occurs */
- (0 << 3) | /* terminate if AVC mbdata error occurs */
- (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
- (0 << 1) | /* AVC long field motion vector */
- (1 << 0)); /* always calculate AVC ILDB boundary strength */
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_surface_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- int standard_select,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- struct object_surface *obj_surface = decode_state->render_object;
- unsigned int surface_format;
-
- surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
- MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
-
- BEGIN_BCS_BATCH(batch, 6);
- OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- ((obj_surface->orig_height - 1) << 19) |
- ((obj_surface->orig_width - 1) << 6));
- OUT_BCS_BATCH(batch,
- (surface_format << 28) | /* 420 planar YUV surface */
- (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
- (0 << 22) | /* surface object control state, FIXME??? */
- ((obj_surface->width - 1) << 3) | /* pitch */
- (0 << 2) | /* must be 0 for interleave U/V */
- (1 << 1) | /* must be y-tiled */
- (I965_TILEWALK_YMAJOR << 0)); /* tile walk, FIXME: must be 1 ??? */
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* must be 0 for interleave U/V */
- (obj_surface->height)); /* y offset for U(cb) */
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- int standard_select,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int i;
-
- BEGIN_BCS_BATCH(batch, 24);
- OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
- if (gen6_mfd_context->pre_deblocking_output.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- if (gen6_mfd_context->post_deblocking_output.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
- OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
-
- if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- /* DW 7..22 */
- for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
- struct object_surface *obj_surface;
-
- if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
- gen6_mfd_context->reference_surface[i].obj_surface &&
- gen6_mfd_context->reference_surface[i].obj_surface->bo) {
- obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
-
- OUT_BCS_RELOC(batch, obj_surface->bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- }
-
- OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
- dri_bo *slice_data_bo,
- int standard_select,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, 11);
- OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
- OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- int standard_select,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
-
- if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- if (gen6_mfd_context->bitplane_read_buffer.valid)
- OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_avc_img_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int qm_present_flag;
- int img_struct;
- int mbaff_frame_flag;
- unsigned int width_in_mbs, height_in_mbs;
- VAPictureParameterBufferH264 *pic_param;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
-
- if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
- qm_present_flag = 1;
- else
- qm_present_flag = 0; /* built-in QM matrices */
-
- if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
- img_struct = 1;
- else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
- img_struct = 3;
- else
- img_struct = 0;
-
- if ((img_struct & 0x1) == 0x1) {
- assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
- } else {
- assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
- }
-
- if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
- assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
- assert(pic_param->pic_fields.bits.field_pic_flag == 0);
- } else {
- assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
- }
-
- mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
- !pic_param->pic_fields.bits.field_pic_flag);
-
- width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
- height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
- assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
-
- /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
- assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
- pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
- assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
-
- BEGIN_BCS_BATCH(batch, 13);
- OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
- OUT_BCS_BATCH(batch,
- ((width_in_mbs * height_in_mbs) & 0x7fff));
- OUT_BCS_BATCH(batch,
- (height_in_mbs << 16) |
- (width_in_mbs << 0));
- OUT_BCS_BATCH(batch,
- ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
- ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
- (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
- (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
- (1 << 12) | /* always 1, hardware requirement */
- (qm_present_flag << 10) |
- (img_struct << 8) |
- (16 << 0));
- OUT_BCS_BATCH(batch,
- (pic_param->seq_fields.bits.chroma_format_idc << 10) |
- (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
- ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
- (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
- (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
- (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
- (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
- (mbaff_frame_flag << 1) |
- (pic_param->pic_fields.bits.field_pic_flag << 0));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_avc_qm_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int cmd_len;
- VAIQMatrixBufferH264 *iq_matrix;
- VAPictureParameterBufferH264 *pic_param;
-
- if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
- return;
-
- iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
-
- cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
-
- if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
- cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
-
- BEGIN_BCS_BATCH(batch, cmd_len);
- OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
-
- if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
- OUT_BCS_BATCH(batch,
- (0x0 << 8) | /* don't use default built-in matrices */
- (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
- else
- OUT_BCS_BATCH(batch,
- (0x0 << 8) | /* don't use default built-in matrices */
- (0x3f << 0)); /* six 4x4 scaling matrices */
-
- intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
-
- if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
- intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_avc_directmode_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- struct object_surface *obj_surface;
- GenAvcSurface *gen6_avc_surface;
- VAPictureH264 *va_pic;
- int i;
-
- BEGIN_BCS_BATCH(batch, 69);
- OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
-
- /* reference surfaces 0..15 */
- for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
- if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
- gen6_mfd_context->reference_surface[i].obj_surface &&
- gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
-
- obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
- gen6_avc_surface = obj_surface->private_data;
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
-
- if (gen6_avc_surface->dmv_bottom_flag == 1)
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- else
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- }
- }
-
- /* the current decoding frame/field */
- va_pic = &pic_param->CurrPic;
- obj_surface = decode_state->render_object;
- assert(obj_surface->bo && obj_surface->private_data);
- gen6_avc_surface = obj_surface->private_data;
-
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
-
- if (gen6_avc_surface->dmv_bottom_flag == 1)
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
-
- /* POC List */
- for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
- obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
-
- if (obj_surface) {
- const VAPictureH264 * const va_pic = avc_find_picture(
- obj_surface->base.id, pic_param->ReferenceFrames,
- ARRAY_ELEMS(pic_param->ReferenceFrames));
-
- assert(va_pic != NULL);
- OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
- OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
- } else {
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- }
- }
-
- va_pic = &pic_param->CurrPic;
- OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
- OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_avc_slice_state(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *slice_param,
- VASliceParameterBufferH264 *next_slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
- int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
- int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
- int num_ref_idx_l0, num_ref_idx_l1;
- int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
- pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
- int weighted_pred_idc = 0;
- int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
- unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
- int slice_type;
-
- if (slice_param->slice_type == SLICE_TYPE_I ||
- slice_param->slice_type == SLICE_TYPE_SI) {
- slice_type = SLICE_TYPE_I;
- } else if (slice_param->slice_type == SLICE_TYPE_P ||
- slice_param->slice_type == SLICE_TYPE_SP) {
- slice_type = SLICE_TYPE_P;
- } else {
- assert(slice_param->slice_type == SLICE_TYPE_B);
- slice_type = SLICE_TYPE_B;
- }
-
- luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
- chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
-
- if (slice_type == SLICE_TYPE_I) {
- assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
- assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
- num_ref_idx_l0 = 0;
- num_ref_idx_l1 = 0;
- } else if (slice_type == SLICE_TYPE_P) {
- assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
- num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_idx_l1 = 0;
- weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
- } else {
- num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
- weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
-
- if (weighted_pred_idc == 2) {
- /* 8.4.3 - Derivation process for prediction weights (8-279) */
- luma_log2_weight_denom = 5;
- chroma_log2_weight_denom = 5;
- }
- }
-
- first_mb_in_slice = slice_param->first_mb_in_slice;
- slice_hor_pos = first_mb_in_slice % width_in_mbs;
- slice_ver_pos = first_mb_in_slice / width_in_mbs;
-
- if (mbaff_picture)
- slice_ver_pos = slice_ver_pos << 1;
-
- if (next_slice_param) {
- first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
- next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
- next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
-
- if (mbaff_picture)
- next_slice_ver_pos = next_slice_ver_pos << 1;
- } else {
- next_slice_hor_pos = 0;
- next_slice_ver_pos = height_in_mbs;
- }
-
- BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
- OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
- OUT_BCS_BATCH(batch, slice_type);
- OUT_BCS_BATCH(batch,
- (num_ref_idx_l1 << 24) |
- (num_ref_idx_l0 << 16) |
- (chroma_log2_weight_denom << 8) |
- (luma_log2_weight_denom << 0));
- OUT_BCS_BATCH(batch,
- (weighted_pred_idc << 30) |
- (slice_param->direct_spatial_mv_pred_flag << 29) |
- (slice_param->disable_deblocking_filter_idc << 27) |
- (slice_param->cabac_init_idc << 24) |
- ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
- ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
- ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
- OUT_BCS_BATCH(batch,
- (slice_ver_pos << 24) |
- (slice_hor_pos << 16) |
- (first_mb_in_slice << 0));
- OUT_BCS_BATCH(batch,
- (next_slice_ver_pos << 16) |
- (next_slice_hor_pos << 0));
- OUT_BCS_BATCH(batch,
- (next_slice_param == NULL) << 19); /* last slice flag */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static inline void
-gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- gen6_send_avc_ref_idx_state(
- gen6_mfd_context->base.batch,
- slice_param,
- gen6_mfd_context->reference_surface
- );
-}
-
-static void
-gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int i, j, num_weight_offset_table = 0;
- short weightoffsets[32 * 6];
-
- if ((slice_param->slice_type == SLICE_TYPE_P ||
- slice_param->slice_type == SLICE_TYPE_SP) &&
- (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
- num_weight_offset_table = 1;
- }
-
- if ((slice_param->slice_type == SLICE_TYPE_B) &&
- (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
- num_weight_offset_table = 2;
- }
-
- for (i = 0; i < num_weight_offset_table; i++) {
- BEGIN_BCS_BATCH(batch, 98);
- OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
- OUT_BCS_BATCH(batch, i);
-
- if (i == 0) {
- for (j = 0; j < 32; j++) {
- weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
- weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
- weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
- weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
- weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
- weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
- }
- } else {
- for (j = 0; j < 32; j++) {
- weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
- weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
- weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
- weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
- weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
- weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
- }
- }
-
- intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
- ADVANCE_BCS_BATCH(batch);
- }
-}
-
-static void
-gen6_mfd_avc_bsd_object(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *slice_param,
- dri_bo *slice_data_bo,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- unsigned int slice_data_bit_offset;
-
- slice_data_bit_offset = avc_get_first_mb_bit_offset(
- slice_data_bo,
- slice_param,
- pic_param->pic_fields.bits.entropy_coding_mode_flag
- );
-
- BEGIN_BCS_BATCH(batch, 6);
- OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
- OUT_BCS_BATCH(batch,
- (slice_param->slice_data_size - slice_param->slice_data_offset));
- OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
- OUT_BCS_BATCH(batch,
- (0 << 31) |
- (0 << 14) |
- (0 << 12) |
- (0 << 10) |
- (0 << 8));
- OUT_BCS_BATCH(batch,
- ((slice_data_bit_offset >> 3) << 16) |
- (1 << 7) |
- (1 << 6) |
- ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- VASliceParameterBufferH264 *next_slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context->base.batch);
-}
-
-static void
-gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
- VAPictureParameterBufferH264 *pic_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context->base.batch);
-}
-
-static void
-gen6_mfd_avc_decode_init(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- VAPictureParameterBufferH264 *pic_param;
- VASliceParameterBufferH264 *slice_param;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct object_surface *obj_surface;
- dri_bo *bo;
- int i, j, enable_avc_ildb = 0;
- int width_in_mbs;
-
- for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
- assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
- slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
-
- for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
- assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
- assert((slice_param->slice_type == SLICE_TYPE_I) ||
- (slice_param->slice_type == SLICE_TYPE_SI) ||
- (slice_param->slice_type == SLICE_TYPE_P) ||
- (slice_param->slice_type == SLICE_TYPE_SP) ||
- (slice_param->slice_type == SLICE_TYPE_B));
-
- if (slice_param->disable_deblocking_filter_idc != 1) {
- enable_avc_ildb = 1;
- break;
- }
-
- slice_param++;
- }
- }
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
- intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
- gen6_mfd_context->reference_surface, &gen6_mfd_context->fs_ctx);
- width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
-
- /* Current decoded picture */
- obj_surface = decode_state->render_object;
- if (pic_param->pic_fields.bits.reference_pic_flag)
- obj_surface->flags |= SURFACE_REFERENCED;
- else
- obj_surface->flags &= ~SURFACE_REFERENCED;
-
- avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
- gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
-
- dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
- gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
- gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
-
- dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
-
- dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "intra row store",
- width_in_mbs * 64,
- 0x1000);
- assert(bo);
- gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "deblocking filter row store",
- width_in_mbs * 64 * 4,
- 0x1000);
- assert(bo);
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "bsd mpc row store",
- width_in_mbs * 96,
- 0x1000);
- assert(bo);
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "mpr row store",
- width_in_mbs * 64,
- 0x1000);
- assert(bo);
- gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
-
- gen6_mfd_context->bitplane_read_buffer.valid = 0;
-}
-
-static void
-gen6_mfd_avc_decode_picture(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferH264 *pic_param;
- VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
- dri_bo *slice_data_bo;
- int i, j;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
- gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
-
- intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
- intel_batchbuffer_emit_mi_flush(batch);
- gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
- gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
- gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
- gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
- gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
- gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
-
- for (j = 0; j < decode_state->num_slice_params; j++) {
- assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
- slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
- slice_data_bo = decode_state->slice_datas[j]->bo;
- gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
-
- if (j == decode_state->num_slice_params - 1)
- next_slice_group_param = NULL;
- else
- next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
-
- if (j == 0 &&
- slice_param->first_mb_in_slice)
- gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
-
- for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
- assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
- assert((slice_param->slice_type == SLICE_TYPE_I) ||
- (slice_param->slice_type == SLICE_TYPE_SI) ||
- (slice_param->slice_type == SLICE_TYPE_P) ||
- (slice_param->slice_type == SLICE_TYPE_SP) ||
- (slice_param->slice_type == SLICE_TYPE_B));
-
- if (i < decode_state->slice_params[j]->num_elements - 1)
- next_slice_param = slice_param + 1;
- else
- next_slice_param = next_slice_group_param;
-
- gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
- gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
- gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
- gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
- gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
- slice_param++;
- }
- }
-
- gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
- intel_batchbuffer_end_atomic(batch);
- intel_batchbuffer_flush(batch);
-}
-
-static void
-gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- VAPictureParameterBufferMPEG2 *pic_param;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct object_surface *obj_surface;
- dri_bo *bo;
- unsigned int width_in_mbs;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
- width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
-
- mpeg2_set_reference_surfaces(
- ctx,
- gen6_mfd_context->reference_surface,
- decode_state,
- pic_param
- );
-
- /* Current decoded picture */
- obj_surface = decode_state->render_object;
- i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
-
- dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "bsd mpc row store",
- width_in_mbs * 96,
- 0x1000);
- assert(bo);
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
-
- gen6_mfd_context->post_deblocking_output.valid = 0;
- gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
- gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
- gen6_mfd_context->bitplane_read_buffer.valid = 0;
-}
-
-static void
-gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferMPEG2 *pic_param;
- unsigned int tff, pic_structure;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
-
- pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
- if (pic_structure == MPEG_FRAME)
- tff = pic_param->picture_coding_extension.bits.top_field_first;
- else
- tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
- (pic_structure & MPEG_TOP_FIELD));
-
- BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
- OUT_BCS_BATCH(batch,
- (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
- ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
- ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
- ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
- pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
- pic_param->picture_coding_extension.bits.picture_structure << 12 |
- tff << 11 |
- pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
- pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
- pic_param->picture_coding_extension.bits.q_scale_type << 8 |
- pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
- pic_param->picture_coding_extension.bits.alternate_scan << 6);
- OUT_BCS_BATCH(batch,
- pic_param->picture_coding_type << 9);
- OUT_BCS_BATCH(batch,
- (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
- (ALIGN(pic_param->horizontal_size, 16) / 16));
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
- int i, j;
-
- /* Update internal QM state */
- if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
- VAIQMatrixBufferMPEG2 * const iq_matrix =
- (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
-
- gen_iq_matrix->load_intra_quantiser_matrix =
- iq_matrix->load_intra_quantiser_matrix;
- if (iq_matrix->load_intra_quantiser_matrix) {
- for (j = 0; j < 64; j++)
- gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
- iq_matrix->intra_quantiser_matrix[j];
- }
-
- gen_iq_matrix->load_non_intra_quantiser_matrix =
- iq_matrix->load_non_intra_quantiser_matrix;
- if (iq_matrix->load_non_intra_quantiser_matrix) {
- for (j = 0; j < 64; j++)
- gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
- iq_matrix->non_intra_quantiser_matrix[j];
- }
- }
-
- /* Commit QM state to HW */
- for (i = 0; i < 2; i++) {
- unsigned char *qm = NULL;
-
- if (i == 0) {
- if (gen_iq_matrix->load_intra_quantiser_matrix)
- qm = gen_iq_matrix->intra_quantiser_matrix;
- } else {
- if (gen_iq_matrix->load_non_intra_quantiser_matrix)
- qm = gen_iq_matrix->non_intra_quantiser_matrix;
- }
-
- if (!qm)
- continue;
-
- BEGIN_BCS_BATCH(batch, 18);
- OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
- OUT_BCS_BATCH(batch, i);
- intel_batchbuffer_data(batch, qm, 64);
- ADVANCE_BCS_BATCH(batch);
- }
-}
-
-static void
-gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
- VAPictureParameterBufferMPEG2 *pic_param,
- VASliceParameterBufferMPEG2 *slice_param,
- VASliceParameterBufferMPEG2 *next_slice_param,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
- int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
-
- if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
- pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
- is_field_pic = 1;
- is_field_pic_wa = is_field_pic &&
- gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
-
- vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
- hpos0 = slice_param->slice_horizontal_position;
-
- if (next_slice_param == NULL) {
- vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
- hpos1 = 0;
- } else {
- vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
- hpos1 = next_slice_param->slice_horizontal_position;
- }
-
- mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
-
- BEGIN_BCS_BATCH(batch, 5);
- OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
- OUT_BCS_BATCH(batch,
- slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
- OUT_BCS_BATCH(batch,
- slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
- OUT_BCS_BATCH(batch,
- hpos0 << 24 |
- vpos0 << 16 |
- mb_count << 8 |
- (next_slice_param == NULL) << 5 |
- (next_slice_param == NULL) << 3 |
- (slice_param->macroblock_offset & 0x7));
- OUT_BCS_BATCH(batch,
- slice_param->quantiser_scale_code << 24);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferMPEG2 *pic_param;
- VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
- dri_bo *slice_data_bo;
- int group_idx = 0, pre_group_idx = -1, element_idx = 0;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
-
- gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
- intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
- intel_batchbuffer_emit_mi_flush(batch);
- gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
- gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
- gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
- gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
- gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
- gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
-
- if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
- gen6_mfd_context->wa_mpeg2_slice_vertical_position =
- mpeg2_wa_slice_vertical_position(decode_state, pic_param);
-
- slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
-
- for (; slice_param;) {
- if (pre_group_idx != group_idx) {
- slice_data_bo = decode_state->slice_datas[group_idx]->bo;
- gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
- pre_group_idx = group_idx;
- }
-
- next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
- gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
- slice_param = next_slice_param;
- }
-
- intel_batchbuffer_end_atomic(batch);
- intel_batchbuffer_flush(batch);
-}
-
-static const int va_to_gen6_vc1_pic_type[5] = {
- GEN6_VC1_I_PICTURE,
- GEN6_VC1_P_PICTURE,
- GEN6_VC1_B_PICTURE,
- GEN6_VC1_BI_PICTURE,
- GEN6_VC1_P_PICTURE,
-};
-
-static const int va_to_gen6_vc1_mv[4] = {
- 1, /* 1-MV */
- 2, /* 1-MV half-pel */
- 3, /* 1-MV half-pef bilinear */
- 0, /* Mixed MV */
-};
-
-static const int b_picture_scale_factor[21] = {
- 128, 85, 170, 64, 192,
- 51, 102, 153, 204, 43,
- 215, 37, 74, 111, 148,
- 185, 222, 32, 96, 160,
- 224,
-};
-
-static const int va_to_gen6_vc1_condover[3] = {
- 0,
- 2,
- 3
-};
-
-static const int va_to_gen6_vc1_profile[4] = {
- GEN6_VC1_SIMPLE_PROFILE,
- GEN6_VC1_MAIN_PROFILE,
- GEN6_VC1_RESERVED_PROFILE,
- GEN6_VC1_ADVANCED_PROFILE
-};
-
-static void
-gen6_mfd_free_vc1_surface(void **data)
-{
- struct gen6_vc1_surface *gen6_vc1_surface = *data;
-
- if (!gen6_vc1_surface)
- return;
-
- dri_bo_unreference(gen6_vc1_surface->dmv);
- free(gen6_vc1_surface);
- *data = NULL;
-}
-
-static void
-gen6_mfd_init_vc1_surface(VADriverContextP ctx,
- VAPictureParameterBufferVC1 *pic_param,
- struct object_surface *obj_surface)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
- int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
-
- obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
-
- if (!gen6_vc1_surface) {
- gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
-
- if (!gen6_vc1_surface)
- return;
-
- assert((obj_surface->size & 0x3f) == 0);
- obj_surface->private_data = gen6_vc1_surface;
- }
-
- gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
-
- if (gen6_vc1_surface->dmv == NULL) {
- gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
- "direct mv w/r buffer",
- 128 * height_in_mbs * 64, /* scalable with frame height */
- 0x1000);
- }
-}
-
-static void
-gen6_mfd_vc1_decode_init(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- VAPictureParameterBufferVC1 *pic_param;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct object_surface *obj_surface;
- dri_bo *bo;
- int width_in_mbs;
- int picture_type;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
- width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
- picture_type = pic_param->picture_fields.bits.picture_type;
-
- intel_update_vc1_frame_store_index(ctx,
- decode_state,
- pic_param,
- gen6_mfd_context->reference_surface);
-
- /* Current decoded picture */
- obj_surface = decode_state->render_object;
- i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
- gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
-
- dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
- gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
- gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
-
- dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
- dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
-
- dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "intra row store",
- width_in_mbs * 64,
- 0x1000);
- assert(bo);
- gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "deblocking filter row store",
- width_in_mbs * 7 * 64,
- 0x1000);
- assert(bo);
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
-
- dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "bsd mpc row store",
- width_in_mbs * 96,
- 0x1000);
- assert(bo);
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
-
- gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
-
- gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
- dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
-
- if (gen6_mfd_context->bitplane_read_buffer.valid) {
- int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
- int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
- int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
- int src_w, src_h;
- uint8_t *src = NULL, *dst = NULL;
-
- assert(decode_state->bit_plane->buffer);
- src = decode_state->bit_plane->buffer;
-
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "VC-1 Bitplane",
- bitplane_width * height_in_mbs,
- 0x1000);
- assert(bo);
- gen6_mfd_context->bitplane_read_buffer.bo = bo;
-
- dri_bo_map(bo, True);
- assert(bo->virtual);
- dst = bo->virtual;
-
- for (src_h = 0; src_h < height_in_mbs; src_h++) {
- for(src_w = 0; src_w < width_in_mbs; src_w++) {
- int src_index, dst_index;
- int src_shift;
- uint8_t src_value;
-
- src_index = (src_h * width_in_mbs + src_w) / 2;
- src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
- src_value = ((src[src_index] >> src_shift) & 0xf);
-
- if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
- src_value |= 0x2;
- }
-
- dst_index = src_w / 2;
- dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
- }
-
- if (src_w & 1)
- dst[src_w / 2] >>= 4;
-
- dst += bitplane_width;
- }
-
- dri_bo_unmap(bo);
- } else
- gen6_mfd_context->bitplane_read_buffer.bo = NULL;
-}
-
-static void
-gen6_mfd_vc1_pic_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferVC1 *pic_param;
- struct object_surface *obj_surface;
- int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
- int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
- int unified_mv_mode;
- int ref_field_pic_polarity = 0;
- int scale_factor = 0;
- int trans_ac_y = 0;
- int dmv_surface_valid = 0;
- int brfd = 0;
- int fcm = 0;
- int picture_type;
- int profile;
- int overlap;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
-
- profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
- dquant = pic_param->pic_quantizer_fields.bits.dquant;
- dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
- dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
- dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
- dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
- dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
- alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
-
- if (dquant == 0) {
- alt_pquant_config = 0;
- alt_pquant_edge_mask = 0;
- } else if (dquant == 2) {
- alt_pquant_config = 1;
- alt_pquant_edge_mask = 0xf;
- } else {
- assert(dquant == 1);
- if (dquantfrm == 0) {
- alt_pquant_config = 0;
- alt_pquant_edge_mask = 0;
- alt_pq = 0;
- } else {
- assert(dquantfrm == 1);
- alt_pquant_config = 1;
-
- switch (dqprofile) {
- case 3:
- if (dqbilevel == 0) {
- alt_pquant_config = 2;
- alt_pquant_edge_mask = 0;
- } else {
- assert(dqbilevel == 1);
- alt_pquant_config = 3;
- alt_pquant_edge_mask = 0;
- }
- break;
-
- case 0:
- alt_pquant_edge_mask = 0xf;
- break;
-
- case 1:
- if (dqdbedge == 3)
- alt_pquant_edge_mask = 0x9;
- else
- alt_pquant_edge_mask = (0x3 << dqdbedge);
-
- break;
-
- case 2:
- alt_pquant_edge_mask = (0x1 << dqsbedge);
- break;
-
- default:
- assert(0);
- }
- }
- }
-
- if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
- assert(pic_param->mv_fields.bits.mv_mode2 < 4);
- unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
- } else {
- assert(pic_param->mv_fields.bits.mv_mode < 4);
- unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
- }
-
- if (pic_param->sequence_fields.bits.interlace == 1 &&
- pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
- /* FIXME: calculate reference field picture polarity */
- assert(0);
- ref_field_pic_polarity = 0;
- }
-
- if (pic_param->b_picture_fraction < 21)
- scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
-
- picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
-
- if (profile == GEN6_VC1_ADVANCED_PROFILE &&
- picture_type == GEN6_VC1_I_PICTURE)
- picture_type = GEN6_VC1_BI_PICTURE;
-
- if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
- trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
- else {
- trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
- /*
- * 8.3.6.2.1 Transform Type Selection
- * If variable-sized transform coding is not enabled,
- * then the 8x8 transform shall be used for all blocks.
- * it is also MFX_VC1_PIC_STATE requirement.
- */
- if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
- pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
- pic_param->transform_fields.bits.frame_level_transform_type = 0;
- }
- }
-
- if (picture_type == GEN6_VC1_B_PICTURE) {
- struct gen6_vc1_surface *gen6_vc1_surface = NULL;
-
- obj_surface = decode_state->reference_objects[1];
-
- if (obj_surface)
- gen6_vc1_surface = obj_surface->private_data;
-
- if (!gen6_vc1_surface ||
- (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
- va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
- dmv_surface_valid = 0;
- else
- dmv_surface_valid = 1;
- }
-
- assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
-
- if (pic_param->picture_fields.bits.frame_coding_mode < 2)
- fcm = pic_param->picture_fields.bits.frame_coding_mode;
- else {
- if (pic_param->picture_fields.bits.top_field_first)
- fcm = 2;
- else
- fcm = 3;
- }
-
- if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
- brfd = pic_param->reference_fields.bits.reference_distance;
- brfd = (scale_factor * brfd) >> 8;
- brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
-
- if (brfd < 0)
- brfd = 0;
- }
-
- overlap = pic_param->sequence_fields.bits.overlap;
-
- if (overlap) {
- overlap = 0;
- if (profile != GEN6_VC1_ADVANCED_PROFILE){
- if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
- pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
- overlap = 1;
- }
- }else {
- if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
- pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
- overlap = 1;
- }
- if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
- pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
- if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
- overlap = 1;
- } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
- va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
- overlap = 1;
- }
- }
- }
- }
-
- assert(pic_param->conditional_overlap_flag < 3);
- assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
-
- BEGIN_BCS_BATCH(batch, 6);
- OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
- OUT_BCS_BATCH(batch,
- (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
- (ALIGN(pic_param->coded_width, 16) / 16));
- OUT_BCS_BATCH(batch,
- pic_param->sequence_fields.bits.syncmarker << 31 |
- 1 << 29 | /* concealment */
- alt_pq << 24 |
- pic_param->entrypoint_fields.bits.loopfilter << 23 |
- overlap << 22 |
- (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
- pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
- alt_pquant_edge_mask << 12 |
- alt_pquant_config << 10 |
- pic_param->pic_quantizer_fields.bits.half_qp << 9 |
- pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
- va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
- !pic_param->picture_fields.bits.is_first_field << 5 |
- picture_type << 2 |
- fcm << 0);
- OUT_BCS_BATCH(batch,
- !!pic_param->bitplane_present.value << 23 |
- !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
- !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
- !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
- !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
- !pic_param->bitplane_present.flags.bp_overflags << 18 |
- !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
- !pic_param->bitplane_present.flags.bp_field_tx << 16 |
- pic_param->mv_fields.bits.extended_dmv_range << 14 |
- pic_param->mv_fields.bits.extended_mv_range << 12 |
- pic_param->mv_fields.bits.four_mv_switch << 11 |
- pic_param->fast_uvmc_flag << 10 |
- unified_mv_mode << 8 |
- ref_field_pic_polarity << 6 |
- pic_param->reference_fields.bits.num_reference_pictures << 5 |
- pic_param->reference_fields.bits.reference_distance << 0);
- OUT_BCS_BATCH(batch,
- scale_factor << 24 |
- pic_param->mv_fields.bits.mv_table << 20 |
- pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
- pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
- pic_param->transform_fields.bits.frame_level_transform_type << 12 |
- pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
- pic_param->mb_mode_table << 8 |
- trans_ac_y << 6 |
- pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
- pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
- pic_param->cbp_table << 0);
- OUT_BCS_BATCH(batch,
- dmv_surface_valid << 13 |
- brfd << 8 |
- ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferVC1 *pic_param;
- int interpolation_mode = 0;
- int intensitycomp_single;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
-
- if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
- (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
- pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
- interpolation_mode = 2; /* Half-pel bilinear */
- else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
- (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
- pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
- interpolation_mode = 0; /* Half-pel bicubic */
- else
- interpolation_mode = 1; /* Quarter-pel bicubic */
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
- intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
-
- BEGIN_BCS_BATCH(batch, 7);
- OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
- OUT_BCS_BATCH(batch,
- 0 << 8 | /* FIXME: interlace mode */
- pic_param->rounding_control << 4 |
- va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
- OUT_BCS_BATCH(batch,
- pic_param->luma_shift << 16 |
- pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- interpolation_mode << 19 |
- pic_param->fast_uvmc_flag << 18 |
- 0 << 17 | /* FIXME: scale up or down ??? */
- pic_param->range_reduction_frame << 16 |
- 0 << 6 | /* FIXME: double ??? */
- 0 << 4 |
- intensitycomp_single << 2 |
- intensitycomp_single << 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-static void
-gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- struct object_surface *obj_surface;
- dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
-
- obj_surface = decode_state->render_object;
-
- if (obj_surface && obj_surface->private_data) {
- dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
- }
-
- obj_surface = decode_state->reference_objects[1];
-
- if (obj_surface && obj_surface->private_data) {
- dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
- }
-
- BEGIN_BCS_BATCH(batch, 3);
- OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
-
- if (dmv_write_buffer)
- OUT_BCS_RELOC(batch, dmv_write_buffer,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- if (dmv_read_buffer)
- OUT_BCS_RELOC(batch, dmv_read_buffer,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- else
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static int
-gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
-{
- int out_slice_data_bit_offset;
- int slice_header_size = in_slice_data_bit_offset / 8;
- int i, j;
-
- if (profile != 3)
- out_slice_data_bit_offset = in_slice_data_bit_offset;
- else {
- for (i = 0, j = 0; i < slice_header_size; i++, j++) {
- if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
- i++, j += 2;
- }
- }
-
- out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
- }
-
- return out_slice_data_bit_offset;
-}
-
-static void
-gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
- VAPictureParameterBufferVC1 *pic_param,
- VASliceParameterBufferVC1 *slice_param,
- VASliceParameterBufferVC1 *next_slice_param,
- dri_bo *slice_data_bo,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- int next_slice_start_vert_pos;
- int macroblock_offset;
- uint8_t *slice_data = NULL;
-
- dri_bo_map(slice_data_bo, 0);
- slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
- macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
- slice_param->macroblock_offset,
- pic_param->sequence_fields.bits.profile);
- dri_bo_unmap(slice_data_bo);
-
- if (next_slice_param)
- next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
- else
- next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
-
- BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
- OUT_BCS_BATCH(batch,
- slice_param->slice_data_size - (macroblock_offset >> 3));
- OUT_BCS_BATCH(batch,
- slice_param->slice_data_offset + (macroblock_offset >> 3));
- OUT_BCS_BATCH(batch,
- slice_param->slice_vertical_position << 24 |
- next_slice_start_vert_pos << 16 |
- (macroblock_offset & 0x7));
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
- struct decode_state *decode_state,
- struct gen6_mfd_context *gen6_mfd_context)
-{
- struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
- VAPictureParameterBufferVC1 *pic_param;
- VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
- dri_bo *slice_data_bo;
- int i, j;
-
- assert(decode_state->pic_param && decode_state->pic_param->buffer);
- pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
-
- gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
- intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
- intel_batchbuffer_emit_mi_flush(batch);
- gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
- gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
- gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
- gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
- gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
- gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
- gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
-
- for (j = 0; j < decode_state->num_slice_params; j++) {
- assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
- slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
- slice_data_bo = decode_state->slice_datas[j]->bo;
- gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
-
- if (j == decode_state->num_slice_params - 1)
- next_slice_group_param = NULL;
- else
- next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
-
- for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
- assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
-
- if (i < decode_state->slice_params[j]->num_elements - 1)
- next_slice_param = slice_param + 1;
- else
- next_slice_param = next_slice_group_param;
-
- gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
- slice_param++;
- }
- }
-
- intel_batchbuffer_end_atomic(batch);
- intel_batchbuffer_flush(batch);
-}
-
-static VAStatus
-gen6_mfd_decode_picture(VADriverContextP ctx,
- VAProfile profile,
- union codec_state *codec_state,
- struct hw_context *hw_context)
-
-{
- struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
- struct decode_state *decode_state = &codec_state->decode;
- VAStatus vaStatus;
-
- assert(gen6_mfd_context);
-
- vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
-
- if (vaStatus != VA_STATUS_SUCCESS)
- goto out;
-
- switch (profile) {
- case VAProfileMPEG2Simple:
- case VAProfileMPEG2Main:
- gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
- break;
-
- case VAProfileH264ConstrainedBaseline:
- case VAProfileH264Main:
- case VAProfileH264High:
- case VAProfileH264StereoHigh:
- gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
- break;
-
- case VAProfileVC1Simple:
- case VAProfileVC1Main:
- case VAProfileVC1Advanced:
- gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
- break;
-
- default:
- assert(0);
- break;
- }
-
- vaStatus = VA_STATUS_SUCCESS;
-
-out:
- return vaStatus;
-}
-
-static void
-gen6_mfd_context_destroy(void *hw_context)
-{
- struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
-
- dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
- gen6_mfd_context->post_deblocking_output.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
- gen6_mfd_context->pre_deblocking_output.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
- gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
- gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
- gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
- gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
-
- dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
- gen6_mfd_context->bitplane_read_buffer.bo = NULL;
-
- intel_batchbuffer_free(gen6_mfd_context->base.batch);
- free(gen6_mfd_context);
-}
-
-struct hw_context *
-gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
-{
- struct intel_driver_data *intel = intel_driver_data(ctx);
- struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
- int i;
-
- if (!gen6_mfd_context)
- return NULL;
-
- gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
- gen6_mfd_context->base.run = gen6_mfd_decode_picture;
- gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
-
- for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
- gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
- gen6_mfd_context->reference_surface[i].frame_store_id = -1;
- gen6_mfd_context->reference_surface[i].obj_surface = NULL;
- }
-
- gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
-
- return (struct hw_context *)gen6_mfd_context;
-}
diff --git a/src/gen6_mfd.h b/src/gen6_mfd.h
deleted file mode 100644
index f499803..0000000
--- a/src/gen6_mfd.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Xiang Haihao <haihao.xiang@intel.com>
- *
- */
-
-#ifndef _GEN6_MFD_H_
-#define _GEN6_MFD_H_
-
-#include <xf86drm.h>
-#include <drm.h>
-#include <i915_drm.h>
-#include <intel_bufmgr.h>
-#include "i965_decoder.h"
-
-#define GEN6_VC1_I_PICTURE 0
-#define GEN6_VC1_P_PICTURE 1
-#define GEN6_VC1_B_PICTURE 2
-#define GEN6_VC1_BI_PICTURE 3
-#define GEN6_VC1_SKIPPED_PICTURE 4
-
-#define GEN6_VC1_SIMPLE_PROFILE 0
-#define GEN6_VC1_MAIN_PROFILE 1
-#define GEN6_VC1_ADVANCED_PROFILE 2
-#define GEN6_VC1_RESERVED_PROFILE 3
-
-struct gen6_vc1_surface
-{
- dri_bo *dmv;
- int picture_type;
-};
-
-struct hw_context;
-
-struct gen6_mfd_context
-{
- struct hw_context base;
-
- union {
- VAIQMatrixBufferMPEG2 mpeg2;
- } iq_matrix;
-
- GenFrameStoreContext fs_ctx;
- GenFrameStore reference_surface[MAX_GEN_REFERENCE_FRAMES];
- GenBuffer post_deblocking_output;
- GenBuffer pre_deblocking_output;
- GenBuffer intra_row_store_scratch_buffer;
- GenBuffer deblocking_filter_row_store_scratch_buffer;
- GenBuffer bsd_mpc_row_store_scratch_buffer;
- GenBuffer mpr_row_store_scratch_buffer;
- GenBuffer bitplane_read_buffer;
-
- int wa_mpeg2_slice_vertical_position;
-};
-
-#endif /* _GEN6_MFD_H_ */
diff --git a/src/gen6_vme.c b/src/gen6_vme.c
deleted file mode 100644
index 97dc3c9..0000000
--- a/src/gen6_vme.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * Copyright © 2010-2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Zhou Chang <chang.zhou@intel.com>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-
-#include "intel_batchbuffer.h"
-#include "intel_driver.h"
-
-#include "i965_defines.h"
-#include "i965_drv_video.h"
-#include "i965_encoder.h"
-#include "gen6_vme.h"
-#include "gen6_mfc.h"
-
-#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
-#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
-#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
-
-#define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
-#define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
-#define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
-
-enum VIDEO_CODING_TYPE{
- VIDEO_CODING_AVC = 0,
- VIDEO_CODING_SUM
-};
-
-enum AVC_VME_KERNEL_TYPE{
- AVC_VME_INTRA_SHADER = 0,
- AVC_VME_INTER_SHADER,
- AVC_VME_BATCHBUFFER,
- AVC_VME_KERNEL_SUM
-};
-
-static const uint32_t gen6_vme_intra_frame[][4] = {
-#include "shaders/vme/intra_frame.g6b"
-};
-
-static const uint32_t gen6_vme_inter_frame[][4] = {
-#include "shaders/vme/inter_frame.g6b"
-};
-
-static const uint32_t gen6_vme_batchbuffer[][4] = {
-#include "shaders/vme/batchbuffer.g6b"
-};
-
-static struct i965_kernel gen6_vme_kernels[] = {
- {
- "AVC VME Intra Frame",
- AVC_VME_INTRA_SHADER, /*index*/
- gen6_vme_intra_frame,
- sizeof(gen6_vme_intra_frame),
- NULL
- },
- {
- "AVC VME inter Frame",
- AVC_VME_INTER_SHADER,
- gen6_vme_inter_frame,
- sizeof(gen6_vme_inter_frame),
- NULL
- },
- {
- "AVC VME BATCHBUFFER",
- AVC_VME_BATCHBUFFER,
- gen6_vme_batchbuffer,
- sizeof(gen6_vme_batchbuffer),
- NULL
- },
-};
-
-/* only used for VME source surface state */
-static void
-gen6_vme_source_surface_state(VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
-
- vme_context->vme_surface2_setup(ctx,
- &vme_context->gpe_context,
- obj_surface,
- BINDING_TABLE_OFFSET(index),
- SURFACE_STATE_OFFSET(index));
-}
-
-static void
-gen6_vme_media_source_surface_state(VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
-
- vme_context->vme_media_rw_surface_setup(ctx,
- &vme_context->gpe_context,
- obj_surface,
- BINDING_TABLE_OFFSET(index),
- SURFACE_STATE_OFFSET(index),
- 0);
-}
-
-static void
-gen6_vme_output_buffer_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- int index,
- struct intel_encoder_context *encoder_context)
-
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
-
- vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
- vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
-
- if (is_intra)
- vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
- else
- vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
-
- vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
- "VME output buffer",
- vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
- 0x1000);
- assert(vme_context->vme_output.bo);
- vme_context->vme_buffer_suface_setup(ctx,
- &vme_context->gpe_context,
- &vme_context->vme_output,
- BINDING_TABLE_OFFSET(index),
- SURFACE_STATE_OFFSET(index));
-}
-
-static void
-gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- int index,
- struct intel_encoder_context *encoder_context)
-
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
-
- vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
- vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
- vme_context->vme_batchbuffer.pitch = 16;
- vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
- "VME batchbuffer",
- vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
- 0x1000);
- vme_context->vme_buffer_suface_setup(ctx,
- &vme_context->gpe_context,
- &vme_context->vme_batchbuffer,
- BINDING_TABLE_OFFSET(index),
- SURFACE_STATE_OFFSET(index));
-}
-
-static VAStatus
-gen6_vme_surface_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- int is_intra,
- struct intel_encoder_context *encoder_context)
-{
- struct object_surface *obj_surface;
-
- /*Setup surfaces state*/
- /* current picture for encoding */
- obj_surface = encode_state->input_yuv_object;
- gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
- gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
-
- if (!is_intra) {
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int slice_type;
-
- slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
- assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
-
- intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen6_vme_source_surface_state);
-
- if (slice_type == SLICE_TYPE_B)
- intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen6_vme_source_surface_state);
- }
-
- /* VME output */
- gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
- gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
-
- return VA_STATUS_SUCCESS;
-}
-
-static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct gen6_interface_descriptor_data *desc;
- int i;
- dri_bo *bo;
-
- bo = vme_context->gpe_context.idrt.bo;
- dri_bo_map(bo, 1);
- assert(bo->virtual);
- desc = bo->virtual;
-
- for (i = 0; i < vme_context->vme_kernel_sum; i++) {
- struct i965_kernel *kernel;
- kernel = &vme_context->gpe_context.kernels[i];
- assert(sizeof(*desc) == 32);
- /*Setup the descritor table*/
- memset(desc, 0, sizeof(*desc));
- desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
- desc->desc2.sampler_count = 1; /* FIXME: */
- desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
- desc->desc3.binding_table_entry_count = 1; /* FIXME: */
- desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
- desc->desc4.constant_urb_entry_read_offset = 0;
- desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
-
- /*kernel start*/
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
- kernel->bo);
- /*Sampler State(VME state pointer)*/
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- (1 << 2), //
- i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
- vme_context->vme_state.bo);
- desc++;
- }
- dri_bo_unmap(bo);
-
- return VA_STATUS_SUCCESS;
-}
-
-static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- // unsigned char *constant_buffer;
- unsigned int *vme_state_message;
- int mv_num = 32;
- if (vme_context->h264_level >= 30) {
- mv_num = 16;
- if (vme_context->h264_level >= 31)
- mv_num = 8;
- }
-
- dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
- assert(vme_context->gpe_context.curbe.bo->virtual);
- // constant_buffer = vme_context->curbe.bo->virtual;
- vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
- vme_state_message[31] = mv_num;
-
- /*TODO copy buffer into CURB*/
-
- dri_bo_unmap( vme_context->gpe_context.curbe.bo);
-
- return VA_STATUS_SUCCESS;
-}
-
-static const unsigned int intra_mb_mode_cost_table[] = {
- 0x31110001, // for qp0
- 0x09110001, // for qp1
- 0x15030001, // for qp2
- 0x0b030001, // for qp3
- 0x0d030011, // for qp4
- 0x17210011, // for qp5
- 0x41210011, // for qp6
- 0x19210011, // for qp7
- 0x25050003, // for qp8
- 0x1b130003, // for qp9
- 0x1d130003, // for qp10
- 0x27070021, // for qp11
- 0x51310021, // for qp12
- 0x29090021, // for qp13
- 0x35150005, // for qp14
- 0x2b0b0013, // for qp15
- 0x2d0d0013, // for qp16
- 0x37170007, // for qp17
- 0x61410031, // for qp18
- 0x39190009, // for qp19
- 0x45250015, // for qp20
- 0x3b1b000b, // for qp21
- 0x3d1d000d, // for qp22
- 0x47270017, // for qp23
- 0x71510041, // for qp24 ! center for qp=0..30
- 0x49290019, // for qp25
- 0x55350025, // for qp26
- 0x4b2b001b, // for qp27
- 0x4d2d001d, // for qp28
- 0x57370027, // for qp29
- 0x81610051, // for qp30
- 0x57270017, // for qp31
- 0x81510041, // for qp32 ! center for qp=31..51
- 0x59290019, // for qp33
- 0x65350025, // for qp34
- 0x5b2b001b, // for qp35
- 0x5d2d001d, // for qp36
- 0x67370027, // for qp37
- 0x91610051, // for qp38
- 0x69390029, // for qp39
- 0x75450035, // for qp40
- 0x6b3b002b, // for qp41
- 0x6d3d002d, // for qp42
- 0x77470037, // for qp43
- 0xa1710061, // for qp44
- 0x79490039, // for qp45
- 0x85550045, // for qp46
- 0x7b4b003b, // for qp47
- 0x7d4d003d, // for qp48
- 0x87570047, // for qp49
- 0xb1810071, // for qp50
- 0x89590049 // for qp51
-};
-
-static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- unsigned int *vme_state_message)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
-
- if (slice_param->slice_type != SLICE_TYPE_I &&
- slice_param->slice_type != SLICE_TYPE_SI)
- return;
-
- if (encoder_context->rate_control_mode == VA_RC_CQP)
- vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
- else
- vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][SLICE_TYPE_I]];
-}
-
-static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- int is_intra,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- unsigned int *vme_state_message;
- int i;
-
- //building VME state message
- dri_bo_map(vme_context->vme_state.bo, 1);
- assert(vme_context->vme_state.bo->virtual);
- vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
-
- if (encoder_context->quality_level != ENCODER_LOW_QUALITY) {
- vme_state_message[0] = 0x01010101;
- vme_state_message[1] = 0x10010101;
- vme_state_message[2] = 0x0F0F0F0F;
- vme_state_message[3] = 0x100F0F0F;
- vme_state_message[4] = 0x01010101;
- vme_state_message[5] = 0x10010101;
- vme_state_message[6] = 0x0F0F0F0F;
- vme_state_message[7] = 0x100F0F0F;
- vme_state_message[8] = 0x01010101;
- vme_state_message[9] = 0x10010101;
- vme_state_message[10] = 0x0F0F0F0F;
- vme_state_message[11] = 0x000F0F0F;
- vme_state_message[12] = 0x00;
- vme_state_message[13] = 0x00;
- } else {
- vme_state_message[0] = 0x10010101;
- vme_state_message[1] = 0x100F0F0F;
- vme_state_message[2] = 0x10010101;
- vme_state_message[3] = 0x000F0F0F;
- vme_state_message[4] = 0;
- vme_state_message[5] = 0;
- vme_state_message[6] = 0;
- vme_state_message[7] = 0;
- vme_state_message[8] = 0;
- vme_state_message[9] = 0;
- vme_state_message[10] = 0;
- vme_state_message[11] = 0;
- vme_state_message[12] = 0;
- vme_state_message[13] = 0;
- }
-
- vme_state_message[14] = 0x4a4a;
- vme_state_message[15] = 0x0;
- vme_state_message[16] = 0x4a4a4a4a;
- vme_state_message[17] = 0x4a4a4a4a;
- vme_state_message[18] = 0x21110100;
- vme_state_message[19] = 0x61514131;
-
- for(i = 20; i < 32; i++) {
- vme_state_message[i] = 0;
- }
- //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
-
- gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
-
- dri_bo_unmap( vme_context->vme_state.bo);
- return VA_STATUS_SUCCESS;
-}
-
-static void
-gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_width, int mb_height,
- int kernel,
- int transform_8x8_mode_flag,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- int number_mb_cmds;
- int mb_x = 0, mb_y = 0;
- int i, s;
- unsigned int *command_ptr;
-
- dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
- command_ptr = vme_context->vme_batchbuffer.bo->virtual;
-
- for (s = 0; s < encode_state->num_slice_params_ext; s++) {
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
- int slice_mb_begin = pSliceParameter->macroblock_address;
- int slice_mb_number = pSliceParameter->num_macroblocks;
-
- for (i = 0; i < slice_mb_number; ) {
- int mb_count = i + slice_mb_begin;
- mb_x = mb_count % mb_width;
- mb_y = mb_count / mb_width;
- if( i == 0 ) {
- number_mb_cmds = mb_width; // we must mark the slice edge.
- } else if ( (i + 128 ) <= slice_mb_number) {
- number_mb_cmds = 128;
- } else {
- number_mb_cmds = slice_mb_number - i;
- }
-
- *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
- *command_ptr++ = kernel;
- *command_ptr++ = 0;
- *command_ptr++ = 0;
- *command_ptr++ = 0;
- *command_ptr++ = 0;
-
- /*inline data */
- *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
- *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
- *command_ptr++ = encoder_context->quality_level;
-
- i += number_mb_cmds;
- }
- }
-
- *command_ptr++ = 0;
- *command_ptr++ = MI_BATCH_BUFFER_END;
-
- dri_bo_unmap(vme_context->vme_batchbuffer.bo);
-}
-
-static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- dri_bo *bo;
-
- i965_gpe_context_init(ctx, &vme_context->gpe_context);
-
- /* VME output buffer */
- dri_bo_unreference(vme_context->vme_output.bo);
- vme_context->vme_output.bo = NULL;
-
- dri_bo_unreference(vme_context->vme_batchbuffer.bo);
- vme_context->vme_batchbuffer.bo = NULL;
-
- /* VME state */
- dri_bo_unreference(vme_context->vme_state.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 1024*16, 64);
- assert(bo);
- vme_context->vme_state.bo = bo;
-}
-
-static void gen6_vme_pipeline_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
- int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
-
- gen6_vme_fill_vme_batchbuffer(ctx,
- encode_state,
- width_in_mbs, height_in_mbs,
- is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER,
- pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
- encoder_context);
-
- intel_batchbuffer_start_atomic(batch, 0x1000);
- gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
- BEGIN_BATCH(batch, 2);
- OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
- OUT_RELOC(batch,
- vme_context->vme_batchbuffer.bo,
- I915_GEM_DOMAIN_COMMAND, 0,
- 0);
- ADVANCE_BATCH(batch);
-
- intel_batchbuffer_end_atomic(batch);
-}
-
-static VAStatus gen6_vme_prepare(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- VAStatus vaStatus = VA_STATUS_SUCCESS;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
- int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
-
- if (!vme_context->h264_level ||
- (vme_context->h264_level != pSequenceParameter->level_idc)) {
- vme_context->h264_level = pSequenceParameter->level_idc;
- }
- /*Setup all the memory object*/
- gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
- gen6_vme_interface_setup(ctx, encode_state, encoder_context);
- gen6_vme_constant_setup(ctx, encode_state, encoder_context);
- gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
-
- /*Programing media pipeline*/
- gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
-
- return vaStatus;
-}
-
-static VAStatus gen6_vme_run(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
-
- intel_batchbuffer_flush(batch);
-
- return VA_STATUS_SUCCESS;
-}
-
-static VAStatus gen6_vme_stop(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- return VA_STATUS_SUCCESS;
-}
-
-static VAStatus
-gen6_vme_pipeline(VADriverContextP ctx,
- VAProfile profile,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- gen6_vme_media_init(ctx, encoder_context);
- gen6_vme_prepare(ctx, encode_state, encoder_context);
- gen6_vme_run(ctx, encode_state, encoder_context);
- gen6_vme_stop(ctx, encode_state, encoder_context);
-
- return VA_STATUS_SUCCESS;
-}
-
-static void
-gen6_vme_context_destroy(void *context)
-{
- struct gen6_vme_context *vme_context = context;
-
- i965_gpe_context_destroy(&vme_context->gpe_context);
-
- dri_bo_unreference(vme_context->vme_output.bo);
- vme_context->vme_output.bo = NULL;
-
- dri_bo_unreference(vme_context->vme_state.bo);
- vme_context->vme_state.bo = NULL;
-
- dri_bo_unreference(vme_context->vme_batchbuffer.bo);
- vme_context->vme_batchbuffer.bo = NULL;
-
- free(vme_context->qp_per_mb);
- vme_context->qp_per_mb = NULL;
-
- free(vme_context);
-}
-
-Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct gen6_vme_context *vme_context = NULL;
-
- if (encoder_context->codec != CODEC_H264) {
- /* Never get here */
- assert(0);
- return False;
- }
-
- vme_context = calloc(1, sizeof(struct gen6_vme_context));
-
- if (!vme_context)
- return False;
-
- vme_context->gpe_context.surface_state_binding_table.length =
- (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
-
- vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
- vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
- vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
-
- vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
- vme_context->gpe_context.vfe_state.num_urb_entries = 16;
- vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
- vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
- vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
-
- vme_context->video_coding_type = VIDEO_CODING_AVC;
- vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
- i965_gpe_load_kernels(ctx,
- &vme_context->gpe_context,
- gen6_vme_kernels,
- vme_context->vme_kernel_sum);
-
- encoder_context->vme_pipeline = gen6_vme_pipeline;
- vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
- vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
- vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
-
- encoder_context->vme_context = vme_context;
- encoder_context->vme_context_destroy = gen6_vme_context_destroy;
-
- return True;
-}
diff --git a/src/gen6_vme.h b/src/gen6_vme.h
deleted file mode 100644
index f94085f..0000000
--- a/src/gen6_vme.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWAR
- *
- * Authors:
- * Zhou Chang <chang.zhou@intel.com>
- *
- */
-
-#ifndef _GEN6_VME_H_
-#define _GEN6_VME_H_
-
-#include <xf86drm.h>
-#include <drm.h>
-#include <i915_drm.h>
-#include <intel_bufmgr.h>
-
-#include "i965_gpe_utils.h"
-
-#define INTRA_VME_OUTPUT_IN_BYTES 16 /* in bytes */
-#define INTRA_VME_OUTPUT_IN_DWS (INTRA_VME_OUTPUT_IN_BYTES / 4)
-#define INTER_VME_OUTPUT_IN_BYTES 160 /* the first 128 bytes for MVs and the last 32 bytes for other info */
-#define INTER_VME_OUTPUT_IN_DWS (INTER_VME_OUTPUT_IN_BYTES / 4)
-
-#define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS
-#define MAX_MEDIA_SURFACES_GEN6 34
-
-#define GEN6_VME_KERNEL_NUMBER 3
-
-#define INTEL_COST_TABLE_OFFSET 8
-
-struct encode_state;
-struct intel_encoder_context;
-
-struct gen6_vme_context
-{
- struct i965_gpe_context gpe_context;
-
- struct {
- dri_bo *bo;
- } vme_state;
-
- struct i965_buffer_surface vme_output;
- struct i965_buffer_surface vme_batchbuffer;
-
-
- void (*vme_surface2_setup)(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset);
- void (*vme_media_rw_surface_setup)(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset,
- int write_enabled);
- void (*vme_buffer_suface_setup)(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_buffer_surface *buffer_surface,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset);
- void (*vme_media_chroma_surface_setup)(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset,
- int write_enabled);
- void *vme_state_message;
- unsigned int h264_level;
- unsigned int hevc_level;
- unsigned int video_coding_type;
- unsigned int vme_kernel_sum;
- unsigned int mpeg2_level;
-
- struct object_surface *used_reference_objects[2];
- void *used_references[2];
- unsigned int ref_index_in_mb[2];
-
- dri_bo *i_qp_cost_table;
- dri_bo *p_qp_cost_table;
- dri_bo *b_qp_cost_table;
- int cost_table_size;
-
- /* one buffer define qp per mb. one byte for every mb.
- * If it needs to be accessed by GPU, it will be changed to dri_bo.
- */
- bool roi_enabled;
- char *qp_per_mb;
- int saved_width_mbs, saved_height_mbs;
-};
-
-#define MPEG2_PIC_WIDTH_HEIGHT 30
-#define MPEG2_MV_RANGE 29
-#define MPEG2_LEVEL_MASK 0x0f
-#define MPEG2_LEVEL_LOW 0x0a
-#define MPEG2_LEVEL_MAIN 0x08
-#define MPEG2_LEVEL_HIGH 0x04
-
-Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern void intel_vme_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-void intel_vme_vp8_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-#define MODE_INTRA_NONPRED 0
-#define MODE_INTRA_16X16 1
-#define MODE_INTRA_8X8 2
-#define MODE_INTRA_4X4 3
-#define MODE_INTER_16X8 4
-#define MODE_INTER_8X16 4
-#define MODE_INTER_8X8 5
-#define MODE_INTER_8X4 6
-#define MODE_INTER_4X8 6
-#define MODE_INTER_4X4 7
-#define MODE_INTER_16X16 8
-#define MODE_INTER_BWD 9
-#define MODE_REFID_COST 10
-#define MODE_CHROMA_INTRA 11
-
-#define MODE_INTER_MV0 12
-#define MODE_INTER_MV1 13
-#define MODE_INTER_MV2 14
-
-#define MODE_INTER_MV3 15
-#define MODE_INTER_MV4 16
-#define MODE_INTER_MV5 17
-#define MODE_INTER_MV6 18
-#define MODE_INTER_MV7 19
-
-#define INTRA_PRED_AVAIL_FLAG_AE 0x60
-#define INTRA_PRED_AVAIL_FLAG_B 0x10
-#define INTRA_PRED_AVAIL_FLAG_C 0x8
-#define INTRA_PRED_AVAIL_FLAG_D 0x4
-#define INTRA_PRED_AVAIL_FLAG_BCD_MASK 0x1C
-
-extern void
-gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_width, int mb_height,
- int kernel,
- int transform_8x8_mode_flag,
- struct intel_encoder_context *encoder_context);
-
-extern void
-gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_context);
-
-extern void
-intel_vme_mpeg2_state_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern void
-gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_width, int mb_height,
- int kernel,
- struct intel_encoder_context *encoder_context);
-
-void
-intel_avc_vme_reference_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int list_index,
- int surface_index,
- void (* vme_source_surface_state)(
- VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context));
-
-/* HEVC */
-void
-intel_hevc_vme_reference_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int list_index,
- int surface_index,
- void (* vme_source_surface_state)(
- VADriverContextP ctx,
- int index,
- struct object_surface *obj_surface,
- struct intel_encoder_context *encoder_context));
-
-void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-
-extern Bool gen8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
-
-extern void
-intel_h264_initialize_mbmv_cost(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-extern void
-intel_h264_setup_cost_surface(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- unsigned long binding_table_offset,
- unsigned long surface_state_offset);
-
-extern void
-intel_h264_enc_roi_config(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context);
-
-#endif /* _GEN6_VME_H_ */
diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
deleted file mode 100644
index 7b76b99..0000000
--- a/src/gen75_mfc.c
+++ /dev/null
@@ -1,2586 +0,0 @@
-/*
- * Copyright © 2010-2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Zhao Yakui <yakui.zhao@intel.com>
- * Xiang Haihao <haihao.xiang@intel.com>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <assert.h>
-
-#include "intel_batchbuffer.h"
-#include "i965_defines.h"
-#include "i965_structs.h"
-#include "i965_drv_video.h"
-#include "i965_encoder.h"
-#include "i965_encoder_utils.h"
-#include "gen6_mfc.h"
-#include "gen6_vme.h"
-#include "intel_media.h"
-
-#define AVC_INTRA_RDO_OFFSET 4
-#define AVC_INTER_RDO_OFFSET 10
-#define AVC_INTER_MSG_OFFSET 8
-#define AVC_INTER_MV_OFFSET 48
-#define AVC_RDO_MASK 0xFFFF
-
-#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
-#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
-#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
-
-#define B0_STEP_REV 2
-#define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
-
-static const uint32_t gen75_mfc_batchbuffer_avc[][4] = {
-#include "shaders/utils/mfc_batchbuffer_hsw.g75b"
-};
-
-static struct i965_kernel gen75_mfc_kernels[] = {
- {
- "MFC AVC INTRA BATCHBUFFER ",
- MFC_BATCHBUFFER_AVC_INTRA,
- gen75_mfc_batchbuffer_avc,
- sizeof(gen75_mfc_batchbuffer_avc),
- NULL
- },
-};
-
-#define INTER_MODE_MASK 0x03
-#define INTER_8X8 0x03
-#define INTER_16X8 0x01
-#define INTER_8X16 0x02
-#define SUBMB_SHAPE_MASK 0x00FF00
-
-#define INTER_MV8 (4 << 20)
-#define INTER_MV32 (6 << 20)
-
-
-static void
-gen75_mfc_pipe_mode_select(VADriverContextP ctx,
- int standard_select,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- assert(standard_select == MFX_FORMAT_MPEG2 ||
- standard_select == MFX_FORMAT_AVC);
-
- BEGIN_BCS_BATCH(batch, 5);
-
- OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
- OUT_BCS_BATCH(batch,
- (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
- (MFD_MODE_VLD << 15) | /* VLD mode */
- (0 << 10) | /* Stream-Out Enable */
- ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
- ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
- (0 << 5) | /* not in stitch mode */
- (1 << 4) | /* encoding mode */
- (standard_select << 0)); /* standard select: avc or mpeg2 */
- OUT_BCS_BATCH(batch,
- (0 << 7) | /* expand NOA bus flag */
- (0 << 6) | /* disable slice-level clock gating */
- (0 << 5) | /* disable clock gating for NOA */
- (0 << 4) | /* terminate if AVC motion and POC table error occurs */
- (0 << 3) | /* terminate if AVC mbdata error occurs */
- (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
- (0 << 1) |
- (0 << 0));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- BEGIN_BCS_BATCH(batch, 6);
-
- OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- ((mfc_context->surface_state.height - 1) << 18) |
- ((mfc_context->surface_state.width - 1) << 4));
- OUT_BCS_BATCH(batch,
- (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
- (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
- (0 << 22) | /* surface object control state, FIXME??? */
- ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
- (0 << 2) | /* must be 0 for interleave U/V */
- (1 << 1) | /* must be tiled */
- (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* must be 0 for interleave U/V */
- (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
-
- BEGIN_BCS_BATCH(batch, 26);
-
- OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
- /* the DW1-3 is for the MFX indirect bistream offset */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /* the DW4-5 is the MFX upper bound */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW6-10 is for MFX Indirect MV Object Base Address */
- OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW11-15 is for MFX IT-COFF. Not used on encoder */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- mfc_context->mfc_indirect_pak_bse_object.end_offset);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
-
- if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_ind_obj_base_addr_state_bplus(ctx, encoder_context);
- return;
- }
-
- BEGIN_BCS_BATCH(batch, 11);
-
- OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /* MFX Indirect MV Object Base Address */
- OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_RELOC(batch,
- mfc_context->mfc_indirect_pak_bse_object.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- mfc_context->mfc_indirect_pak_bse_object.end_offset);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
-
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
-
- BEGIN_BCS_BATCH(batch, 16);
-
- OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
- /*DW1. MB setting of frame */
- OUT_BCS_BATCH(batch,
- ((width_in_mbs * height_in_mbs - 1) & 0xFFFF));
- OUT_BCS_BATCH(batch,
- ((height_in_mbs - 1) << 16) |
- ((width_in_mbs - 1) << 0));
- /* DW3 QP setting */
- OUT_BCS_BATCH(batch,
- (0 << 24) | /* Second Chroma QP Offset */
- (0 << 16) | /* Chroma QP Offset */
- (0 << 14) | /* Max-bit conformance Intra flag */
- (0 << 13) | /* Max Macroblock size conformance Inter flag */
- (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */
- (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */
- (0 << 8) | /* FIXME: Image Structure */
- (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* Mininum Frame size */
- (0 << 15) | /* Disable reading of Macroblock Status Buffer */
- (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
- (0 << 13) | /* CABAC 0 word insertion test enable */
- (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
- (1 << 10) | /* Chroma Format IDC, 4:2:0 */
- (0 << 8) | /* FIXME: MbMvFormatFlag */
- (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
- (0 << 6) | /* Only valid for VLD decoding mode */
- (0 << 5) | /* Constrained Intra Predition Flag, from PPS */
- (0 << 4) | /* Direct 8x8 inference flag */
- (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
- (1 << 2) | /* Frame MB only flag */
- (0 << 1) | /* MBAFF mode is in active */
- (0 << 0)); /* Field picture flag */
- /* DW5 Trellis quantization */
- OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
- OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
- (0xBB8 << 16) | /* InterMbMaxSz */
- (0xEE8) ); /* IntraMbMaxSz */
- OUT_BCS_BATCH(batch, 0); /* Reserved */
- /* DW8. QP delta */
- OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
- OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
- /* DW10. Bit setting for MB */
- OUT_BCS_BATCH(batch, 0x8C000000);
- OUT_BCS_BATCH(batch, 0x00010000);
- /* DW12. */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0x02010100);
- /* DW14. For short format */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_qm_state(VADriverContextP ctx,
- int qm_type,
- unsigned int *qm,
- int qm_length,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- unsigned int qm_buffer[16];
-
- assert(qm_length <= 16);
- assert(sizeof(*qm) == 4);
- memcpy(qm_buffer, qm, qm_length * 4);
-
- BEGIN_BCS_BATCH(batch, 18);
- OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
- OUT_BCS_BATCH(batch, qm_type << 0);
- intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_qm_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- unsigned int qm[16] = {
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010
- };
-
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
-}
-
-static void
-gen75_mfc_fqm_state(VADriverContextP ctx,
- int fqm_type,
- unsigned int *fqm,
- int fqm_length,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- unsigned int fqm_buffer[32];
-
- assert(fqm_length <= 32);
- assert(sizeof(*fqm) == 4);
- memcpy(fqm_buffer, fqm, fqm_length * 4);
-
- BEGIN_BCS_BATCH(batch, 34);
- OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
- OUT_BCS_BATCH(batch, fqm_type << 0);
- intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_fqm_state(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- unsigned int qm[32] = {
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000,
- 0x10001000, 0x10001000, 0x10001000, 0x10001000
- };
-
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
-}
-
-static void
-gen75_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
- unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
- int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
- struct intel_batchbuffer *batch)
-{
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
-
- OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
- OUT_BCS_BATCH(batch,
- (0 << 16) | /* always start at offset 0 */
- (data_bits_in_last_dw << 8) |
- (skip_emul_byte_count << 4) |
- (!!emulation_flag << 3) |
- ((!!is_last_header) << 2) |
- ((!!is_end_of_slice) << 1) |
- (0 << 0)); /* FIXME: ??? */
- intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-static void gen75_mfc_init(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- dri_bo *bo;
- int i;
- int width_in_mbs = 0;
- int height_in_mbs = 0;
- int slice_batchbuffer_size;
-
- if (encoder_context->codec == CODEC_H264 ||
- encoder_context->codec == CODEC_H264_MVC) {
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- width_in_mbs = pSequenceParameter->picture_width_in_mbs;
- height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- } else {
- VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
-
- assert(encoder_context->codec == CODEC_MPEG2);
-
- width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
- height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
- }
-
- slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
- (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
-
- /*Encode common setup for MFC*/
- dri_bo_unreference(mfc_context->post_deblocking_output.bo);
- mfc_context->post_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
- mfc_context->pre_deblocking_output.bo = NULL;
-
- dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
- mfc_context->uncompressed_picture_source.bo = NULL;
-
- dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
- mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
-
- for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
- if (mfc_context->direct_mv_buffers[i].bo != NULL)
- dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
- mfc_context->direct_mv_buffers[i].bo = NULL;
- }
-
- for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
- if (mfc_context->reference_surfaces[i].bo != NULL)
- dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
- mfc_context->reference_surfaces[i].bo = NULL;
- }
-
- dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- width_in_mbs * 64,
- 64);
- assert(bo);
- mfc_context->intra_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- width_in_mbs * height_in_mbs * 16,
- 64);
- assert(bo);
- mfc_context->macroblock_status_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
- 64);
- assert(bo);
- mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
- bo = dri_bo_alloc(i965->intel.bufmgr,
- "Buffer",
- 2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */
- 0x1000);
- assert(bo);
- mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
-
- dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
- mfc_context->mfc_batchbuffer_surface.bo = NULL;
-
- dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->aux_batchbuffer_surface.bo = NULL;
-
- if (mfc_context->aux_batchbuffer)
- intel_batchbuffer_free(mfc_context->aux_batchbuffer);
-
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
- slice_batchbuffer_size);
- mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
- dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->aux_batchbuffer_surface.pitch = 16;
- mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
- mfc_context->aux_batchbuffer_surface.size_block = 16;
-
- i965_gpe_context_init(ctx, &mfc_context->gpe_context);
-}
-
-static void
-gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int i;
-
- BEGIN_BCS_BATCH(batch, 61);
-
- OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
-
- /* the DW1-3 is for pre_deblocking */
- if (mfc_context->pre_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0); /* pre output addr */
-
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- /* the DW4-6 is for the post_deblocking */
-
- if (mfc_context->post_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* post output addr */
- else
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW7-9 is for the uncompressed_picture */
- OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* uncompressed data */
-
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW10-12 is for the mb status */
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* StreamOut data*/
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW13-15 is for the intra_row_store_scratch */
- OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW16-18 is for the deblocking filter */
- OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW 19-50 is for Reference pictures*/
- for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
- if ( mfc_context->reference_surfaces[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- OUT_BCS_BATCH(batch, 0);
- }
- OUT_BCS_BATCH(batch, 0);
-
- /* The DW 52-54 is for the MB status buffer */
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* Macroblock status buffer*/
-
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW 55-57 is the ILDB buffer */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW 58-60 is the second ILDB buffer */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- int i;
-
- if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_pipe_buf_addr_state_bplus(ctx, encoder_context);
- return;
- }
-
- BEGIN_BCS_BATCH(batch, 25);
-
- OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
-
- if (mfc_context->pre_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- else
- OUT_BCS_BATCH(batch, 0); /* pre output addr */
-
- if (mfc_context->post_deblocking_output.bo)
- OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* post output addr */
- else
- OUT_BCS_BATCH(batch, 0);
-
- OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* uncompressed data */
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* StreamOut data*/
- OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- /* 7..22 Reference pictures*/
- for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
- if ( mfc_context->reference_surfaces[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- }
- OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0); /* Macroblock status buffer*/
-
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- int i;
-
- BEGIN_BCS_BATCH(batch, 71);
-
- OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
-
- /* Reference frames and Current frames */
- /* the DW1-32 is for the direct MV for reference */
- for(i = 0; i < NUM_MFC_DMV_BUFFERS - 2; i += 2) {
- if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- OUT_BCS_BATCH(batch, 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- }
- }
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW34-36 is the MV for the current reference */
- OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
-
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* POL list */
- for(i = 0; i < 32; i++) {
- OUT_BCS_BATCH(batch, i/2);
- }
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
- int i;
-
- if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_avc_directmode_state_bplus(ctx, encoder_context);
- return;
- }
-
- BEGIN_BCS_BATCH(batch, 69);
-
- OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
-
- /* Reference frames and Current frames */
- for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
- if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
- OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
- } else {
- OUT_BCS_BATCH(batch, 0);
- }
- }
-
- /* POL list */
- for(i = 0; i < 32; i++) {
- OUT_BCS_BATCH(batch, i/2);
- }
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-static void
-gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- BEGIN_BCS_BATCH(batch, 10);
-
- OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
- OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- /* the DW7-9 is for Bitplane Read Buffer Base Address */
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-static void
-gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
-
- if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_bsp_buf_base_addr_state_bplus(ctx, encoder_context);
- return;
- }
-
- BEGIN_BCS_BATCH(batch, 4);
-
- OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
- OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
- mfc_context->set_surface_state(ctx, encoder_context);
- mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
- gen75_mfc_pipe_buf_addr_state(ctx, encoder_context);
- gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
- mfc_context->avc_img_state(ctx, encode_state, encoder_context);
- mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
- mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
- gen75_mfc_avc_directmode_state(ctx, encoder_context);
- intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
-}
-
-
-static VAStatus gen75_mfc_run(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
-
- intel_batchbuffer_flush(batch); //run the pipeline
-
- return VA_STATUS_SUCCESS;
-}
-
-
-static VAStatus
-gen75_mfc_stop(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int *encoded_bits_size)
-{
- VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VACodedBufferSegment *coded_buffer_segment;
-
- vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
- assert(vaStatus == VA_STATUS_SUCCESS);
- *encoded_bits_size = coded_buffer_segment->size * 8;
- i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
-
- return VA_STATUS_SUCCESS;
-}
-
-
-static void
-gen75_mfc_avc_slice_state(VADriverContextP ctx,
- VAEncPictureParameterBufferH264 *pic_param,
- VAEncSliceParameterBufferH264 *slice_param,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int rate_control_enable,
- int qp,
- struct intel_batchbuffer *batch)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int beginmb = slice_param->macroblock_address;
- int endmb = beginmb + slice_param->num_macroblocks;
- int beginx = beginmb % width_in_mbs;
- int beginy = beginmb / width_in_mbs;
- int nextx = endmb % width_in_mbs;
- int nexty = endmb / width_in_mbs;
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
- int last_slice = (endmb == (width_in_mbs * height_in_mbs));
- int maxQpN, maxQpP;
- unsigned char correct[6], grow, shrink;
- int i;
- int weighted_pred_idc = 0;
- unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
- unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
- int num_ref_l0 = 0, num_ref_l1 = 0;
-
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- if (slice_type == SLICE_TYPE_I) {
- luma_log2_weight_denom = 0;
- chroma_log2_weight_denom = 0;
- } else if (slice_type == SLICE_TYPE_P) {
- weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
- num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
-
- if (slice_param->num_ref_idx_active_override_flag)
- num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- } else if (slice_type == SLICE_TYPE_B) {
- weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
- num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
-
- if (slice_param->num_ref_idx_active_override_flag) {
- num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
- num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
- }
-
- if (weighted_pred_idc == 2) {
- /* 8.4.3 - Derivation process for prediction weights (8-279) */
- luma_log2_weight_denom = 5;
- chroma_log2_weight_denom = 5;
- }
- }
-
- maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
- maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
-
- for (i = 0; i < 6; i++)
- correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
-
- grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
- (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
- shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
- (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
-
- BEGIN_BCS_BATCH(batch, 11);;
-
- OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
- OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
-
- OUT_BCS_BATCH(batch,
- (num_ref_l0 << 16) |
- (num_ref_l1 << 24) |
- (chroma_log2_weight_denom << 8) |
- (luma_log2_weight_denom << 0));
-
- OUT_BCS_BATCH(batch,
- (weighted_pred_idc << 30) |
- (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
- (slice_param->disable_deblocking_filter_idc << 27) |
- (slice_param->cabac_init_idc << 24) |
- (qp<<16) | /*Slice Quantization Parameter*/
- ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
- ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
- OUT_BCS_BATCH(batch,
- (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
- (beginx << 16) |
- slice_param->macroblock_address );
- OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
- OUT_BCS_BATCH(batch,
- (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
- (1 << 30) | /*ResetRateControlCounter*/
- (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
- (4 << 24) | /*RC Stable Tolerance, middle level*/
- (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
- (0 << 22) | /*QP mode, don't modfiy CBP*/
- (0 << 21) | /*MB Type Direct Conversion Enabled*/
- (0 << 20) | /*MB Type Skip Conversion Enabled*/
- (last_slice << 19) | /*IsLastSlice*/
- (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
- (1 << 17) | /*HeaderPresentFlag*/
- (1 << 16) | /*SliceData PresentFlag*/
- (1 << 15) | /*TailPresentFlag*/
- (1 << 13) | /*RBSP NAL TYPE*/
- (0 << 12) ); /*CabacZeroWordInsertionEnable*/
- OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
- OUT_BCS_BATCH(batch,
- (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
- (maxQpP << 16) | /*Target QP + 20 is highest QP*/
- (shrink << 8) |
- (grow << 0));
- OUT_BCS_BATCH(batch,
- (correct[5] << 20) |
- (correct[4] << 16) |
- (correct[3] << 12) |
- (correct[2] << 8) |
- (correct[1] << 4) |
- (correct[0] << 0));
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-}
-
-
-
-static int
-gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
- int qp,unsigned int *msg,
- struct intel_encoder_context *encoder_context,
- unsigned char target_mb_size, unsigned char max_mb_size,
- struct intel_batchbuffer *batch)
-{
- int len_in_dwords = 12;
- unsigned int intra_msg;
-#define INTRA_MSG_FLAG (1 << 13)
-#define INTRA_MBTYPE_MASK (0x1F0000)
- if (batch == NULL)
- batch = encoder_context->base.batch;
-
- BEGIN_BCS_BATCH(batch, len_in_dwords);
-
- intra_msg = msg[0] & 0xC0FF;
- intra_msg |= INTRA_MSG_FLAG;
- intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8);
- OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch,
- (0 << 24) | /* PackedMvNum, Debug*/
- (0 << 20) | /* No motion vector */
- (1 << 19) | /* CbpDcY */
- (1 << 18) | /* CbpDcU */
- (1 << 17) | /* CbpDcV */
- intra_msg);
-
- OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
- OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
-
- /*Stuff for Intra MB*/
- OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
- OUT_BCS_BATCH(batch, msg[2]);
- OUT_BCS_BATCH(batch, msg[3]&0xFF);
-
- /*MaxSizeInWord and TargetSzieInWord*/
- OUT_BCS_BATCH(batch, (max_mb_size << 24) |
- (target_mb_size << 16) );
-
- OUT_BCS_BATCH(batch, 0);
-
- ADVANCE_BCS_BATCH(batch);
-
- return len_in_dwords;
-}
-
-static int
-gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
- unsigned int *msg, unsigned int offset,
- struct intel_encoder_context *encoder_context,
- unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
- struct intel_batchbuffer *batch)
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- int len_in_dwords = 12;
- unsigned int inter_msg = 0;
- if (batch == NULL)
- batch = encoder_context->base.batch;
- {
-#define MSG_MV_OFFSET 4
- unsigned int *mv_ptr;
- mv_ptr = msg + MSG_MV_OFFSET;
- /* MV of VME output is based on 16 sub-blocks. So it is necessary
- * to convert them to be compatible with the format of AVC_PAK
- * command.
- */
- if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) {
- /* MV[0] and MV[2] are replicated */
- mv_ptr[4] = mv_ptr[0];
- mv_ptr[5] = mv_ptr[1];
- mv_ptr[2] = mv_ptr[8];
- mv_ptr[3] = mv_ptr[9];
- mv_ptr[6] = mv_ptr[8];
- mv_ptr[7] = mv_ptr[9];
- } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) {
- /* MV[0] and MV[1] are replicated */
- mv_ptr[2] = mv_ptr[0];
- mv_ptr[3] = mv_ptr[1];
- mv_ptr[4] = mv_ptr[16];
- mv_ptr[5] = mv_ptr[17];
- mv_ptr[6] = mv_ptr[24];
- mv_ptr[7] = mv_ptr[25];
- } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
- !(msg[1] & SUBMB_SHAPE_MASK)) {
- /* Don't touch MV[0] or MV[1] */
- mv_ptr[2] = mv_ptr[8];
- mv_ptr[3] = mv_ptr[9];
- mv_ptr[4] = mv_ptr[16];
- mv_ptr[5] = mv_ptr[17];
- mv_ptr[6] = mv_ptr[24];
- mv_ptr[7] = mv_ptr[25];
- }
- }
-
- BEGIN_BCS_BATCH(batch, len_in_dwords);
-
- OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
-
- inter_msg = 32;
- /* MV quantity */
- if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) {
- if (msg[1] & SUBMB_SHAPE_MASK)
- inter_msg = 128;
- }
- OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/
- OUT_BCS_BATCH(batch, offset);
- inter_msg = msg[0] & (0x1F00FFFF);
- inter_msg |= INTER_MV8;
- inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17));
- if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
- (msg[1] & SUBMB_SHAPE_MASK)) {
- inter_msg |= INTER_MV32;
- }
-
- OUT_BCS_BATCH(batch, inter_msg);
-
- OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
-#if 0
- if ( slice_type == SLICE_TYPE_B) {
- OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
- } else {
- OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
- }
-#else
- OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
-#endif
-
- inter_msg = msg[1] >> 8;
- /*Stuff for Inter MB*/
- OUT_BCS_BATCH(batch, inter_msg);
- OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
- OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
-
- /*MaxSizeInWord and TargetSzieInWord*/
- OUT_BCS_BATCH(batch, (max_mb_size << 24) |
- (target_mb_size << 16) );
-
- OUT_BCS_BATCH(batch, 0x0);
-
- ADVANCE_BCS_BATCH(batch);
-
- return len_in_dwords;
-}
-
-static void
-gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index,
- struct intel_batchbuffer *slice_batch)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
- unsigned int *msg = NULL, offset = 0;
- unsigned char *msg_ptr = NULL;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
- int i,x,y;
- int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- unsigned int tail_data[] = { 0x0, 0x0 };
- int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int is_intra = slice_type == SLICE_TYPE_I;
- int qp_slice;
- int qp_mb;
-
- qp_slice = qp;
- if (rate_control_mode != VA_RC_CQP) {
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
- if (encode_state->slice_header_index[slice_index] == 0) {
- pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
- qp_slice = qp;
- }
- }
-
- /* only support for 8-bit pixel bit-depth */
- assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
- assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
- assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
- assert(qp >= 0 && qp < 52);
-
- gen75_mfc_avc_slice_state(ctx,
- pPicParameter,
- pSliceParameter,
- encode_state, encoder_context,
- (rate_control_mode != VA_RC_CQP), qp_slice, slice_batch);
-
- if ( slice_index == 0)
- intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
-
- intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
-
- dri_bo_map(vme_context->vme_output.bo , 1);
- msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual;
-
- if (is_intra) {
- msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
- } else {
- msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
- }
-
- for (i = pSliceParameter->macroblock_address;
- i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
- int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
- x = i % width_in_mbs;
- y = i / width_in_mbs;
- msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
-
- if (vme_context->roi_enabled) {
- qp_mb = *(vme_context->qp_per_mb + i);
- } else
- qp_mb = qp;
-
- if (is_intra) {
- assert(msg);
- gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
- } else {
- int inter_rdo, intra_rdo;
- inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK;
- intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK;
- offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET;
- if (intra_rdo < inter_rdo) {
- gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
- } else {
- msg += AVC_INTER_MSG_OFFSET;
- gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb,
- msg, offset, encoder_context,
- 0, 0, slice_type, slice_batch);
- }
- }
- }
-
- dri_bo_unmap(vme_context->vme_output.bo);
-
- if ( last_slice ) {
- mfc_context->insert_object(ctx, encoder_context,
- tail_data, 2, 8,
- 2, 1, 1, 0, slice_batch);
- } else {
- mfc_context->insert_object(ctx, encoder_context,
- tail_data, 1, 8,
- 1, 1, 1, 0, slice_batch);
- }
-}
-
-static dri_bo *
-gen75_mfc_avc_software_batchbuffer(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *batch;
- dri_bo *batch_bo;
- int i;
-
- batch = mfc_context->aux_batchbuffer;
- batch_bo = batch->buffer;
- for (i = 0; i < encode_state->num_slice_params_ext; i++) {
- gen75_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
- }
-
- intel_batchbuffer_align(batch, 8);
-
- BEGIN_BCS_BATCH(batch, 2);
- OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
- ADVANCE_BCS_BATCH(batch);
-
- dri_bo_reference(batch_bo);
-
- intel_batchbuffer_free(batch);
- mfc_context->aux_batchbuffer = NULL;
-
- return batch_bo;
-}
-
-
-static void
-gen75_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-
-{
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- assert(vme_context->vme_output.bo);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &vme_context->vme_output,
- BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
- SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
-}
-
-static void
-gen75_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- assert(mfc_context->aux_batchbuffer_surface.bo);
- mfc_context->buffer_suface_setup(ctx,
- &mfc_context->gpe_context,
- &mfc_context->aux_batchbuffer_surface,
- BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
- SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
-}
-
-static void
-gen75_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- gen75_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
- gen75_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
-}
-
-static void
-gen75_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct gen6_interface_descriptor_data *desc;
- int i;
- dri_bo *bo;
-
- bo = mfc_context->gpe_context.idrt.bo;
- dri_bo_map(bo, 1);
- assert(bo->virtual);
- desc = bo->virtual;
-
- for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
- struct i965_kernel *kernel;
-
- kernel = &mfc_context->gpe_context.kernels[i];
- assert(sizeof(*desc) == 32);
-
- /*Setup the descritor table*/
- memset(desc, 0, sizeof(*desc));
- desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
- desc->desc2.sampler_count = 0;
- desc->desc2.sampler_state_pointer = 0;
- desc->desc3.binding_table_entry_count = 2;
- desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
- desc->desc4.constant_urb_entry_read_offset = 0;
- desc->desc4.constant_urb_entry_read_length = 4;
-
- /*kernel start*/
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
- kernel->bo);
- desc++;
- }
-
- dri_bo_unmap(bo);
-}
-
-static void
-gen75_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
-
- (void)mfc_context;
-}
-
-#define AVC_PAK_LEN_IN_BYTE 48
-#define AVC_PAK_LEN_IN_OWORD 3
-
-static void
-gen75_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
- uint32_t intra_flag,
- int head_offset,
- int number_mb_cmds,
- int slice_end_x,
- int slice_end_y,
- int mb_x,
- int mb_y,
- int width_in_mbs,
- int qp,
- uint32_t fwd_ref,
- uint32_t bwd_ref)
-{
- uint32_t temp_value;
- BEGIN_BATCH(batch, 14);
-
- OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
-
- /*inline data */
- OUT_BATCH(batch, head_offset / 16);
- OUT_BATCH(batch, (intra_flag) | (qp << 16));
- temp_value = (mb_x | (mb_y << 8) | (width_in_mbs << 16));
- OUT_BATCH(batch, temp_value);
-
- OUT_BATCH(batch, number_mb_cmds);
-
- OUT_BATCH(batch,
- ((slice_end_y << 8) | (slice_end_x)));
- OUT_BATCH(batch, fwd_ref);
- OUT_BATCH(batch, bwd_ref);
-
- OUT_BATCH(batch, MI_NOOP);
-
- ADVANCE_BATCH(batch);
-}
-
-static void
-gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
- struct intel_encoder_context *encoder_context,
- VAEncSliceParameterBufferH264 *slice_param,
- int head_offset,
- int qp,
- int last_slice)
-{
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- struct gen6_vme_context *vme_context = encoder_context->vme_context;
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int total_mbs = slice_param->num_macroblocks;
- int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
- int number_mb_cmds = 128;
- int starting_offset = 0;
- int mb_x, mb_y;
- int last_mb, slice_end_x, slice_end_y;
- int remaining_mb = total_mbs;
- uint32_t fwd_ref , bwd_ref, mb_flag;
-
- last_mb = slice_param->macroblock_address + total_mbs - 1;
- slice_end_x = last_mb % width_in_mbs;
- slice_end_y = last_mb / width_in_mbs;
-
- if (slice_type == SLICE_TYPE_I) {
- fwd_ref = 0;
- bwd_ref = 0;
- mb_flag = 1;
- } else {
- fwd_ref = vme_context->ref_index_in_mb[0];
- bwd_ref = vme_context->ref_index_in_mb[1];
- mb_flag = 0;
- }
-
- if (width_in_mbs >= 100) {
- number_mb_cmds = width_in_mbs / 5;
- } else if (width_in_mbs >= 80) {
- number_mb_cmds = width_in_mbs / 4;
- } else if (width_in_mbs >= 60) {
- number_mb_cmds = width_in_mbs / 3;
- } else if (width_in_mbs >= 40) {
- number_mb_cmds = width_in_mbs / 2;
- } else {
- number_mb_cmds = width_in_mbs;
- }
-
- do {
- if (number_mb_cmds >= remaining_mb) {
- number_mb_cmds = remaining_mb;
- }
- mb_x = (slice_param->macroblock_address + starting_offset) % width_in_mbs;
- mb_y = (slice_param->macroblock_address + starting_offset) / width_in_mbs;
-
- gen75_mfc_batchbuffer_emit_object_command(batch,
- mb_flag,
- head_offset,
- number_mb_cmds,
- slice_end_x,
- slice_end_y,
- mb_x,
- mb_y,
- width_in_mbs,
- qp,
- fwd_ref,
- bwd_ref);
-
- head_offset += (number_mb_cmds * AVC_PAK_LEN_IN_BYTE);
- remaining_mb -= number_mb_cmds;
- starting_offset += number_mb_cmds;
- } while (remaining_mb > 0);
-}
-
-/*
- * return size in Owords (16bytes)
- */
-static void
-gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context,
- int slice_index)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
- VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
- VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
- VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
- int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
- int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
- int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
- unsigned int rate_control_mode = encoder_context->rate_control_mode;
- unsigned int tail_data[] = { 0x0, 0x0 };
- long head_offset;
- int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
- int qp_slice;
-
- qp_slice = qp;
- if (rate_control_mode != VA_RC_CQP) {
- qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
- if (encode_state->slice_header_index[slice_index] == 0) {
- pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
- qp_slice = qp;
- }
- }
-
- /* only support for 8-bit pixel bit-depth */
- assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
- assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
- assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
- assert(qp >= 0 && qp < 52);
-
- gen75_mfc_avc_slice_state(ctx,
- pPicParameter,
- pSliceParameter,
- encode_state,
- encoder_context,
- (rate_control_mode != VA_RC_CQP),
- qp_slice,
- slice_batch);
-
- if (slice_index == 0)
- intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
-
- intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
-
- intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- head_offset = intel_batchbuffer_used_size(slice_batch);
-
- slice_batch->ptr += pSliceParameter->num_macroblocks * AVC_PAK_LEN_IN_BYTE;
-
- gen75_mfc_avc_batchbuffer_slice_command(ctx,
- encoder_context,
- pSliceParameter,
- head_offset,
- qp,
- last_slice);
-
-
- /* Aligned for tail */
- intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
- if (last_slice) {
- mfc_context->insert_object(ctx,
- encoder_context,
- tail_data,
- 2,
- 8,
- 2,
- 1,
- 1,
- 0,
- slice_batch);
- } else {
- mfc_context->insert_object(ctx,
- encoder_context,
- tail_data,
- 1,
- 8,
- 1,
- 1,
- 1,
- 0,
- slice_batch);
- }
-
- return;
-}
-
-static void
-gen75_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
- struct encode_state *encode_state,
- struct intel_encoder_context *encoder_context)
-{
- struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- struct intel_batchbuffer *batch = encoder_context->base.batch;
- int i;
- intel_batchbuffer_start_atomic(batch, 0x4000);
- gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
-
- for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
- gen75_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i);
- }
- {
- struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
- intel_batchbuffer_align(slice_batch, 8);
- BEGIN_BCS_BATCH(slice_b