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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
AgeCommit message (Expand)AuthorFilesLines
2021-12-03classic/i965: Remove driverDylan Baker1-728/+0
2021-11-08intel: move away from booleans to identify platformsLionel Landwerlin1-5/+5
2021-10-28i965: Port STATE_BASE_ADDRESS to genxml and fix bugsKenneth Graunke1-196/+0
2021-10-28i965: Set default MOCS for NULL depth/stencil/HiZ buffersKenneth Graunke1-0/+1
2021-10-28i965: Use ISL for MOCS rather than open coding it everywhereKenneth Graunke1-11/+10
2021-09-13intel: Move subslice_total into devinfoJordan Justen1-2/+1
2021-08-17intel/isl: Use uint64_t for computed byte offsetsJason Ekstrand1-2/+2
2021-05-17intel: simplify is_haswell checks, part 1Marcin Ślusarz1-1/+1
2021-04-20intel: Rename gen_device prefix to intel_deviceAnuj Phogat1-9/+9
2021-04-02intel: Rename GENx keyword to GFXxAnuj Phogat1-1/+1
2021-04-02intel: Rename Genx keyword to GfxxAnuj Phogat1-5/+5
2021-04-02intel: Rename genx keyword to gfxx in source filesAnuj Phogat1-2/+2
2021-04-02intel: Rename GENx prefix in macros to GFXx in source filesAnuj Phogat1-9/+9
2021-04-02intel: Rename gen field in gen_device_info struct to verAnuj Phogat1-29/+29
2021-03-11i965: Rename files with "intel_" prefix to "brw_"Anuj Phogat1-3/+3
2021-02-25i965: Eliminate all tabs except in brw_defines.hKenneth Graunke1-17/+17
2021-02-25i965: Rename the rest of intel_* functions to brw_*Kenneth Graunke1-8/+8
2021-02-25i965: Rename intel_mip* to brw_mip*.Kenneth Graunke1-10/+10
2021-02-25i965: Rename intel_renderbuffer to brw_renderbufferKenneth Graunke1-15/+15
2021-02-25i965: Rename intel_batchbuffer_* to brw_batch_*.Kenneth Graunke1-2/+2
2020-12-30intel/isl: move get_tile dims/masks to common isl headerDave Airlie1-2/+2
2019-08-12i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez1-0/+90
2019-08-08i965: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3DDanylo Piliaiev1-0/+21
2019-04-14intel: Emit 3DSTATE_VF_STATISTICS dynamicallyKenneth Graunke1-6/+0
2018-10-11i965/gen10+: Initialize new fields in STATE_BASE_ADDRESSJordan Justen1-1/+6
2018-09-26intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand1-1/+1
2018-07-19i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery1-1/+3
2018-05-22i965: Remove ring switching entirelyJason Ekstrand1-1/+1
2018-05-08i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hizJason Ekstrand1-81/+26
2018-05-08i965: Move brw_emit_depth_stencil_hiz higher up in the fileJason Ekstrand1-50/+40
2018-05-08i965: Use ISL for emitting depth/stencil/hiz state on gen6+Jason Ekstrand1-18/+129
2018-05-08i965: Use the brw_depthbuffer atom on all gensJason Ekstrand1-1/+2
2018-03-27i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke1-3/+1
2018-03-01i965: Allow 48-bit addressing on Gen8+.Kenneth Graunke1-4/+9
2018-02-28Revert "i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+"Mark Janes1-9/+0
2018-02-28i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+Jason Ekstrand1-0/+9
2018-01-09intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke1-0/+15
2017-11-29i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.Kenneth Graunke1-12/+12
2017-11-29i965: Program the dynamic state heap size to MAX_STATE_SIZE.Kenneth Graunke1-1/+1
2017-11-16i965: Upload invariant state once at the start of the batch on Gen4-5.Kenneth Graunke1-9/+0
2017-11-13i965: Add more precise cache tracking helpersJason Ekstrand1-2/+2
2017-09-14i965: Use a separate state buffer, but avoid changing flushing behavior.Kenneth Graunke1-13/+13
2017-08-30i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin1-1/+2
2017-08-30i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin1-1/+1
2017-08-30i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin1-4/+4
2017-08-30i965: drop brw->gen in favor of devinfo->genLionel Landwerlin1-27/+36
2017-08-04i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson1-33/+18
2017-07-20i965: Drop redundant check for non-tiled depth bufferTopi Pohjolainen1-2/+1
2017-07-20i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen1-1/+1
2017-07-20i965/miptree: Switch to isl_surf::tilingTopi Pohjolainen1-4/+4
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