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21 hoursintel/fs: decouple alphaToCoverage from per sample dispatchLionel Landwerlin1-2/+0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27803>
21 hoursintel/brw: fixup wm_prog_data_barycentric_modes()Lionel Landwerlin1-4/+12
Always select sample barycentric when persample dispatch is unknown at compile time and let the payload adjustments feed the expected value based on dispatch. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27803>
39 hoursintel/brw: Replace type_sz and brw_reg_type_to_size with brw_type_size_*Kenneth Graunke1-14/+14
Both of these helpers do the same thing. We now have brw_type_size_bits and brw_type_size_bytes and can use whichever makes sense in that place. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
39 hoursintel/brw: Use newer brw_type_is_* shorter namesKenneth Graunke1-2/+2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
39 hoursintel/brw: Reindent after shortening BRW_REGISTER_TYPE_* to BRW_TYPE_*Kenneth Graunke1-2/+1
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
39 hoursintel/brw: Stop using long BRW_REGISTER_TYPE enum namesKenneth Graunke1-54/+54
s/BRW_REGISTER_TYPE/BRW_TYPE/g Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
3 daysintel/brw: Lower VGRFs to FIXED_GRFs earlierCaio Oliveira1-0/+12
Moves the lowering of VGRFs into FIXED_GRFs from the code generation to (almost) right after the register allocation. This will allow: (1) later passes not worry about VGRFs (and what they mean in a post reg alloc phase) and (2) make easier to add certain types of validation post reg alloc phase using the backend IR. Note that a couple of passes still take advantage of seeing "allocated VGRFs", so perform lowering after they run. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28604>
11 daysintel/brw: Replace FS_OPCODE_LINTERP with BRW_OPCODE_PLNKenneth Graunke1-11/+4
We no longer support the old LINE+MAC lowering, and we already lower this to MAD in NIR on Gfx11+, so the LINTERP virtual opcode always corresponds the PLN. The only catch is that LINTERP's operands are reversed from PLN, so we have to switch them. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28705>
11 daysintel/brw: Use SHADER_OPCODE_SEND for coherent framebuffer readsKenneth Graunke1-6/+0
We already have a logical opcode and lower to what is basically a send instruction. We just weren't using SHADER_OPCODE_SEND, instead having extra redundant infrastructure for no real gain. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28705>
11 daysintel/brw: Delete fs_visitor::vgrf helperKenneth Graunke1-64/+5
Just use fs_builder::vgrf instead of the older glsl_type-based one. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28705>
2024-04-05intel/fs: printout a couple of more late compile stepsLionel Landwerlin1-1/+14
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28188>
2024-04-01intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*().Francisco Jerez1-4/+1
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
2024-04-01intel/brw/xehp+: Replace lsc_msg_desc_dest_len()/lsc_msg_desc_src0_len() ↵Francisco Jerez1-2/+2
with helpers to do the computation. We cannot rely on the immediate message descriptor having accurate values for mlen and rlen at the IR level, since they are updated at codegen time via 'inst->mlen' and 'inst->size_written', which could end up with values inconsistent with the message descriptor if e.g. the split sends optimization had an effect. Instead, define helpers that do the computation without relying on the message descriptor, and use the pre-existing brw_message_desc_mlen()/brw_message_desc_rlen() helpers (fully equivalent to the lsc helpers deleted here) during disassembly. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
2024-04-01intel/brw/xe2: Update uniform handling to account for 512b physical registersIan Romanick1-2/+17
Rework: * Jordan: Drop FINISHME (s-b Caio) * Jordan: Use reg_unit() in asserts rather than a ver check (s-b Caio) * Ian: Make use of reg_unit() in round_components_to_whole_registers() Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28484>
2024-03-29intel/brw: Add a src array for the common case in fs_instCaio Oliveira1-15/+58
In the common case, fs_inst will have up to 4 sources (the HW instructions have up to 3, and our representation of SENDs have 4). Embed such array into the fs_inst, and use it whenever applicable instead of allocating a new array. Also change the code to reuse the allocated src array when resizing to a smaller length. Between the changes above and the reduced amount of initializing fs_regs, this reduces fossil-db time by around 2% for Borderlands 3 and Rise of the Tomb Raider, and around 1.5% for Total War Warhammer 3. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28379>
2024-03-27intel/brw: Allow changing types for LOAD_PAYLOAD with 1 sourceKenneth Graunke1-0/+1
This is equivalent to a MOV. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28067>
2024-03-26Revert "intel/brw: Don't consider UNIFORM_PULL_CONSTANT_LOAD a send-from-GRF"Kenneth Graunke1-0/+2
This reverts commit 5814534de57444475cc3e20c88c4110e7629d9de. It apparently caused GPU hangs in Assassin's Creed: Valhalla, and it isn't that critical of a patch, so let's just roll it back for now. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10894 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28390>
2024-03-21intel/brw: Fix handling of accumulator register numbersIan Romanick1-4/+12
Folks, there's more than one accumulator. In general, when the register file is ARF, the upper 4 bits of the register number specify which ARF, and the lower 4 bits specify which one of that ARF. This can be further partitioned by the subregister number. This is already mostly handled correctly for flags register, but lots of places wanted to check the register number for equality with BRW_ARF_ACCUMULATOR. If acc1 is ever specified, that won't work. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-20intel/blorp/xe2+: Don't use replicated-data clears.Francisco Jerez1-0/+1
They've been removed from the hardware. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20intel/brw/xe2+: Update encoding of FB write descriptor message control.Francisco Jerez1-1/+3
Ref: bspec: 65209, 63908 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20intel/brw: Don't consider UNIFORM_PULL_CONSTANT_LOAD a send-from-GRFKenneth Graunke1-2/+0
It's a logical opcode which is lowered to a send-from-GRF later. That lowering code is responsible for ensuring the sources are set up in a proper SEND payload. This was preventing copy propagation of surface handles which started out as scalars, were splatted out to full-SIMD values with NoMask, then actually consumed as only component 0 (scalar again), because we thought that scalar values were not allowed. fossil-db on Alchemist shows improvements in q2rtx but no other titles: Totals: Instrs: 161310436 -> 161310152 (-0.00%) Cycles: 14370605159 -> 14370601066 (-0.00%) Totals from 17 (0.00% of 652298) affected shaders: Instrs: 16097 -> 15813 (-1.76%) Cycles: 185508 -> 181415 (-2.21%) Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28286>
2024-03-15intel/compiler/fs: Restore SIMD32 restriction for ray_queries on Xe2Jordan Justen1-3/+3
In 96e0d979a7b, the restriction was dropped because we don't compile a SIMD8 program on Xe2. This change moves it to run_fs() so the restriction will be added when compiling SIMD16 on Xe2. Fixes: 96e0d979a7b ("intel/fs: Check fs_visitor instance before using it") Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28191>
2024-03-12intel/brw: Avoid a silly add with zero in assign_curb_setupIan Romanick1-2/+11
No shader-db changes. fossil-db: DG2 Totals: Instrs: 161008251 -> 161004452 (-0.00%) Cycles: 13894249509 -> 13893050101 (-0.01%); split: -0.01%, +0.00% Totals from 3804 (0.58% of 652145) affected shaders: Instrs: 2232984 -> 2229185 (-0.17%) Cycles: 7124966553 -> 7123767145 (-0.02%); split: -0.02%, +0.00% No fossil-db changes on any other platform. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
2024-03-12intel/brw: Correctly dump subnr for FIXED_GRF in INTEL_DEBUG=optimizerIan Romanick1-1/+7
v2: Also update printing FIXED_GRF as destionation. Suggested by Lionel. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
2024-03-05intel/brw: Replace CS_OPCODE_CS_TERMINATE with SHADER_OPCODE_SENDKenneth Graunke1-3/+0
There's no need for special handling here, it's just a send message with a trivial g0 header and descriptor. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27924>
2024-03-01intel/brw: Mark FIND[_LAST]_LIVE_CHANNEL as not writing the flagKenneth Graunke1-3/+1
brw_lower_find_live_channel doesn't actually write a flag register, but elk_find_live_channel notes that the flag was used on Gfx7. This allows more CSE on FIND[_LAST]_LIVE_CHANNEL. shader-db and fossil-db on Alchemist show minor reductions in cycles and instruction count, a few minor increases, but it doesn't seem to be a large effect in either direction. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27862>
2024-03-01intel/brw: Delete legacy texture opcodesKenneth Graunke1-99/+0
We first generate the logical opcodes, and these days fully lower to SHADER_OPCODE_SEND. In the past, we lowered to a non-logical variant and handled that in the generator. These days, we were just using the non-logical opcodes as an awkward intermediate opcode change during the lowering...which isn't really necessary at all. This patch eliminates them by using the original logical opcodes. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
2024-03-01intel/brw: Delete SHADER_OPCODE_TXF_UMSKenneth Graunke1-8/+0
Nothing seems to generate this anymore. I guess we always use CMS. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
2024-03-01intel/brw: Delete SHADER_OPCODE_TXF_CMS[_LOGICAL]Kenneth Graunke1-9/+0
We always use the wide variant (_W) on hardware this compiler supports. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
2024-03-01intel/brw: Fold backend_reg into fs_regCaio Oliveira1-5/+7
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27904>
2024-02-29intel/brw: Move functions from backend_instruction into fs_instCaio Oliveira1-5/+63
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27866>
2024-02-29intel/brw: Use fs_inst explicitly in various passesCaio Oliveira1-1/+1
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27866>
2024-02-29intel/brw: Remove brw_shader.hCaio Oliveira1-0/+354
Find a better home for its existing content. Some functions are now just static functions at the usage sites. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Remove extra stage_prog_data field in fs_visitorCaio Oliveira1-9/+9
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Fold backend_shader into fs_visitorCaio Oliveira1-2/+1
The base class was used when we had vec4, but now we can fold it with its only subclass. Declare fs_visitor now as a struct to be able to forward declare for C code without causing errors due to class/struct being mixed. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Move dump_* functions into fs_visitorCaio Oliveira1-4/+19
Make them non-virtual and update the parameter to use fs_inst. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Fold fs_instruction_scheduler into instruction_schedulerCaio Oliveira1-1/+1
And use fs_inst instead of backend_instruction. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Use fs_visitor instead of backend_shader in various passesCaio Oliveira1-1/+1
And since we are touching them, rename a couple of passes to follow same name convention as existing ones. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
2024-02-29intel/brw: Delete unnecessary brw_wm_prog_data fieldsKenneth Graunke1-17/+0
Register blocks and interp_mode[] were for Gfx4-5. The binding table section doesn't seem to be used anymore, nor does color_outputs_written. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-28intel/brw: Remove runtime_check_aads_emitCaio Oliveira1-6/+4
It was used for Gfx4 payload. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- fields from *_prog_key structsCaio Oliveira1-8/+1
Those are not used or relevant anymore. Also update Iris accordingly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove MRF typeCaio Oliveira1-64/+0
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- remaining opcodesCaio Oliveira1-35/+5
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- code from visitorCaio Oliveira1-125/+37
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- code from fs_instCaio Oliveira1-10/+3
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- code from backend passesCaio Oliveira1-4/+4
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove Gfx8- code from brw_compile_* functionsCaio Oliveira1-46/+3
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove now unused vec4-only opcodesCaio Oliveira1-3/+0
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-28intel/brw: Remove vec4 backendCaio Oliveira1-1/+0
It still exists as part of ELK for older gfx versions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
2024-02-27intel/compiler: Add texture gather offset LOD/Bias message supportSagar Ghuge1-0/+12
v2: (Ian) - Space formatting on conditional statement Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 02:12:41 +0000