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33 min.intel/ds: track end of pipe bitsHEADmainLionel Landwerlin5-3/+10
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.anv: rename a few internal functions to highlight gfx useLionel Landwerlin1-5/+5
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.anv: rename RT pipeline function helperLionel Landwerlin1-6/+7
Making it clear this is intended for RT pipelines only. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs: make alpha_to_coverage a tristateLionel Landwerlin8-11/+52
That way in some cases we can do this dynamically. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs: Rework dynamic coarse handlingJason Ekstrand4-15/+19
Use 2 flags for PI & RT messages. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs: Break out yet another FB write helperJason Ekstrand2-37/+44
This new helper, do_emit_fb_writes() does the actual walk over all the render targets to emit each of the different FB writes. We want this in a helper because we're about to go a bit crazy with coarse. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs/validate: Assert SEND [extended] descriptors are uniformJason Ekstrand2-1/+12
This is required by code-gen since it generates a 1-wide OR and it'll blow up if the register width > 1. It's also way better than the "your register is the wrong size" assert you get from the more generic validation check. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-stateJason Ekstrand10-13/+31
This allows us to communicate to the back-end that we don't actually know if the framebuffer is multisampled or not. No drivers set anything but ALWAYS/NEVER and we still have a few ALWAYS/NEVER assumptions but those should be asserted. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/compiler: Convert wm_prog_key::persample_interp to a tri-stateJason Ekstrand11-51/+175
This allows for the possibility that we may not know at compile time if sample shading is enabled through the API. While we're here, also document exactly what this bit means so we don't confuse ourselves. v2: Fixup coarse pixel values (Lionel) Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs: Make per-sample and coarse dispatch tri-stateJason Ekstrand12-80/+349
Whenever one of them is BRW_SOMETIMES, we depend on dynamic flag pushed in as a push constant. In this case, we have to often have to do the calculation both ways and SEL the result. It's a bit more code but decouples MSAA from the shader key. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/compiler: Convert brw_wm_aa_enable to brw_sometimesJason Ekstrand3-14/+14
There are other cases where we want a tri-state logic like this. May as well have one enum for all the cases. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/fs: Return early in a couple builtin setup helpersJason Ekstrand1-47/+45
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/compiler: Use SHADER_OPCODE_SEND for PI messagesJason Ekstrand7-83/+79
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.nir: Remove nir_lower_io_force_sample_interpolationJason Ekstrand2-11/+2
It's no longer used. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/nir: Lower barycentrics to per-sample in a dedicated passJason Ekstrand1-6/+31
This is more similar to what we do for single-sample and it should be more clear going forward once our lowering gets more complex. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
33 min.intel/compiler: Document wm_prog_key::persample_interpJason Ekstrand1-0/+10
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
5 hoursamd: don't hardcode real VGPR allocation granularity on gfx10.3 and gfx11Marek Olšák2-9/+7
That's how it really works. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursamd,util: fix how lod bias is converted to fixed-pointMarek Olšák3-8/+10
according to internal docs Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursamd/surface: clean up is_dcc_supported_by_L2Marek Olšák1-16/+12
no functional change, though this removes "<=" for navi10, which was never true in the "<" case Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursradeonsi: clean up si_set_mutable_tex_desc_fieldsMarek Olšák1-17/+19
- sink code into existing branches - remove unnecessary clearing of fields - no functional change Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursamd: define new SET_*_REG_PAIRS packetsMarek Olšák3-0/+32
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursradeonsi/gfx11: don't add alpha to mrt0 format for A2C if exporting via mrtzMarek Olšák2-7/+11
If alpha-to-coverage is exported via mrtz, don't upgrade the mrt0 format to one with an alpha channel. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
5 hoursradeonsi/gfx11: don't add mrt0 export for alpha-to-coverage if mrtz is presentMarek Olšák1-1/+4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
7 hoursnir/lower_clip: Only emit 1 discardAlyssa Rosenzweig1-5/+10
If we have multiple clip planes, rather than emit multiple discards we can just OR together the discard criteria. Then a nir_opt_algebraic rule kicks in to optimize out the flt/.../flt/ior/.../ior into fmin/.../fmin/flt, generating much less code at the end. Written while debugging an unrelated issue with the clip lowering. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21103>
20 hourszink: conditionally enable PIPE_CAP_NULL_TEXTURESMike Blumenkrantz1-0/+2
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
20 hoursradeonsi: set PIPE_CAP_NULL_TEXTURESMike Blumenkrantz1-0/+1
fixes #8163 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
20 hoursgallium: add PIPE_CAP_NULL_TEXTURESMike Blumenkrantz8-11/+25
this allows drivers to indicate that they support sampling from null textures instead of using fallback textures for now, this is only used for depth-based fallback textures Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
21 hoursradv: Scalarize global IO with LLVM enabledKonstantin Seurer1-0/+3
Fixes the "atomic store operand must have integer, pointer, or floating point type!" error with RADV_DEBUG=llvm,checkir. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20840>
21 hoursac/llvm: Fix validation error with global ioKonstantin Seurer1-1/+1
Fixes: afd645f0576 ("ac/llvm: remove LLVMBuildGEP usages") Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
21 hoursradv/llvm: Use the shader names as module nameKonstantin Seurer1-0/+24
This makes it easier to identify which (if any) shaders fail validation. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
22 hoursradv/rq: Use 16 stack entries if there is only one ray queryKonstantin Seurer1-4/+7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21120>
24 hoursmeson: Fix Asahi build on macOSAsahi Lina1-1/+1
!19950 introduced a dependency between NIR and Vulkan headers, and the Vulkan headers try to include X11 headers we cannot find on macOS. Disable this (we have no plans for Vulkan on the macOS testing platform anyway). Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21059>
25 hoursagx: Don't scalarize preambles in NIRAlyssa Rosenzweig2-64/+21
Scalarizing preambles in NIR isn't really necessary, we can do it more efficiently in the backend. This makes the final NIR a lot less annoying to read; the backend IR was already nice to read thanks to all the scalarized moves being copypropped. Plus, this is a lot simpler. No shader-db changes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
25 hoursagx: Lower uniform sources with a dedicated passAlyssa Rosenzweig5-18/+67
Move the decision of "can I copyprop this uniform?" from copyprop to a standalone lowering pass. This is more straightforward and will enable the next patch. This has the side effect of sinking load_preamble instructions, for a nice reduction in register pressure. Instruction count increase is from rematerializing some moves, which should be more than balanced out by the reduced register pressure. total instructions in shared programs: 1523285 -> 1523317 (<.01%) instructions in affected programs: 1148 -> 1180 (2.79%) helped: 0 HURT: 13 HURT stats (abs) min: 1.0 max: 4.0 x̄: 2.46 x̃: 2 HURT stats (rel) min: 0.69% max: 7.69% x̄: 3.65% x̃: 2.61% 95% mean confidence interval for instructions value: 1.78 3.14 95% mean confidence interval for instructions %-change: 2.16% 5.15% Instructions are HURT. total bytes in shared programs: 10444532 -> 10444724 (<.01%) bytes in affected programs: 7386 -> 7578 (2.60%) helped: 0 HURT: 13 HURT stats (abs) min: 6.0 max: 24.0 x̄: 14.77 x̃: 12 HURT stats (rel) min: 0.63% max: 7.14% x̄: 3.40% x̃: 2.48% 95% mean confidence interval for bytes value: 10.68 18.85 95% mean confidence interval for bytes %-change: 2.02% 4.78% Bytes are HURT. total halfregs in shared programs: 419444 -> 416434 (-0.72%) halfregs in affected programs: 27080 -> 24070 (-11.12%) helped: 634 HURT: 0 helped stats (abs) min: 1.0 max: 30.0 x̄: 4.75 x̃: 2 helped stats (rel) min: 2.90% max: 54.55% x̄: 13.13% x̃: 8.51% 95% mean confidence interval for halfregs value: -5.08 -4.41 95% mean confidence interval for halfregs %-change: -14.03% -12.23% Halfregs are helped. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
25 hoursagx: Run DCE twiceAlyssa Rosenzweig1-0/+4
Needed to combine fsat with vectors due to nir_lower_blend changes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
25 hoursagx: Allow uniform sources on phisAlyssa Rosenzweig3-5/+4
The parallel copy lowering has been able to handle uniform sources since 98f0ebf2647 ("agx: Pass agx_index to agx_copy"), and uniform sources work fine with phis. It's not super common but there's no need to restrict them. This is a small instruction count win and will greatly simplify the lowering later in this series. total instructions in shared programs: 1523806 -> 1523285 (-0.03%) instructions in affected programs: 17088 -> 16567 (-3.05%) helped: 38 HURT: 1 helped stats (abs) min: 1.0 max: 44.0 x̄: 13.95 x̃: 7 helped stats (rel) min: 0.42% max: 18.64% x̄: 4.73% x̃: 1.26% HURT stats (abs) min: 9.0 max: 9.0 x̄: 9.00 x̃: 9 HURT stats (rel) min: 8.57% max: 8.57% x̄: 8.57% x̃: 8.57% 95% mean confidence interval for instructions value: -17.95 -8.77 95% mean confidence interval for instructions %-change: -6.35% -2.43% Instructions are helped. total bytes in shared programs: 10447658 -> 10444532 (-0.03%) bytes in affected programs: 118850 -> 115724 (-2.63%) helped: 38 HURT: 1 helped stats (abs) min: 6.0 max: 264.0 x̄: 83.68 x̃: 45 helped stats (rel) min: 0.36% max: 16.51% x̄: 4.14% x̃: 1.09% HURT stats (abs) min: 54.0 max: 54.0 x̄: 54.00 x̃: 54 HURT stats (rel) min: 7.30% max: 7.30% x̄: 7.30% x̃: 7.30% 95% mean confidence interval for bytes value: -107.68 -52.62 95% mean confidence interval for bytes %-change: -5.55% -2.13% Bytes are helped. total halfregs in shared programs: 419446 -> 419444 (<.01%) halfregs in affected programs: 29 -> 27 (-6.90%) helped: 1 HURT: 0 Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
35 hoursxlib: fix glXDestroyContext in Gallium frontendsLuc Ma1-2/+8
when glx is built with -Dglx=xlib, the mishandle in glXDestroyContext causes glmark2 to exit unexpectedly. Error: Glmark2 needs OpenGL(ES) version >= 2.0 to run (but version string is: '(null)')! Error: Failed to add vertex shader from file None: Error: Failed to create the new program [build] <default>: Set up failed Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3985 Signed-off-by: Luc Ma <luc@sietium.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21067>
40 hourszink: fix cap check for arb sparse texture2SoroushIMG1-1/+3
arb_sparse_texture2 also enables multisampled sparse textures. bring back the check for msaa support. fixes #8229 Fixes: 4f8ba2b9aae ("zink: fix sparse residency query and minLOD feature checks") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21121>
40 hoursnir/print: Pretty-print color0/1_interpAlyssa Rosenzweig1-2/+8
These are an enum. Furthermore, their 0 state is INTERP_MODE_NONE which we shouldn't bother printing at all. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
40 hoursnir/print: Pretty-print I/O semantic locationsAlyssa Rosenzweig1-1/+27
Instead of printing the raw location number, which is pretty hard to interpret, let's print the name of the location. Example output: vec4 16 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=0, component=0, dest_type=float16 /*144*/, io location=VARYING_SLOT_VAR0 slots=1 mediump /*8388768*/) One of the "regressions" from moving to purely lowered I/O with all variables removed is a lack of debuggability, since otherwise these location strings don't show up anywhere in the printed shader! By contrast this should make the lowered I/O nice to read like the early I/O. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
40 hoursnir/print: Extract get_location_strAlyssa Rosenzweig1-44/+46
Locations show up in two places: variables and lowered I/O semantics. We want to reuse the logic in both places, so extract it out. The extracted logic is IMO easier to read, too. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
41 hoursagx: Implement barriersAlyssa Rosenzweig2-0/+16
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursagx: Implement compute ID intrinsicsAlyssa Rosenzweig1-0/+29
These NIR intrinsics map to vectors of special registers. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Identify more compute-related XMLAlyssa Rosenzweig2-4/+14
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Implement load_ssbo_address/get_ssbo_sizeAlyssa Rosenzweig3-0/+30
More uniforms that get pushed. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Add compute batchesAlyssa Rosenzweig2-1/+20
Add a specialized agx_batch for compute commands (queued to the CDM instead of the VDM for graphics). This uses a sentinel value for the width. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Bump PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERSAlyssa Rosenzweig1-1/+1
Seems arbitrary. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Stub out MSAA for dEQPAlyssa Rosenzweig1-1/+3
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Advertise seamless cube mapsAlyssa Rosenzweig1-2/+2
These are already wired up. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
41 hoursasahi: Fake more caps for dEQP-GLES31Alyssa Rosenzweig1-1/+16
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>