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10 hoursetnaviv: allow mapped buffers during executionHEADmainLucas Stach1-1/+0
Etnaviv has no restrictions on buffers being mapped during execution. In fact most buffers are already always mapped during their lifetime as the unmap is a no-op. Let the frontend know that it doesn't need to bother with unmapping buffers. Signed-off-by: Lucas Stach <> Reviewed-by: Christian Gmeiner <> Part-of: <>
10 hoursetnaviv: expose real map buffer alignmentLucas Stach1-1/+1
As we do not suballocate any buffers, the real map buffer alignment is determined by the GEM BO map alignment, which is at least 4KB. Signed-off-by: Lucas Stach <> Reviewed-by: Christian Gmeiner <> Part-of: <>
19 hoursradv/ci: add CI lists for LLVM on NAVI21Samuel Pitoiset3-1/+831
Copied and adjusted from the ACO lists. v2: Martin Roukala - add an extra test in the list of timeouts - add an extra test in the list of flakes - remove a fail Signed-off-by: Samuel Pitoiset <> Reviewed-by: Martin Roukala <> Acked-by: Timur Kristóf <> Part-of: <>
19 hoursradv/ci: test the llvm backend on navi21Martin Roukala (né Peres)1-0/+8
The LLVM backend is not officially supported by the RADV developers, but it has been useful early during bring-up, or later when users are experiencing what looks like a compiler bug. It is thus beneficial to keep it working. However, maintaining the vkcts expectations for every platform requires more work and machine time than what we would like to commit to. This is why we agreed that we would only keep LLVM tested on the latest family of Radeon GPUs. Signed-off-by: Martin Roukala (né Peres) <> Reviewed-by: Samuel Pitoiset <> Acked-by: Timur Kristóf <> Part-of: <>
32 hoursgallium/util: Move u_dl and u_pointer to src/utilJesse Natalie5-19/+18
Reviewed-by: Eric Engestrom <> Reviewed-by: Mike Blumenkrantz <> Part-of: <>
33 hoursetnaviv: async shader compileChristian Gmeiner4-6/+70
Passes following piglit: - spec@khr_parallel_shader_compile@basic Signed-off-by: Christian Gmeiner <> Reviewed-by: Philipp Zabel <> Part-of: <>
33 hoursetnaviv: factor out shader screen related init/deintChristian Gmeiner3-4/+28
This is a prep step for the next changes. Signed-off-by: Christian Gmeiner <> Reviewed-by: Philipp Zabel <> Part-of: <>
34 hoursci/x86: update to llvm 13Martin Roukala (né Peres)5-0/+20
Most CI tests are currently running on LLVM 11 (released over 2 years ago), which predates some of the GPUs we have in CI and prevents testing RADV's LLVM backend. LLVM 13 is known to work for RADV, released almost 8 months ago, and is already available in most distributions. Fedora 36 is even already on LLVM 14. So this commit updates x86 testing on llvm 13. v2: - store the llvm apt repo key locally (Michel Dänzer) Signed-off-by: Martin Roukala (né Peres) <> Acked-by: Timur Kristóf <> Acked-by: Daniel Stone <> Part-of: <>
34 hoursradv: Use NIR optimization to move discards to the top.Timur Kristóf1-1/+7
Fossil stats on Sienna Cichlid: Totals from 1988 (1.55% of 128653) affected shaders: VGPRs: 68096 -> 67928 (-0.25%); split: -0.61%, +0.36% CodeSize: 5391936 -> 5391312 (-0.01%); split: -0.11%, +0.10% MaxWaves: 53020 -> 52946 (-0.14%); split: +0.05%, -0.19% Instrs: 992413 -> 992509 (+0.01%); split: -0.10%, +0.11% Latency: 8643141 -> 8789295 (+1.69%); split: -0.31%, +2.00% InvThroughput: 1680195 -> 1680605 (+0.02%); split: -0.04%, +0.07% SClause: 50886 -> 51318 (+0.85%); split: -0.73%, +1.57% Copies: 57017 -> 56741 (-0.48%); split: -1.28%, +0.80% PreSGPRs: 66766 -> 67048 (+0.42%); split: -0.24%, +0.66% PreVGPRs: 56832 -> 56935 (+0.18%); split: -0.44%, +0.62% Signed-off-by: Timur Kristóf <> Reviewed-by: Daniel Schürmann <> Part-of: <>
34 hoursvenus: swizzle the chroma channels for YVU420 to match the VkFormatYiwei Zhang1-0/+14
Test: - testVP8EncodeDecodeVideoFromBufferToSurface - Signed-off-by: Yiwei Zhang <> Reviewed-by: Ryan Neph <> Part-of: <>
35 hoursradv: Add CULL_PRIMITIVE to special output mask.Timur Kristóf1-1/+3
It isn't compiled to an output param, so can be safely ignored from the param assignment. Signed-off-by: Timur Kristóf <> Reviewed-by: Rhys Perry <> Part-of: <>
35 hoursradv: Don't assign driver locations to mesh shader outputs.Timur Kristóf1-28/+4
Set all driver locations to zero. These are ignored by ac_nir_lower_ngg anyway. Signed-off-by: Timur Kristóf <> Reviewed-by: Rhys Perry <> Part-of: <>
35 hoursac/nir/ngg: Ignore driver location for mesh shader outputs.Timur Kristóf1-10/+4
Signed-off-by: Timur Kristóf <> Reviewed-by: Rhys Perry <> Part-of: <>
36 hoursci/radv: enable vkcts testing on kabiniMartin Roukala (né Peres)4-5/+43
It seems like the hangs have been resolved on kabini, so let's allow developers to run their tests on kabini, if they are *very* patient (~10h). Signed-off-by: Martin Roukala (né Peres) <> Acked-by: Samuel Pitoiset <> Part-of: <>
37 hoursci/freedreno: disable SpecOps trace, each run flakyDavid Heidelberg1-4/+5
Signed-off-by: David Heidelberg <> Part-of: <>
38 hoursfreedreno/registers: add a7xx registers for drm/msm kernel driverJonathan Marek4-0/+380
Most of this is taken directly from the downstream kernel driver. Signed-off-by: Jonathan Marek <> Part-of: <>
38 hoursdzn: Support Vulkan loader interface v5Jesse Natalie1-1/+7
Reviewed-by: Boris Brezillon <> Part-of: <>
39 hoursradv: Use two bools for ahit_statusKonstantin Seurer1-27/+22
This avoids using a VGPR and uses two SGPRs instead since we only need to store 2 bits. Quake II RTX: Totals from 7 (0.46% of 1513) affected shaders: CodeSize: 229364 -> 229148 (-0.09%); split: -0.12%, +0.02% Instrs: 41937 -> 41879 (-0.14%) Latency: 977374 -> 976723 (-0.07%) InvThroughput: 651582 -> 651148 (-0.07%) Copies: 5064 -> 5033 (-0.61%) PreSGPRs: 430 -> 433 (+0.70%) Signed-off-by: Konstantin Seurer <> Reviewed-by: Daniel Schürmann <> Part-of: <>
40 hoursci/freedreno: disable Stellaris traceDavid Heidelberg1-4/+5
Revert when it gets fixed on CI runner (works on OnePlus 6T with 5.18 kernel). Signed-off-by: David Heidelberg <> Part-of: <>
40 hoursci/freedreno: temporary disable AmnesiaTDDDavid Heidelberg1-4/+5
Revert when get fixed. Signed-off-by: David Heidelberg <> Part-of: <>
40 hoursci/freedreno: add more restricted tracesDavid Heidelberg1-15/+69
Signed-off-by: David Heidelberg <> Part-of: <>
41 hoursnir/opt_shrink_vectors: fix re-using of components for vecNDaniel Schürmann1-2/+4
Cc: mesa-stable Reviewed-by: Emma Anholt <> Part-of: <>
41 hoursir3: Use NIR's info.writes_memory to detect when when to force late-zDanylo Piliaiev1-14/+4
Better than maintaining our old checks. Signed-off-by: Danylo Piliaiev <> Part-of: <>
42 hoursv3dv: fix pool descriptor count for inline uniform buffersIago Toral Quiroga1-1/+1
Fixes VK_ERROR_OUT_OF_POOL_MEMORY in the inlineuniformblocks sample from Sascha Willems. Fixes: ea3223e7a46 ('v3dv: implement VK_EXT_inline_uniform_block') Reviewed-by: Alejandro Piñeiro <> Part-of: <>
43 hoursvulkan/wsi: Disable dma-buf sync file if ENOSYS is returnedJordan Justen1-2/+2
ENOSYS is commented as "Invalid system call number". This is returned by qemu-user for unbridged ioctls. Fixes: 30b57f10b36d ("vulkan/wsi: Signal semaphores and fences from the dma-buf") Signed-off-by: Jordan Justen <> Reviewed-by: Jason Ekstrand <> Part-of: <>
43 hoursdzn: Mark transition barriers as executed when we execute barriersBoris Brezillon1-4/+4
It was previously done dzn_cmd_buffer_flush_transition_barriers(), leaving the queue+flush case unhandled. Let's fix that by moving this piece of code to dzn_cmd_buffer_exec_transition_barriers(). Fixes: 35356b1173e ("dzn: Cache and pack transition barriers") Reviewed-by: Jesse Natalie <> Part-of: <>
45 hoursbroadcom/rpi4-skips: drop duplicated linesEric Engestrom1-20/+0
Signed-off-by: Eric Engestrom <> Reviewed-by: Juan A. Suarez <> Part-of: <>
2 daysglsl: drop non-nir path for atan in builtin functionsTimothy Arceri1-177/+3
All drivers now use NIR. Here we drop the non NIR path and rename the NIR path to drop the extra "_op" chars from the function names. Reviewed-by: Emma Anholt <> Part-of: <>
2 daysintel/fs: Opportunistically split SEND message payloadsKenneth Graunke2-0/+95
While we've taken advantage of split-sends in select situations, there are many other cases (such as sampler messages, framebuffer writes, and URB writes) that have never received that treatment, and continued to use monolithic send payloads. This commit introduces a new optimization pass which detects SEND messages with a single payload, finds an adjacent LOAD_PAYLOAD that produces that payload, splits it two, and updates the SEND to use both of the new smaller payloads. In places where we manually used split SENDS, we rely on underlying knowledge of the message to determine a natural split point. For example, header and data, or address and value. In this pass, we instead infer a natural split point by looking at the source registers. Often times, consecutive LOAD_PAYLOAD sources may already be grouped together in a contiguous block, such as a texture coordinate. Then, there is another bit of data, such as a LOD, that may come from elsewhere. We look for the point where the source list switches VGRFs, and split it there. (If there is a message header, we choose to split there, as it will naturally come from elsewhere.) This not only reduces the payload sizes, alleviating register pressure, but it means that we may be able to eliminate some payload construction altogether, if we have a contiguous block already and some extra data being tacked on to one side or the other. shader-db results for Icelake are: total instructions in shared programs: 19602513 -> 19369255 (-1.19%) instructions in affected programs: 6085404 -> 5852146 (-3.83%) helped: 23650 / HURT: 15 helped stats (abs) min: 1 max: 1344 x̄: 9.87 x̃: 3 helped stats (rel) min: 0.03% max: 35.71% x̄: 3.78% x̃: 2.15% HURT stats (abs) min: 1 max: 44 x̄: 7.20 x̃: 2 HURT stats (rel) min: 1.04% max: 20.00% x̄: 4.13% x̃: 2.00% 95% mean confidence interval for instructions value: -10.16 -9.55 95% mean confidence interval for instructions %-change: -3.84% -3.72% Instructions are helped. total cycles in shared programs: 848180368 -> 842208063 (-0.70%) cycles in affected programs: 599931746 -> 593959441 (-1.00%) helped: 22114 / HURT: 13053 helped stats (abs) min: 1 max: 482486 x̄: 580.94 x̃: 22 helped stats (rel) min: <.01% max: 78.92% x̄: 4.76% x̃: 0.75% HURT stats (abs) min: 1 max: 94022 x̄: 526.67 x̃: 22 HURT stats (rel) min: <.01% max: 188.99% x̄: 4.52% x̃: 0.61% 95% mean confidence interval for cycles value: -222.87 -116.79 95% mean confidence interval for cycles %-change: -1.44% -1.20% Cycles are helped. total spills in shared programs: 8387 -> 6569 (-21.68%) spills in affected programs: 5110 -> 3292 (-35.58%) helped: 359 / HURT: 3 total fills in shared programs: 11833 -> 8218 (-30.55%) fills in affected programs: 8635 -> 5020 (-41.86%) helped: 358 / HURT: 3 LOST: 1 SIMD16 shader, 659 SIMD32 shaders GAINED: 65 SIMD16 shaders, 959 SIMD32 shaders Total CPU time (seconds): 1505.48 -> 1474.08 (-2.09%) Examining these results: the few shaders where spills/fills increased were already spilling significantly, and were only slightly hurt. The applications affected were also helped in countless other shaders, and other shaders stopped spilling altogether or had 50% reductions. Many SIMD16 shaders were gained, and overall we gain more SIMD32, though many close to the register pressure line go back and forth. Reviewed-by: Francisco Jerez <> Part-of: <>
2 daysintel/compiler: Handle split-sends in EOT high-register pinning caseKenneth Graunke1-2/+7
SEND messages with EOT need to use g112-g127 for their sources so that the hardware is able to launch new threads while old ones are finishing without worrying about register overlap when pushing payloads. For the newer split-send messages, this applies to both source registers. Our special case for this in the register allocator was only considering the first source. This wasn't a problem because we hadn't ever tried to use split-sends with EOT before. However, my new optimization pass is going to introduce some shortly, so we'll need to handle them properly. Reviewed-by: Francisco Jerez <> Part-of: <>
2 daysaco: drop radv_shader.h includeDave Airlie1-1/+0
This shouldn't be used anymore Reviewed-by: Daniel Schürmann <> Part-of: <>
2 daysaco/radv: provide a vs prolog callback from aco to radv.Dave Airlie3-23/+51
Avoid building the radv binary in aco, just callback with the necessary info. Reviewed-by: Daniel Schürmann <> Part-of: <>
2 daysaco/radv: provide a callback from aco shader building to build binaryDave Airlie3-73/+89
This moves the radv specific code into radv, and calls back from aco into radv. This should allow easier radeonsi integration later. Reviewed-by: Daniel Schürmann <> Part-of: <>
2 daysaco: refactor the radv binary builder out of the core aco fn.Dave Airlie1-42/+71
Reviewed-by: Daniel Schürmann <> Part-of: <>
2 daysintel/compiler: Convert brw_eu.cpp back to brw_eu.cKenneth Graunke2-4/+4
Now that we've removed the thread_local lookup tables using pointer-to-member C++ features, this can go back to being a standard C file, like it was in the past. We just need to annotate a couple of things with "struct". Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Remove use of thread_local for opcode tablesKenneth Graunke2-44/+22
We had been using thread_local index -> opcode_desc tables to avoid plumbing through a storage location throughout all the code. But now we have done so with the new brw_isa_info structure. So we can just store the tables there, and initialize it with the compiler. This fixes crashes in gtk4-demo on iris, and should help with some programs on zink as well. Something was going wrong with the thread_local variables not being set up correctly. While we might be able to work around that issue, there's really no advantage to storing these lookup tables in TLS (beyond it being simpler to do originally). So let's simply stop doing so. Closes: Closes: Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Introduce a new brw_isa_info structureKenneth Graunke48-399/+541
This structure will contain the opcode mapping tables in the next commit. For now, this is the mechanical change to plumb it into all the necessary places, and it continues simply holding devinfo. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Move opcode_desc handling to a separate headerKenneth Graunke4-48/+88
This patch creates a new header file, brw_isa_info.h, which will contains all the functions related to opcode encoding on various generations. Opcode numbers may have different meanings on different hardware, so we remap them between an enum we can easily work with and the hardware encoding. We move the brw_inst setters and getters to brw_inst.h. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/tools: Stop malloc'ing device info in i965_disasmKenneth Graunke1-26/+5
There's not really any point, a stack allocated struct works fine. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Split 3DPRIM_* defines out to a separate header.Kenneth Graunke13-23/+61
These clash with genxml and will become a problem shortly. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Fix brw_gfx_ver_enum.h to be a proper header fileKenneth Graunke1-1/+6
This header file didn't include normal guards against being included multiple times. It also defined a function in a header file without marking it static inline. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysintel/compiler: Stop including src/mesa/main/config.hKenneth Graunke6-15/+16
src/mesa/main includes are for Mesa's OpenGL implementation, and the compiler is used in Vulkan drivers and other tools. We really only needed one #define, which is that we offer 32 samplers. It probably makes more sense to have our own defined limit for that rather than importing a project-wide value which theoretically could be adjusted, so swap MAX_SAMPLERS for a new BRW_MAX_SAMPLERS and call it a day. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 dayscrocus: Use PIPE_* defines rather than ones from main/config.hKenneth Graunke2-10/+10
Gallium drivers shouldn't be including src/mesa/main headers, but we're picking up a rogue main/config.h via the compiler, so this code I ported over from i965 kept compiling. Use the PIPE_* defines instead so that we can stop including that. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 daysiris: Use PIPE_* defines rather than ones from main/config.hKenneth Graunke2-10/+10
Gallium drivers shouldn't be including src/mesa/main headers, but we're picking up a rogue main/config.h via the compiler, so this code I ported over from i965 kept compiling. Use the PIPE_* defines instead so that we can stop including that. Reviewed-by: Lionel Landwerlin <> Part-of: <>
2 dayszink: enforce viewport depth clampingMike Blumenkrantz2-5/+15
VUID-VkViewport-minDepth-01234 specifies that depth must be in the range [0.0, 1.0], so the viewport must always be clamped to this range this affects texture clears using u_blitter, as this expects to be able to use the GL range of [-1.0, 1.0], so pass the depth value as though it's been de-converted back to a GL z coordinate to account for viewport transform cc: mesa-stable fixes #6757 Reviewed-by: Dave Airlie <> Part-of: <>
2 dayslavapipe: don't remove xfb outputsMike Blumenkrantz1-1/+9
cc: mesa-stable fixes: dEQP-VK.transform_feedback.simple.multiquery_omit_write_1 dEQP-VK.transform_feedback.simple.multiquery_omit_write_3 dEQP-VK.transform_feedback.simple.query_omit_write_0_127_32bits dEQP-VK.transform_feedback.simple.query_omit_write_0_127_64bits dEQP-VK.transform_feedback.simple.query_omit_write_0_251_32bits dEQP-VK.transform_feedback.simple.query_omit_write_0_251_64bits dEQP-VK.transform_feedback.simple.query_omit_write_0_4_32bits dEQP-VK.transform_feedback.simple.query_omit_write_0_4_64bits dEQP-VK.transform_feedback.simple.query_omit_write_0_509_32bits dEQP-VK.transform_feedback.simple.query_omit_write_0_509_64bits dEQP-VK.transform_feedback.simple.query_omit_write_0_61_32bits dEQP-VK.transform_feedback.simple.query_omit_write_0_61_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_64bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_64bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_32bits dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_64bits Reviewed-by: Dave Airlie <> Part-of: <>
2 dayszink: disable turnip traces temporarilyMike Blumenkrantz1-1/+1
this needs a libX11 update Reviewed-by: Emma Anholt <> Part-of: <>
2 daysvenus: use narrow range to match up with mesa EGLYiwei Zhang1-1/+2
This matches up with the native gl drivers as well as the media stack. Test: Test: Signed-off-by: Yiwei Zhang <> Reviewed-by: Ryan Neph <> Reviewed-by: Chad Versace <> Part-of: <>
2 daysradv/ci: re-enable vega10 fossils testingRhys Perry1-3/+3
Should work now. Signed-off-by: Rhys Perry <> Reviewed-by: Daniel Schürmann <> Part-of: <>
2 daysaco/ra: update register file when updating phi definitionRhys Perry1-0/+1
update_renames() fills in the wrong temp id. Signed-off-by: Rhys Perry <> Reviewed-by: Daniel Schürmann <> Fixes: 302cb5c9001 ("aco/ra: remove some redundant code") Part-of: <>