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43 Skip the piglit glx tests since we're not running X.HEADmainEmma Anholt2-107/+3
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43 min.i915g: Finish out blend factor overrides for both RGBx and A8.Emma Anholt7-57/+96
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43 min.i915g: Fix bad naming of depth texture formats.Emma Anholt2-4/+4
Now matches classic's i915_reg.h and the spec. Part-of: <>
3 hoursir3/ra: Fix corner case in collect handlingConnor Abbott1-2/+13
I ran into this when accidentally changing the scheduling order in the hl2 trace. Fixes: 0ffcb19 ("ir3: Rewrite register allocation") Part-of: <>
3 hoursir3: Remove IR3_REG_DESTConnor Abbott6-20/+17
This was needed because code iterating the regs array needed to know what was a destination and what wasn't, but now we have separate srcs and dsts arrays so it's not needed. Part-of: <>
3 hoursir3: Remove regs arrayConnor Abbott3-31/+14
Now that everything is converted over, switch to separate src/dst arrays. Part-of: <>
3 hoursir3/frontend: Switch to srcs/dsts arraysConnor Abbott5-80/+80
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3 hoursir3/opts: Switch to srcs/dsts arraysConnor Abbott5-57/+60
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3 hoursir3/validate: Switch to srcs/dsts arraysConnor Abbott1-42/+54
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3 hoursir3/print: Switch to srcs/dsts arraysConnor Abbott1-10/+18
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3 hoursir3/legalize: Switch to srcs/dsts arraysConnor Abbott1-17/+21
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3 hoursir3/array_to_ssa: Switch to srcs/dsts arraysConnor Abbott1-28/+41
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3 hoursir3/parser: Switch to srcs/dsts arraysConnor Abbott1-21/+14
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3 hoursir3/ra: Switch to srcs/dsts arraysConnor Abbott7-140/+143
RA was manually fiddling with regs to copy over the parallel copy code, which has to be done in a different way, but if we switch this all over at once it shouldn't be a problem. Part-of: <>
3 hoursir3/core: Switch to srcs/dsts arraysConnor Abbott2-48/+48
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3 hoursir3/sched: Convert to srcs/dsts arraysConnor Abbott4-40/+34
Also change the indexing in ir3_delayslots, so it's finally sane! To do this we also have to change foreach_ssa_src_n to index srcs instead of regs, so that the indexing stays in sync. Part-of: <>
3 hoursfreedreno/tests: Convert to srcs/dstsConnor Abbott1-1/+1
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3 hoursfreedreno/isa: Convert to srcs/dstsConnor Abbott9-111/+112
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3 hoursir3: Add srcs/dsts arrays to ir3_instructionConnor Abbott2-1/+10
Initially these will shadow regs, so that we can transition things before getting rid of regs. Part-of: <>
3 hoursir3/legalize: Construct branch properlyConnor Abbott1-1/+2
Don't just yeet stuff into regs without updating regs_count, etc. This will break horribly during the transition otherwise. Part-of: <>
3 hoursir3: Add separate src/dst count in ir3_instrConnor Abbott10-49/+64
srcs and dsts will be in separate arrays, so we need everything creating it to give a separate source and dest max count. Part-of: <>
3 hoursir3: Split ir3_reg_create() into ir3_{src,dst}_create()Connor Abbott9-95/+132
Right now they are basically the same, but in the future they will append to different arrays. Part-of: <>
3 hoursir3: Make ir3_instruction::address a normal registerConnor Abbott10-69/+44
This fixes an annoying mismatch in the indices between foreach_ssa_src_n and ir3_delayslots(), and lets us remove a bunch of other special cases. Part-of: <>
3 hoursir3: Add is_reg_special()Connor Abbott2-1/+12
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3 hoursir3: Validate that ir3_register::instr is correctConnor Abbott1-0/+3
Catch the mistake fixed in the previous commit. Part-of: <>
3 hoursir3: Update ir3_register::instr when cloning instructionsConnor Abbott1-0/+2
We happened to not clone any SSA instructions, but we will once address instructions start counting as SSA. Fix this oversight. Part-of: <>
3 hoursir3: Split read-modify-write array dests in twoConnor Abbott10-59/+56
Instructions that operate on an array read the previous state of the array, modify it, and write a new array, at least conceptually before RA. Previously the same register specified the previous state and acted as the new state, but this meant that it was both a source and destination which meant that it was getting in the way of splitting up sources and destinations. Break out the source into a separate register, and use the new tied-src infrastructure to share code with a6xx atomics. With this, there are basically no more special cases for arrays in RA. Part-of: <>
3 hoursir3: Make tied sources/destinations part of the IRConnor Abbott8-31/+57
Previously this was hard-coded for a6xx atomic instructions. However we'll need a way for array destinations to point to the source with the previous value of the array when we split them up. This is conceptually the same as tied source/destinations for a6xx atomics, except that array writes sometimes won't have a previous value to point to. So move this into the IR so that it can be more dynamic. As a bonus we can move the knowledge of a6xx atomics out of RA, where it's out-of-place, and into the a6xx-specific code that creates them. Part-of: <>
5 hoursamd/ci: add hawaii-specific skip and fail listsDaniel Schürmann2-0/+48
Reviewed-by: Samuel Pitoiset <> Part-of: <>
6 hourspan/mdg: Add 16 bytes of padding to the end of shadersIcecream951-0/+6
Fixes INSTR_INVALID_PC faults when a shader ends on a 16MB boundary. Cc: mesa-stable Part-of: <>
9 hoursanv: fix emitting dynamic primitive topologyTapani Pälli7-126/+295
Initial implementation missed various fields that derive from the primitive topology. This patch fixes 3DSTATE_RASTER/3DSTATE_SF, 3DSTATE_CLIP and 3DSTATE_WM (gen7.x) emission in the dynamic case. Fixes: f6fa4a80000 ("anv: add support for dynamic primitive topology change") Closes: Signed-off-by: Tapani Pälli <> Reviewed-by: Lionel Landwerlin <> Part-of: <>
9 hoursRevert "ci: disable panfrost t760 jobs"Daniel Stone1-2/+2
Both our T760 machines took a dive in beautiful synchronicity last night, were recovered early this morning. This reverts commit 854d93f73d6064a13ddc13dddf74c8c760cda1d4. Part-of: <>
10 hoursiris: take a reference to memobj bo in iris_resource_from_memobjTapani Pälli1-2/+2
v2: and remove it from iris_memobj_create_from_handle ... (Nanley) Closes: Fixes: 772dc50d162 ("iris: hook up resource creation from memory object") Signed-off-by: Tapani Pälli <> Reviewed-by: Nanley Chery <> Part-of: <>
12 hoursradeonsi: disable ngg culling on llvm < 12Pierre-Eric Pelloux-Prayer1-1/+3
Closes: Reviewed-by: Marek Olšák <> CC: mesa-stable Part-of: <>
12 hoursanv: bound checks buffer memory binding in debug buildsLionel Landwerlin1-0/+2
Validation layers should warn you about this (VUID-VkBindBufferMemoryInfo-size-01037) but this would be useful for zink debugging. Requested by Zmike. v2: Also check memoryOffset (Jason) Signed-off-by: Lionel Landwerlin <> Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Implement Wa_14013745556 on TGL+.Francisco Jerez1-0/+17
Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Fix synchronization of accumulator-clearing W/A move on TGL+.Francisco Jerez1-3/+6
Right now the accumulator-clearing move emitted by the generator for Wa_14010017096 inherits the SWSB field from the previous instruction. This can lead to redundant synchronization, or possibly more serious issues if the previous instruction had a TGL_SBID_SET SWSB synchronization mode. Take the SWSB synchronization information from the IR. Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT") Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Teach IR about EOT instruction writing the accumulator implicitly ↵Francisco Jerez1-1/+2
on TGL+. This is unlikely to have had any negative side effect on the original TGL, but will lead to issues on XeHP+ if the software scoreboard pass isn't able to synchronize the accumulator writes. Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT") Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Add SWSB dependency annotations for cross-pipeline WaR data ↵Francisco Jerez1-4/+9
hazards on XeHP+. In cases where an in-order instruction is overwriting a register previously read by another in-order instruction, drop the dependency iff the previous read is guaranteed to have occurred from the same in-order pipeline. This should only have an effect on XeHP+ since previous Xe platforms only had one in-order FPU pipeline. The previous workaround we were using for this treated all ordered read dependencies as write dependencies to avoid noise from our simulation environment. Relative to our previous workaround this improves performance of GFXBench5 gl_tess by ~7% on a DG2 system among other single-digit percentual FPS improvements. Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Implement Wa_22012725308 for cross-pipe accumulator data hazard.Francisco Jerez1-1/+50
The hardware fails to provide the expected data coherency guarantees for accumulator registers when accessed from multiple FPU pipelines. Fix this by tracking implicit accumulator accesses just like we do for regular GRF registers, but instead of adding synchronization annotations for any dependency we only do it for dependencies with a pipeline mismatch, since the hardware should be able to guarantee proper synchronization for matching pipelines. Note that this workaround handles RaW and WaW dependencies in addition to the WaR dependencies described in the hardware bug report even though cross-pipeline RaW accumulator dependencies should be extremely rare, since chances are the hardware will also hang if we ever hit such a condition. This only affects XeHP+, since all FPU instructions are executed as a single in-order pipeline on earlier Xe platforms. Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs: Track single accumulator in scoreboard lowering pass.Francisco Jerez1-16/+9
This change reduces the precision of the scoreboard data structure for accumulator registers, because the rules determining the aliasing of accumulator registers are non-trivial and poorly documented (e.g. acc0 overlaps the storage of acc1 when the former is accessed with an integer type). We could implement those rules but it wouldn't have any practical benefit since we currently only use acc0-1, and for the most part we can rely on the hardware's accumulator dependency tracking. Instead make our lives easier by representing it as a single register. Reviewed-by: Jason Ekstrand <> Part-of: <>
13 hoursintel/fs/xehp: Assert that the compiler is sending all 3 coords for cubemaps.Francisco Jerez2-2/+11
As required by HSDES:14013363432. Reviewed-by: Jason Ekstrand <> Part-of: <>
14 hoursfreedreno/ci: Use TU_IGNORE_CONFORMANCE_WARNING to reduce warningsMatt Turner1-0/+3
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14 hourstu: Provide a toggle to avoid warnings about unsupported devicesMatt Turner1-2/+10
In the CI, we have such devices, and this message is printed many hundreds of times. This results in a useless spam which makes it difficult to see real issues. Part-of: <>
14 hoursmeson/crocus: add prefer-crocus option.Dave Airlie1-0/+4
This just allows picking crocus without having to set the env var. Acked-by: Alyssa Rosenzweig <> Acked-by: Adam Jackson <> Part-of: <>
15 hoursmesa: unreference zombie buffers when creating buffers to lower memory usageMarek Olšák1-2/+19
This fixes an issue where one context only creates buffers while another context only destroys buffers. Only the creating context can release its buffers and the destroying context only turns them into zombie buffers. This fix makes the creating context release its zombie buffers. It's not a plot from an apocalyptic movie. Fixes: e014e3b6be6 "mesa: don't count buffer references for the context that created them" Closes: Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
15 hourscrocus: fix batch state bo leakDave Airlie1-0/+1
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15 hourscrocus: fix vertex buffer leak on screen end.Dave Airlie1-0/+2
this was stopping the screen from being cleaned up as well Part-of: <>
15 hourscrocus: free context state properly.Dave Airlie1-1/+2
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17 hourszink: ci updatesMike Blumenkrantz1-16/+0
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