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2024-04-09r600: update licensing to SPDX headerDavid Heidelberg1-19/+2
Acked-by: Gert Wollny <gert.wollny@collabora.com> Signed-off-by: David Heidelberg <david@ixit.cz> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28395>
2024-01-06r300,r600,radeonsi: switch to pb_buffer_leanMarek Olšák1-2/+2
to remove pb_buffer::vtbl from all buffer structures Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_buffer: define pb_buffer_lean without vtbl, inherit it by pb_bufferMarek Olšák1-2/+2
amdgpu doesn't need vtbl. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2023-10-31r600: Replace TGSI I/O semantics with shader_enumsVitaliy Triang3l Kuzmin1-35/+40
Removes the link-time dependency on tgsi_get_gl_varying_semantic from Gallium auxiliary. ps_prim_id_input linkage removed due to redundancy - the SPI SID is calculated for VARYING_SLOT_PRIMITIVE_ID on both sides. Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25695>
2023-10-31r600: Remove Gallium dependencies in r600_asmVitaliy Triang3l Kuzmin1-1/+2
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25695>
2023-10-01r600: Replace R600_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIANVitaliy Triang3l Kuzmin1-2/+3
In particular, removes the dependency of r600_formats.h on r600_pipe.h so it can be shared between Gallium and Vulkan. Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24513>
2023-08-18r600: better tracking for vertex buffer emissionMike Blumenkrantz1-2/+2
Fixes: 76725452 (gallium: move vertex stride to CSO) Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24754>
2023-08-17r600: use correct cso pointer for fetch shaderGert Wollny1-1/+1
Fixes: 76725452 (gallium: move vertex stride to CSO) Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9567 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24728>
2023-08-14gallium: move vertex stride to CSOMike Blumenkrantz1-1/+3
this simplifies code in most place and enables some optimizations in frontends Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24117>
2023-07-07r600: Pre-EG - Set wrap texture modes to repeat when seemless cube is usedGert Wollny1-0/+14
On Pre-Evergreen hardware we have a flag "Force Clamp X,Y policy to wrap for CubeMaps" but it doesn't seem to affect how border clamping is done. With bf3027 this is set to PIPE_TEX_WRAP_CLAMP_TO_EDGE for cube maps, and results in the regression reported in #9028. Forcing repeat mode fixes the issue. Fixes: bf3027c3916ad5be172c22851e7172671709a9bc mesa/st: Normalize wrap modes for seamless cubes Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9028 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23848>
2023-06-27treewide: Replace the usage of TRUE/FALSE with true/falseYonggang Luo1-7/+7
this is a separate patch as it's won't affect the code style Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
2023-06-27treewide: replace usage of boolean to boolYonggang Luo1-2/+2
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
2023-05-01r600+sfn: Assign ps_conservative_z and switch to NIR definesGert Wollny1-3/+3
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22778>
2023-04-17r600: Report multi-plane formats as unsupportedAndres Calderon Jaramillo1-0/+3
This is the analogous of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9490 but for r600. Discoloration of NV12 video frames was observed in Chrome/ChromeOS and the problem was tracked down to the fact that Mesa was following the PIPE_FORMAT_R8_G8B8_420_UNORM/lower_yuv_external() path. The symptom is that (for an unknown reason) the YUV-to-RGB conversion is using the value of Y as the value of Y, U, and V. So, for example, if the input value is YUV = (50, 120, 130), then what actually gets converted to RGB is YUV = (50, 50, 50). Considering that PIPE_FORMAT_R8_G8B8_420_UNORM was introduced for freedreno (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6693) and it is already being reported as unsupported for radeonsi, it's reasonable to assume that GPUs targeted by r600 don't support this path either. Note: I tested this patch with an AMD Palm device which follows the evergreen_is_format_supported() path. I did not have access to a device to test the r600_is_format_supported() path. v2: Changed >= 2 to > 1. Fixes: 826a10255f5 ("st/mesa: Add NV12 lowering to PIPE_FORMAT_R8_G8B8_420_UNORM") Tested-by: Andres Calderon Jaramillo <andrescj@chromium.org> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22511>
2023-04-13r600: fix typosHarri Nieminen1-6/+6
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
2022-12-02r600: Use get_first_non_void_channel more oftenKonstantin Seurer1-5/+1
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18634>
2022-07-27gallium/radeon: require radeon DRM 2.45.0 from April 2016Marek Olšák1-4/+2
This removes most non-radeonsi workarounds. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-05-13amd: change chip_class naming to "enum amd_gfx_level gfx_level"Marek Olšák1-22/+22
This aligns the naming with PAL. Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
2022-05-02r600: Allow eight bit, three channel formats for vertex buffersGert Wollny1-2/+2
While using three component texture formats results in CTs failures, three component vertex attributes are fine, and not allowing them results in significant performance regressisons. Fixes: e41958e344cb4b15d01008140a1ee08817104334 r600: Disable eight bit three channel formats Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6399 v2: rename function to is_buffer_format_supported (Emma) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16267>
2022-03-28r600: Update the PS state when MSAA-ness changes, too.Emma Anholt1-7/+12
Avoids a regression when enabling shader precompilation, where the precompile would happen with MSAA disabled (so no sample mask export) but we'd never catch up to the shader being rendered with MSAA. Doesn't fix any current testcases, though. Acked-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
2021-10-29gallium/radeon: merge BO read/write usage flags with priority flagsMarek Olšák1-22/+22
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-06-04r600: explicitly advertise index buffer format supportErik Faye-Lund1-0/+5
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
2021-04-12ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8Marek Olšák1-11/+11
Images are always aligned to 256B (enforced by register and descriptor fields) and limited to 40-bit addresses. This saves some space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-06gallium/pb: change pb_buffer::alignment to alignment_log2Marek Olšák1-2/+2
Alignments are always 2^n, so store n = log2(alignment). The next commit will take advantage of the saved space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-02-25r600: Fix typos.Vinson Lee1-1/+1
Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8293>
2020-12-22gallium: inline pipe_depth_state to decrease DSA state size by 4 bytesMarek Olšák1-6/+6
Depth and alpha states are now packed together, interleaved somewhat. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7940>
2020-12-22gallium: inline pipe_alpha_state to enable better DSA bitfield packingMarek Olšák1-3/+3
pipe_alpha_state and pipe_depth_state will be packed together because they have only a few bitfields each. This will eventually remove 4 bytes of padding in pipe_depth_stencil_alpha_state. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7940>
2020-12-05r300,r600,radeonsi: inline struct radeon_cmdbuf to remove dereferencesMarek Olšák1-19/+19
It's straightforward except that the amdgpu winsys had to be cleaned up to allow this. radeon_cmdbuf is inlined and optionally the winsys can save the pointer to it. radeon_cmdbuf::priv points to the winsys cs structure. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7907>
2020-09-22gallium: rename PIPE_TRANSFER_* -> PIPE_MAP_*Marek Olšák1-1/+1
Acked-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5749>
2020-05-18r600: enable TEXCOORD semantic for TGSI.Dave Airlie1-11/+10
This should make intergrating with NIR easier Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5083>
2019-07-22gallium: switch boolean -> bool at the interface definitionsIlia Mirkin1-11/+11
This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-05-02r600: reset tex array override even when no view boundDave Airlie1-11/+10
If no view is bound we still should reset the override to 0 and array mode. This should fix misrendering in firefox WebRender since the pbo sampler was removed. Fixes: 1250383e36 (st/mesa: remove sampler associated with buffer texture in pbo logic)
2018-09-06gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák1-1/+1
2018-09-06gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák1-2/+2
for AMD_depth_clamp_separate.
2018-07-31gallium: add storage_sample_count parameter into is_format_supportedMarek Olšák1-0/+4
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-07-17r600g: constify some variablesKonstantin Kharlamov1-6/+6
Just a nice hint for both peoples and compilers. Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-07-16r600: fix build after the removal of RADEON_PRIO_* flagsMarek Olšák1-4/+2
2018-07-16radeonsi: merge DCC/CMASK/HTILE priority flagsMarek Olšák1-1/+1
For a later simplification. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-06-29gallium/util: remove dummy function util_format_is_supportedMarek Olšák1-3/+0
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2018-06-19amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák1-17/+17
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-10r600: fix constant buffer bounds.Dave Airlie1-1/+1
If you have an indirect access to a constant buffer on r600/eg use a vertex fetch in the shader. However apps have expected behaviour on those out of bounds accessess (even if illegal). If the constants were being uploaded as part of a larger upload buffer, we'd set the range of allowed access to a lot larger than required so apps would get values back from other parts of the upload buffer instead of the expected out of bounds access. This fixes rendering bugs in Trine and Witcher 1, thanks to iive for nagging me effectively until I figured it out :-) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808 Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-03-05r600: fix color export maskRoland Scheidegger1-0/+1
The r600 code (not the eg one) forgot to copy the ps_color_export_mask in commit 5b14e06d8b42e2b08ebc52b6c314ef8647d87a1f when updating the pixel state, leading to misrenderings (probably with MRT). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105262 Tested-by: LoneVVolf <lonewolf@xs4all.nl> Tested-by: Pavel Vinogradov <public@sourcemage.org>
2018-02-08r600: fix rendering regression on r6/7 gpusDave Airlie1-1/+6
Fixes: 2d5b5d267e (r600: work out target mask at framebuffer bind.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104989 Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-02-07r600: work out target mask at framebuffer bind.Dave Airlie1-1/+1
If we only get 1,2,3,6 framebuffers we want a sparse target mask. Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-02-07r600: work out shader export mask at shader build time (v1.1)Dave Airlie1-1/+1
Since enhanced layouts allows setting specific MRT outputs, we can get sparse outputs, so we have to calculate the shader mask earlier. v1.1: update checks for state update (Roland) Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-10r600: increase number of ubos by one to 14Roland Scheidegger1-0/+1
Ideally we'd support 16 (d3d11 requires 15, and mesa subtracts one for non-ubo constants), but that's kind of impossible (it would be only doable if either we'd somehow merge the mesa non-ubo constants with the driver constants, or only use the driver constants with vtx fetch instead of through the kcache mechanism - the latter probably wouldn't be too bad). For now just do as the comment already said, place the gs ring (not really a const buffer in any case) which is only ever referred to through vc fetch clauses at index 16. Throw in a couple asserts for good measure to make sure the hw limit isn't exceeded. Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru> Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-10r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger1-4/+3
It looks like this reloc belongs to setting the constant reg, which is skipped for gs ring. Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-11-27ac: change legacy_surf_level::slice_size to dword unitsMarek Olšák1-4/+4
The next commit will reduce the size even more. v2: typecast to uint64_t manually v3: add more typecasts, add asserts Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-15r600: set the number type correctly for float rts in cb setupRoland Scheidegger1-1/+9
Float rts were always set as unorm instead of float. Not sure of the consequences, but at least it looks like the blend clamp would have been enabled, which is against the rules (only eg really bothered to even attempt to specify this correctly, r600 always used clamp anyway). Albeit r600 (not r700) setup still looks bugged to me due to never setting BLEND_FLOAT32 which must be set according to docs... Not sure if the hw really cares, no piglit change (on eg/juniper). Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-11-15r600: use DX10_CLAMP bit in shader setupRoland Scheidegger1-0/+9
The docs are not very concise in what this really does, however both Alex Deucher and Nicolai Hähnle suggested this only really affects instructions using the CLAMP output modifier, and I've confirmed that with the newly changed piglit isinf_and_isnan test. So, with this bit set, if an instruction has the CLAMP modifier bit (which clamps to [0,1]) set, then NaNs will be converted to zero, otherwise the result will be NaN. D3D10 would require this, glsl doesn't have modifiers (with mesa clamp(x,0,1) would get converted to such a modifier) coupled with a whatever-floats-your-boat specified NaN behavior, but the clamp behavior should probably always be used (this also matches what a decomposition into min(1.0, max(x, 0.0)) would do, if min/max also adhere to the ieee spec of picking the non-nan result). Some apps may in fact rely on this, as this prevents misrenderings in This War of Mine since using ieee muls (ce7a045feeef8cad155f1c9aa07f166e146e3d00), without having to use clamped rcp opcode, which would also fix this bug there. radeonsi also seems to set this bit nowadays if I see that righ (albeit the llvm amdgpu code comment now says "Make clamp modifier on NaN input returns 0" instead of "Do not clamp NAN to 0" since it was changed, which also looks a bit misleading). v2: set it in all shader stages. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544 Reviewed-by: Dave Airlie <airlied@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 00:42:22 +0000