diff options
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 8 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_shader_args.c | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_shader_info.c | 8 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5e03dbb593d..c6d029159c7 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -543,7 +543,7 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, */ num_targets = (util_last_bit(col_format) + 3) / 4; for (unsigned i = 0; i < num_targets; i++) { - if (!(col_format & (0xf << (i * 4)))) { + if (!(col_format & (0xfu << (i * 4)))) { col_format |= V_028714_SPI_SHADER_32_R << (i * 4); } } @@ -681,7 +681,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, continue; blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); - blend.cb_target_enabled_4bit |= 0xf << (4 * i); + blend.cb_target_enabled_4bit |= 0xfu << (4 * i); if (!att->blendEnable) { blend.cb_blend_control[i] = blend_cntl; continue; @@ -701,9 +701,9 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, } radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB, - 0x7 << (4 * i)); + 0x7u << (4 * i)); radv_blend_check_commutativity(&blend, eqA, srcA, dstA, - 0x8 << (4 * i)); + 0x8u << (4 * i)); /* Blending optimizations for RB+. * These transformations don't change the behavior. diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index 1b57d402d5c..c6070dfe8ef 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -68,7 +68,7 @@ set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) set_loc(ud_info, sgpr_idx, 1); - locs->descriptor_sets_enabled |= 1 << idx; + locs->descriptor_sets_enabled |= 1u << idx; } struct user_sgpr_info { diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 2c8d4e0511f..63a1f19e771 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -29,7 +29,7 @@ static void mark_sampler_desc(const nir_variable *var, struct radv_shader_info *info) { - info->desc_set_used_mask |= (1 << var->data.descriptor_set); + info->desc_set_used_mask |= (1u << var->data.descriptor_set); } static void mark_ls_output(struct radv_shader_info *info, @@ -288,7 +288,7 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, gather_push_constant_info(nir, instr, info); break; case nir_intrinsic_vulkan_resource_index: - info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr)); + info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr)); break; case nir_intrinsic_image_deref_load: case nir_intrinsic_image_deref_store: @@ -853,8 +853,8 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, */ unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4; for (unsigned i = 0; i < num_targets; i++) { - if (!(info->ps.cb_shader_mask & (0xf << (i * 4)))) { - info->ps.cb_shader_mask |= 0xf << (i * 4); + if (!(info->ps.cb_shader_mask & (0xfu << (i * 4)))) { + info->ps.cb_shader_mask |= 0xfu << (i * 4); } } |