diff options
| author | Tapani Pälli <tapani.palli@intel.com> | 2022-01-31 11:48:49 +0200 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2022-02-24 14:56:50 -0800 |
| commit | c820bbced0bd852ae00e60506164a168e896d078 (patch) | |
| tree | a461b55bd5c21398202ac70a2daf9fb6afe6da42 | |
| parent | b8e9c345d063c8283be9cb2e625f09e7de7ce47b (diff) | |
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/genxml/gen12.xml | 1 | ||||
| -rw-r--r-- | src/intel/genxml/gen125.xml | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index d1817a7e0d5..0afd59ad3c5 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -76,7 +76,7 @@ "description": "intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 08a49c33abf..c250da0c07c 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6450,6 +6450,7 @@ <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render"> <field name="DWord Length" start="0" end="7" type="uint" default="4"/> <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/> + <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/> <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/> <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/> <field name="Command SubType" start="27" end="28" type="uint" default="3"/> diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 6f2def17848..a11b70b405e 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -6781,6 +6781,7 @@ <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render"> <field name="DWord Length" start="0" end="7" type="uint" default="4"/> <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/> + <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/> <field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool"/> <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/> <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/> |