diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2021-04-19 08:44:40 +0200 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2021-04-20 19:43:34 +0200 |
| commit | 2c21bc476fcbe164cc30702eb3fadbfc50693b3d (patch) | |
| tree | 9b6481d31165bd74ec0be1e4fc04ec1f00c2501b | |
| parent | de8c1ab62a7a720c8cb58b24923750f19e38b9f4 (diff) | |
radv: fix emitting depth bias when beginning a command buffer
If depth bias is enabled but zero values used, they were never
emitted to the command buffer because they are equal to the default
values.
Previously, they were always emitted when the bound DS attachment
changed.
This should fix some sort of Z fighting with Dota2 on all GPUs.
This also fixes a different issue (ie. some occlusion queries failures)
on GFX6 because CLEAR_STATE is not used on that chip.
Fixes: 8a47422d977 ("radv: do not scale the depth bias for D16_UNORM depth surfaces")
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10310>
(cherry picked from commit 1d3542694bd26d6a912e558af6421aef8e62758f)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/.pick_status.json b/.pick_status.json index 99bdfd7823a..baa695f96c7 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -193,7 +193,7 @@ "description": "radv: fix emitting depth bias when beginning a command buffer", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "8a47422d9778056b2263d5f253fab49dfed91486" }, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 5e98bd2bc36..059216002ee 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1262,7 +1262,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) RADV_CMD_DIRTY_DYNAMIC_CULL_MODE | RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE; if (!cmd_buffer->state.emitted_pipeline) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY; + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | + RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS; if (!cmd_buffer->state.emitted_pipeline || cmd_buffer->state.emitted_pipeline->graphics.db_depth_control != |