diff options
| author | Francisco Jerez <currojerez@riseup.net> | 2018-12-07 14:27:24 -0800 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-04-16 08:27:35 +0000 |
| commit | 05cce1f97d87cff14f7e869f4fa5bd39d3faef29 (patch) | |
| tree | cbd055f4e42a39a44f9e3a46e2235c5eada412e9 | |
| parent | d57f3ced6caa48691f29bfa47eb957042eb9f3f2 (diff) | |
intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.
According to the hardware spec "Vx1 and VxH indirect addressing for
Float, Half-Float, Double-Float and Quad-Word data must not be used."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 938133bd77a..f3799b15ed6 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -551,7 +551,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, if (type_sz(reg.type) > 4 && ((devinfo->ver == 7 && !devinfo->is_haswell) || devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) || - !devinfo->has_64bit_float)) { + !devinfo->has_64bit_float || devinfo->verx10 >= 125)) { /* IVB has an issue (which we found empirically) where it reads two * address register components per channel for indirectly addressed * 64-bit sources. |