From 05cce1f97d87cff14f7e869f4fa5bd39d3faef29 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 7 Dec 2018 14:27:24 -0800 Subject: intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+. According to the hardware spec "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float and Quad-Word data must not be used." Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_generator.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 938133bd77a..f3799b15ed6 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -551,7 +551,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, if (type_sz(reg.type) > 4 && ((devinfo->ver == 7 && !devinfo->is_haswell) || devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) || - !devinfo->has_64bit_float)) { + !devinfo->has_64bit_float || devinfo->verx10 >= 125)) { /* IVB has an issue (which we found empirically) where it reads two * address register components per channel for indirectly addressed * 64-bit sources. -- cgit v1.2.3