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2021-03-10intel: Rename "GEN_" prefix used in common code to "INTEL_"Anuj Phogat28-305/+305
2021-03-10intel: Fix broken alignment due to gen_ prefix renamingAnuj Phogat37-179/+178
2021-03-10intel: Rename "gen_" prefix used in common code to "intel_"Anuj Phogat68-955/+955
2021-03-10intel: Rename files with gen_ prefix in common code to intel_Anuj Phogat65-151/+151
2021-03-10intel/fs: Handle payload node interference in destinationsJason Ekstrand1-0/+10
2021-03-10intel/fs: Use INTEL_MASK for pushish constant address maskingJason Ekstrand1-1/+1
2021-03-10turnip: fix alpha to coverage in no color and unused attachment casesYannik Marek2-12/+26
2021-03-10zink: Fix a thinko in instance setupAdam Jackson1-2/+2
2021-03-10turnip: Remove unused TU_DEBUG_IR3 flagMatt Turner2-2/+0
2021-03-10ci/freedreno: Mark another a5xx TF flake.Eric Anholt1-0/+1
2021-03-10radeonsi: enable RGP on gfx10.3Marek Olšák1-5/+8
2021-03-10radv: Drop CreateRenderPassJason Ekstrand1-182/+0
2021-03-10radv/meta: Use CreateRenderPass2Jason Ekstrand7-105/+181
2021-03-10anv: Drop CreateRenderPassJason Ekstrand1-170/+0
2021-03-10vulkan: Preserve preserve attachments in CreateRenderPassJason Ekstrand1-0/+2
2021-03-10vulkan: Add some asserts and checks for multiview in CreateRenderPassJason Ekstrand1-3/+7
2021-03-10vulkan: Use correct aspectMask in CreateRenderPassJason Ekstrand1-12/+54
2021-03-10anv: Move vk_format helpers to common codeJason Ekstrand22-361/+170
2021-03-10vulkan: Use VK_MULTIALLOC in CreateRenderPassJason Ekstrand1-15/+30
2021-03-10anv: Move multialloc to common codeJason Ekstrand8-151/+155
2021-03-10turnip: Move the CreateRenderPass wrapper to common codeJason Ekstrand4-145/+176
2021-03-10ac: remove switch cases for pc_lines for compute-only chipsMarek Olšák1-4/+1
2021-03-10ac,radeonsi: use correct VGPR granularity on AldebaranMarek Olšák3-5/+12
2021-03-10ac: handle bigger instruction prefetch for AldebaranMarek Olšák1-18/+24
2021-03-10ac/llvm: unpack thread IDs on AldebaranMarek Olšák2-2/+17
2021-03-10ac: set the TCC line size for AldebaranMarek Olšák1-2/+6
2021-03-10ac,radeonsi: add sampler changes for AldebaranMarek Olšák16-27/+95
2021-03-10amd: add Aldebaran chip enumJames Zhu5-1/+9
2021-03-10ir3: use OPC_GETBUF to get size of sampler buffersDanylo Piliaiev2-1/+13
2021-03-10freedreno/a5xx: port handling of PIPE_BUFFER textures from a6xxDanylo Piliaiev4-62/+62
2021-03-10turnip: fix SP_HS_WAVE_INPUT_SIZE valueDanylo Piliaiev1-13/+15
2021-03-10freedreno/computerator: Add branching exampleConnor Abbott1-0/+15
2021-03-10ir3/parser: Add ability to specify branchstackConnor Abbott2-0/+5
2021-03-10ir3/parser: Support labelsConnor Abbott3-2/+44
2021-03-10freedreno/computerator: Fix example assemblyConnor Abbott3-6/+6
2021-03-10ir3/parser: Fix parsing of "0.0" in @const lineConnor Abbott2-19/+18
2021-03-10etnaviv: Fix point sprite Z,W coordinate replacementMarek Vasut4-4/+42
2021-03-10v3dv: call util_cpu_detect() when initializing the instanceIago Toral Quiroga1-0/+3
2021-03-10broadcom/compiler: disallow ldunif during ldvary sequences if possibleIago Toral Quiroga1-4/+31
2021-03-10broadcom/compiler: simplify ldvary pipeliningIago Toral Quiroga3-86/+8
2021-03-10broadcom/compiler: move code block aroundIago Toral Quiroga1-15/+16
2021-03-10broadcom/compiler: add an additional sanity check assert to the ldvary fixupIago Toral Quiroga1-0/+9
2021-03-10radv: check if dynamic line stipple state changedSamuel Pitoiset1-0/+4
2021-03-10radv: check if dynamic VRS state changedSamuel Pitoiset1-0/+6
2021-03-10radv: do not declare push constants for DCC decompress on computeSamuel Pitoiset1-2/+2
2021-03-09intel/blorp: Fix condition to figure out aux_addressSagar Ghuge1-1/+1
2021-03-09Revert "Revert "blorp/gen12: Don't use aux address if implicit CCS""Sagar Ghuge1-2/+7
2021-03-09Revert "blorp/gen12: Don't use aux address if implicit CCS"Mark Janes1-7/+2
2021-03-09freedreno/a5xx: Flush depth at the end of sysmem, like a6xx does.Eric Anholt1-0/+1
2021-03-09freedreno/a5xx: Introduce an event write helper like a6xx has.Eric Anholt4-43/+34
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