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AgeCommit message (Expand)AuthorFilesLines
2018-10-29swr/rast: fix intrinsic/function for LLVM 7 compatibilityAlok Hota6-14/+3
2018-10-29freedreno: don't flush when new and old pfb is identicalRob Clark1-0/+3
2018-10-29freedreno: fix inorder rendering caseRob Clark1-6/+7
2018-10-29anv: Flag semaphore BOs as externalJason Ekstrand1-2/+3
2018-10-29intel/blorp: Define the clear value bounds for HiZ clearsNanley Chery1-0/+14
2018-10-29anv: Fix sanitization of stencil state when the depth test is disabledAlex Smith1-7/+7
2018-10-29blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OPJason Ekstrand1-0/+9
2018-10-29spirv: Use the right bit-size for spec constant opsJason Ekstrand1-3/+9
2018-10-26util: Change remaining uint32 cache ids to sha1David McFarland5-93/+81
2018-10-26radv: Emit enqueued pipeline barriers on event write.Bas Nieuwenhuizen1-0/+2
2018-10-26swr/rast: ignore CreateElementUnorderedAtomicMemCpyAlok Hota1-1/+2
2018-10-25gallium: Correctly handle no config context creationElie Tournier3-2/+13
2018-10-23radv: s/abs/fabsf/ for floatsEric Engestrom1-4/+4
2018-10-22ac: Fix loading a dvec3 from an SSBOConnor Abbott1-2/+2
2018-10-22ac: Introduce ac_build_expand()Connor Abbott2-14/+29
2018-10-22loader/dri3: Also wait for front buffer fence if we triggered itMichel Dänzer1-2/+5
2018-10-22radeonsi: fix a VGT hang with primitive restart on Polaris10 and laterMarek Olšák1-2/+8
2018-10-22radeonsi: Bump number of allowed global buffers to 32Jan Vesely1-1/+1
2018-10-22radv: fix check for perftest options sizeAndres Rodriguez1-1/+1
2018-10-22ac/nir: Use context-specific LLVM typesAlex Smith1-2/+2
2018-10-15util: add drirc workarounds for RAGETimothy Arceri1-0/+8
2018-10-15util: better handle program names from wineTimothy Arceri1-5/+12
2018-10-15r600/sb: Fix constant-logical-operand warning.Vinson Lee1-1/+1
2018-10-15st/va: use provided sizes and coords for vlVaGetImageBoyuan Zhang1-3/+28
2018-10-15radv: add a workaround for a VGT hang with prim restart and stripsSamuel Pitoiset1-0/+11
2018-10-11util: use force_compat_profile for Wolfenstein The Old BloodTimothy Arceri1-0/+4
2018-10-11mesa/st: add force_compat_profile option to driconfigTimothy Arceri3-2/+14
2018-10-11r600: use build-id when available for disk cacheTimothy Arceri1-7/+7
2018-10-11nouveau: use build-id when available for disk cacheTimothy Arceri1-7/+7
2018-10-11radeonsi: use build-id when available for disk cacheTimothy Arceri1-12/+9
2018-10-11util: add disk_cache_get_function_identifier()Timothy Arceri1-0/+16
2018-10-11util: rename timestamp param in disk_cache_create()Timothy Arceri1-4/+4
2018-10-11util: disable cache if we have no build-id and timestamp is zeroTimothy Arceri2-4/+9
2018-10-11glsl: ignore trailing whitespace when define redefinedTimothy Arceri3-3/+25
2018-10-11anv: add missing unlock in error path.Dave Airlie1-0/+1
2018-10-11intel: Don't propagate conditional modifiers if a UD source is negatedJason Ekstrand5-0/+50
2018-10-10radv: add missing meson c++ visibility argumentsEric Engestrom1-0/+1
2018-10-10virgl, vtest: Correct the transfer size calculationGert Wollny1-1/+3
2018-10-10nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansionsJason Ekstrand1-15/+18
2018-10-10anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_STARTJason Ekstrand1-0/+9
2018-10-10Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"Emil Velikov1-2/+44
2018-10-10vl/dri3: do full teardown on screen_destroyEmil Velikov1-1/+0
2018-10-10i965: Replace checks for rb->Name with FlipY (v2)Fritz Koenig2-13/+11
2018-10-10nir/from_ssa: Don't rewrite derefs destinations to registersJason Ekstrand1-0/+6
2018-10-10intel/fs: Fix a typo in need_matching_subreg_offsetJason Ekstrand1-1/+1
2018-10-10nvc0: fix blitting red to srgb8_alphaIlia Mirkin1-0/+4
2018-10-10nv50,nvc0: guard against zero-size blitsIlia Mirkin2-0/+14
2018-10-10nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin1-4/+4
2018-10-10glsl: fix array assignments of a swizzled vectorIlia Mirkin1-3/+10
2018-10-10glsl: do not attempt assignment if operand type not parsed correctlyTapani Pälli1-0/+6
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