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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
AgeCommit message (Expand)AuthorFilesLines
2017-11-22CHROMIUM: i965: Fix corner cases of brw depth stencil workaroundHaixia Shi1-4/+4
2017-11-22CHROMIUM: i965: Return NULL if we don't have a miptreeStéphane Marchesin1-0/+2
2017-11-17i965: Upload invariant state once at the start of the batch on Gen4-5.Kenneth Graunke1-9/+0
2017-09-14i965: Use a separate state buffer, but avoid changing flushing behavior.Kenneth Graunke1-13/+13
2017-08-30i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin1-1/+2
2017-08-30i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin1-1/+1
2017-08-30i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin1-4/+4
2017-08-30i965: drop brw->gen in favor of devinfo->genLionel Landwerlin1-27/+36
2017-08-04i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson1-33/+18
2017-07-20i965: Drop redundant check for non-tiled depth bufferTopi Pohjolainen1-2/+1
2017-07-20i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen1-1/+1
2017-07-20i965/miptree: Switch to isl_surf::tilingTopi Pohjolainen1-4/+4
2017-07-18i965/gen4: Set tile offsets to zero after depth rebaseTopi Pohjolainen1-4/+6
2017-06-19i965/gen4: Add support for single layer in alignment workaroundTopi Pohjolainen1-2/+2
2017-06-18i965/gen4: Refactor depth/stencil rebaseTopi Pohjolainen1-180/+63
2017-06-18i965: Drop depth/stencil miptree pointers in alignment workaroundTopi Pohjolainen1-12/+3
2017-06-18i965/gen4: Simplify depth/stencil invalidate checkTopi Pohjolainen1-13/+3
2017-06-18i965/gen4: Remove redundant check for depth when rebasing stencilTopi Pohjolainen1-51/+12
2017-06-18i965/gen4: Remove non-existing stencil and hiz buffer setupTopi Pohjolainen1-115/+10
2017-06-17i965/gen4: Set depth offset when there is stencil attachment onlyTopi Pohjolainen1-0/+6
2017-06-14i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESSJason Ekstrand1-6/+12
2017-06-14i965: Flush around state base addressJason Ekstrand1-0/+32
2017-06-07i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand1-1/+22
2017-05-03i965: Port gen4+ state emitting code to genxml.Rafael Antognolli1-147/+0
2017-03-27i965: Delete tile resource mode codeAnuj Phogat1-2/+1
2017-03-16i965/gen8+: Do full stall when switching pipelineTopi Pohjolainen1-1/+2
2017-03-13i965: Move the back-end compiler to src/intel/compilerJason Ekstrand1-1/+1
2017-03-13i965: split EU defines to brw_eu_defines.hEmil Velikov1-0/+1
2017-03-06i965: Delete vestiges of resource streamer code.Kenneth Graunke1-40/+0
2017-01-27i965/gen6: Simplify hiz surface setupTopi Pohjolainen1-3/+2
2017-01-27i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen1-16/+2
2016-10-31i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_stateNanley Chery1-31/+10
2016-10-27i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offsetJason Ekstrand1-4/+2
2016-08-17i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand1-3/+3
2016-07-07i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez1-9/+0
2016-05-25i965: Assert that a depth_mt exists when using HiZ.Matt Turner1-0/+1
2016-05-16i965: Send the minimal number of STATE_BASE_ADDRESS packets.Kenneth Graunke1-9/+4
2016-05-16i965: Combine Gen4-7 and Gen8+ state base address emitters.Kenneth Graunke1-4/+42
2016-05-12i965: Drop BRW_NEW_BLORP from stipple and line parameter packets.Kenneth Graunke1-8/+4
2016-04-23i965/blorp: Do not trigger re-emission of base state addressTopi Pohjolainen1-1/+0
2016-04-23i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke1-7/+16
2016-02-08i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez1-1/+1
2016-01-14i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez1-0/+40
2016-01-14i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipe...Francisco Jerez1-0/+24
2016-01-14i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez1-0/+13
2016-01-14i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez1-0/+37
2016-01-14i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.Francisco Jerez1-0/+20
2015-10-05i965: add EXT_polygon_offset_clamp support to gen4/gen5Ilia Mirkin1-8/+0
2015-09-28i965: Use intel_get_tile_dims() to get tile masksAnuj Phogat1-7/+13
2015-08-24i965: Always re-emit the pipeline select during invariant state emissionChris Wilson1-1/+2
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