mesa/mesa - The Mesa 3D Graphics Library (mirrored from https://gitlab.freedesktop.org/mesa/mesa)

Age	Commit message (Expand)	Author	Files	Lines
2020-01-27	intel/genxml: Make SO_DECL::"Hole Flag" a Boolean	Jason Ekstrand	1	-1/+1
2020-01-09	genxml: Remove a non-existant HW bit	Jason Ekstrand	1	-1/+0
2019-10-23	intel/genxml: add RPSTAT register for core frequency	Lionel Landwerlin	1	-0/+5
2019-10-23	intel/genxml: add generic perf counters registers	Lionel Landwerlin	1	-0/+18
2019-04-29	intel/genxml: Update MI_ATOMIC genxml definition.	Rafael Antognolli	1	-5/+39
2019-04-09	genxml: sort xml files using new script	Lionel Landwerlin	1	-3633/+3625
2019-03-28	intel/genxml: Media instructions and structures for gen10	Toni Lönnberg	1	-24/+3284
2019-02-22	genxml: add missing field values for 3DSTATE_SF	Juan A. Suarez Romero	1	-1/+4
2019-01-22	genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTEN	Jason Ekstrand	1	-0/+32
2019-01-19	intel/genxml: add missing MI_PREDICATE compare operations	Lionel Landwerlin	1	-0/+2
2018-12-14	intel/genxml: Add register for object preemption.	Rafael Antognolli	1	-0/+8
2018-12-14	genxml: Consistently use a numeric "MOCS" field	Kenneth Graunke	1	-32/+21
2018-11-13	intel/genxml: Add engine definition to render engine instructions (gen10)	Toni Lönnberg	1	-113/+113
2018-09-07	intel/genxml: turn SLM Enable bit into boolean	Lionel Landwerlin	1	-1/+1
2018-06-18	intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.	Rafael Antognolli	1	-0/+4
2018-05-07	intel/genxml: Fix some more fake booleans in genxml.	Kenneth Graunke	1	-2/+2
2018-04-05	intel/genxml: Add Clear Color struct to gen10+.	Rafael Antognolli	1	-0/+8
2018-04-05	intel/genxml: Use a single field for clear color address on gen10.	Rafael Antognolli	1	-4/+3
2018-04-03	intel: genxml: decode variable length MI_LRI	Lionel Landwerlin	1	-0/+4
2018-04-03	intel: genxml: add preemption control instructions	Lionel Landwerlin	1	-0/+7
2018-03-26	intel/genxml: Add SAMPLER_INSTDONE register.	Rafael Antognolli	1	-0/+23
2018-03-26	intel/genxml: Add ROW_INSTDONE register.	Rafael Antognolli	1	-0/+18
2018-03-26	intel/genxml: Add SC_INSTDONE register.	Rafael Antognolli	1	-0/+27
2018-03-20	intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers	Lionel Landwerlin	1	-0/+6
2018-03-05	intel: Drop SURFACE_FORMAT enum from genxml.	Kenneth Graunke	1	-227/+2
2018-01-09	genxml: Add missing INSTDONE_1 bits on Gen7.5+.	Kenneth Graunke	1	-0/+2
2017-11-14	intel/genxml: Add Cache Mode SubSlice Register to gen10.xml	Anuj Phogat	1	-0/+12
2017-08-15	intel/genxml: Fix gen10 BLEND_STATE variable length packing	Scott D Phillips	1	-2/+2
2017-07-02	intel: genxml: make a couple of enums show up in aubinator	Lionel Landwerlin	1	-7/+7
2017-06-22	intel/genxml: Add Gen10 CACHE_MODE_1 definitions	Anuj Phogat	1	-0/+18
2017-06-22	intel/genxml: Rename StartInstanceLocation to StartingInstanceLocation	Anuj Phogat	1	-1/+1
2017-06-22	intel/genxml: Rename IndirectStatePointer to BorderColorPointer	Anuj Phogat	1	-1/+1
2017-06-22	intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData field	Anuj Phogat	1	-2/+1
2017-06-22	intel/genxml: Add INSTDONE registers in gen10	Anuj Phogat	1	-0/+115
2017-06-22	intel/genxml: Add better support for MI_MATH in gen10	Anuj Phogat	1	-4/+65
2017-06-09	i965/genxml: Add gen10.xml	Jason Ekstrand	1	-0/+3562