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2021-06-22nir: use a more fitting index for btd_stack_push_intelLionel Landwerlin1-1/+1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
2021-06-22nir: drop the btd_resume_intel intrinsicLionel Landwerlin1-2/+0
This is now 100% equivalent to the new rt_resume intrinsic. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
2021-06-22spirv: Create acceleration structure and shader record variablesJason Ekstrand1-5/+2
spirv_to_nir now requires NIR variables to be created for everything. Fixes: 10b3eecd361af "spirv: Don't remove variables used by resource..." Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
2021-06-22spirv_to_nir: Add environment variable to change default log levelCharlie Turner2-1/+35
During dEQP runs for radv, I see a lot of warnings like, ERROR - dEQP error: SPIR-V WARNING: ERROR - dEQP error: In file ../src/compiler/spirv/spirv_to_nir.c:1073 ERROR - dEQP error: Decoration not allowed on struct members: SpvDecorationRestrict ERROR - dEQP error: 408 bytes into the SPIR-V binary This fails jobs on Gitlab, due to, Job's log exceeded limit of 4194304 bytes. Job execution will continue but no more output will be collected. Since it doesn't seem feasible right now to fix the many shaders in the VK-CTS triggering this warning, add an environment toggle that allows test runners to only see the level of commentary they want. v2 from Martin: - Add my SoB v3 from Martin: - fix the indentation (suggested by Eric) - put the declarations at the top of the function v4 from Martin: - make vtn_default_log_level() static (Marcin) - cache the default level in vtn_log (Marcin) - move vtn_log_level_strings inside vtn_default_log_level() - Fix the build issue on MSC Signed-off-by: Martin Peres <martin.peres@mupuf.org> Reviewed-by: Eric Engestrom <eric@engestrom.ch> Acked-by: Andres Gomez <agomez@igalia.com> Acked-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11491>
2021-06-21nir: Add raytracing shader call lowering pass.Bas Nieuwenhuizen4-0/+1131
Really copying Jason's pass. Changes: - Instead of all the intel lowering introduce rt_{execute_callable,trace_ray,resume} - Add the ability to use scratch intrinsics directly. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10339>
2021-06-21nir: Add lowered vendor independent raytracing intrinsics.Bas Nieuwenhuizen5-5/+42
For use in a generic nir_lower_shader_calls. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10339>
2021-06-21nir,docs: Add docs for NIR ALU instructionsJason Ekstrand1-12/+44
About half or more of the text here is actually from Connor Abbot. I've edited it a bit to bring it up-to-date and make a few things more clear. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
2021-06-21nir: Require vectorized ALU ops to be all-or-nothingJason Ekstrand1-0/+2
Long ago, the semantics of bcsel were such that it took a single boolean value and selected between whole vectors. These days, it takes a vector boolean with the assumption that if you want the old behavior you can just use a .xxxx swizzle. There currently are no opcodes which use a output_size of 0 but have a scalar or fixed-vector input. Let's disallow it for now to force us to think through the semantics again if this ever comes up as something someone actually wants. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
2021-06-21nir/propagate_invariant: add invariant_prim optionRhys Perry2-2/+26
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11035>
2021-06-21nir,vc4: Suffix a bunch of unorm 4x8 opcodes _vc4Jason Ekstrand2-51/+53
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
2021-06-21nir,panfrost: Suffix fsat_signed and fclamp_pos with _maliJason Ekstrand1-2/+4
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
2021-06-21nir,amd: Suffix nir_op_cube_face_coord/index with _amdJason Ekstrand3-6/+6
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
2021-06-18nir: Add an interface for logging shaders with mesa_log*.Emma Anholt2-2/+23
For debug on Android, it's useful to be able to print shaders to the android log interface, since you don't usually have stdout/stderr. Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18nir: Do peephole select on other instructions if the limit is ~0.Eric Anholt1-3/+31
limit==0 is the signal for "don't peephole anything but a move that will be optimized aways." limit > 0 is "up to N alu instructions may be moved out." nir-to-tgsi uses ~0 as the indicator of "No, we really need to eliminate all if instructions" on hardware like i915 that doesn't have control flow. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18nir/lower_int_to_float: Make sure the cursor is in the right spot.Emma Anholt1-0/+2
We need to make get it updated after we may have nir_instr_remove()d an instruction, and when we cross blocks. This didn't really matter before because the only builder usage was idiv, which other users of lower_int_to_float were probably never hitting. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-17spirv: Fix handling of OpBranchConditional with same THEN and ELSECaio Marcelo de Oliveira Filho2-23/+23
When an OpBranchConditional that had two equal branches was parsed, we were treating it as a regular OpBranch. However this doesn't work well when there's an associated OpSelectionMerge. We ended up skipping marking the merge block as such, and depending on what was inside the construct we would end up trying to process the block twice. Fix this by keeping the vtn_if around, but when emitting NIR identify the two equal branch case. Fixes: 9c2a11430e1 ("spirv: Rewrite CFG construction") Closes: #3786, #4580 Reviewed-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9297>
2021-06-17intel/nir: Fix txs for null surfacesIván Briano1-3/+7
Closes: #4860 Fixes: 05a37e24220 ("intel/nir: Set lower txs with non-zero LOD") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11435>
2021-06-16compiler/glsl: Use mutex lock while freeing up mem_ctxMartin Krastev1-1/+10
builtin_builder::~builtin_builder() and builtin_builder::release() are running into race condition. This leads lightsmark to crash at the end because both calls ralloc_free which mutates the arguments state This patch fixes lightsmark2008 crash Fixes: e4da8b9c331cc3a ("mesa/compiler: rework tear down of builtin/types") Reviewed-by: Charmaine Lee <charmainel@vmware.com> Reviewed-by: Neha Bhende <bhenden@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Neha Bhende <bhenden@vmware.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11385>
2021-06-16shader_enums: change VERT_BIT back to the 32-bit shiftMarek Olšák1-1/+1
This reverts 0e2566a8. The warning is fixed differently. Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10993>
2021-06-15nir/cse: resize the instruction setRhys Perry1-0/+2
ministat (CSE only): Difference at 95.0% confidence -3357.54 +/- 32.5177 -25.267% +/- 0.24098% (Student's t, pooled s = 33.909) ministat (entire run): Difference at 95.0% confidence -3414.27 +/- 270.628 -2.76477% +/- 0.217647% (Student's t, pooled s = 282.207) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6390>
2021-06-15nir: use a single set during CSERhys Perry4-36/+32
Use a single set and ensure dominance by checking after a equivalent instruction is found. Besides removing the need to copy a set, this also lets us resize the set at the start of the pass in the next commit. ministat (CSE only): Difference at 95.0% confidence -984.956 +/- 28.8559 -6.90075% +/- 0.190231% (Student's t, pooled s = 26.9052) ministat (entire run): Difference at 95.0% confidence -1246.1 +/- 257.253 -0.998972% +/- 0.205094% (Student's t, pooled s = 239.863) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Co-authored-by: Daniel Schürmann <daniel@schuermann.dev> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6390>
2021-06-11i965: Use nir_lower_passthrough_edgeflagsJason Ekstrand1-2/+5
Now that there's a common NIR pass, there's no point in us doing this in the back-end anymore. In order to use this pass in i965, we do have to make one tiny change. Gallium runs the pass after assigning input and output locations and so needs the pass to respect those locations and num_inputs. i965, however, runs it before any location assignment or I/O lowering so we don't care. We do, however, need the pass to succeed with num_inputs == 0 because we set that later. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11313>
2021-06-11nir/edgeflags: update outputs written when lowering edge flags.Dave Airlie1-1/+2
In theory you can rerun the info gather pass, but in practice that doesn't always end well. Be consistent inside this pass and update the info. While we're here, change the inputs read to use VERT_BIT_EDGEFLAG. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11313>
2021-06-10nir: document that ACCESS_RESTRICT is not set at intrinsicsRhys Perry1-1/+2
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
2021-06-10nir/opt_load_store_vectorize: only require one variable to be restrictRhys Perry1-2/+2
No fossil-db changes. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
2021-06-10nir/opt_load_store_vectorize: check for restrict at the variableRhys Perry1-23/+40
SPIR-V -> NIR doesn't set ACCESS_RESTRICT at the intrinsic. fossil-db (GFX10.3): Totals from 3 (0.00% of 139391) affected shaders: CodeSize: 12364 -> 12356 (-0.06%) Instrs: 2493 -> 2494 (+0.04%); split: -0.04%, +0.08% Cycles: 15279372 -> 15295756 (+0.11%); split: -0.11%, +0.21% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
2021-06-10nir/load_store_vectorizer: fix check_for_robustness() with indirect loadsRhys Perry2-11/+132
fossil-db (GFX10.3, robustness2 enabled): Totals from 13958 (9.54% of 146267) affected shaders: VGPRs: 609168 -> 624304 (+2.48%); split: -0.05%, +2.53% CodeSize: 48229504 -> 48488392 (+0.54%); split: -0.02%, +0.56% MaxWaves: 354426 -> 349448 (-1.40%); split: +0.00%, -1.41% Instrs: 9332093 -> 9375053 (+0.46%); split: -0.03%, +0.49% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
2021-06-09amd: Add extra source to the mbcnt_amd NIR intrinsic.Timur Kristóf3-2/+17
The v_mbcnt instructions can take an extra source that they add to the result. This is not exposed in SPIR-V but we now expose it in NIR. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
2021-06-09nir: Add AMD-specific byte and lane permute intrinsics.Timur Kristóf2-0/+6
These map directly to v_perm_b32 and v_permlane_b32. Unfortunately there is no corresponding NIR opcode or intrinsics, and it's too tedious to puzzle these things together from the existing NIR instructions. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
2021-06-09nir: Add nir_op_sad_u8x4 which corresponds to AMD's v_sad_u8.Timur Kristóf2-0/+21
NIR currently doesn't have any intrinsics for a horizontal packed add, so this one is modeled after AMD's v_sad_u8. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
2021-06-09nir/gather_info: Rename per_vertex to is_arrayedCaio Marcelo de Oliveira Filho1-7/+7
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
2021-06-09nir/lower_io: Rename vertex_index to array_index in helpersCaio Marcelo de Oliveira Filho2-43/+43
The helpers will be reused for per-primitive variables that are also arrayed, so use a more general name. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
2021-06-09nir/lower_fragcolor: Avoid redundant load_outputAlyssa Rosenzweig1-1/+2
At best, this is an extra instruction for NIR to optimize out. At worst, depending on pass ordering nir_load_output could sneak into the final NIR, even on drivers that don't support fbfetch. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
2021-06-08nir: Move workgroup_size and workgroup_variable_size into common shader_infoCaio Marcelo de Oliveira Filho10-63/+81
Move it out the "cs" sub-struct, since these will be used for other shader stages in the future. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
2021-06-08nir: Move zero_initialize_shared_memory into common shader_infoCaio Marcelo de Oliveira Filho2-3/+6
Move it out the "cs" sub-struct, since the bit will be used for other shader stages in the future. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
2021-06-08nir/lower_returns: Deal with single-arg phis after if.Bas Nieuwenhuizen1-0/+10
if we have if ... { return; } else { // block X } // block Y phi(X: ...) then nir_lower_returns tries to move block Y into the else body, except nir_cf_extract doesn't move the phi. As the return is removed in the then-body the phi suddenly has the wrong number of arguments (and the phi doesn't dominate its uses anymore). In this case we know that the phi has to be single arg, so we can just rewrite the users of the phis and drop them. Hit this in my RT adventures, not sure if this is actually reachable right now, as single arg phis tend to be kind of exceptional outside of CSSA and we typically call nir_lower_returns pretty early. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11207>
2021-06-08nir, nir/algebraic: add byte/word insertion instructionsRhys Perry3-0/+19
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
2021-06-08nir/algebraic: optimize extract of extractRhys Perry1-0/+6
Found in some sottr shaders (originally iand(ishr(a, 16), 0xffff)) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3151>
2021-06-07nir: Rename WORK_GROUP (and similar) to WORKGROUPCaio Marcelo de Oliveira Filho13-61/+61
Be consistent with other usages in Vulkan and SPIR-V, and the recently added workgroup_size field. Acked-by: Emma Anholt <emma@anholt.net> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
2021-06-07nir: Rename nir_intrinsic_load_local_group_size to ↵Caio Marcelo de Oliveira Filho5-12/+12
nir_intrinsic_load_workgroup_size Acked-by: Emma Anholt <emma@anholt.net> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
2021-06-07compiler: Rename SYSTEM_VALUE_LOCAL_GROUP_SIZE to SYSTEM_VALUE_WORKGROUP_SIZECaio Marcelo de Oliveira Filho6-7/+7
Acked-by: Emma Anholt <emma@anholt.net> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
2021-06-07compiler: Rename local_size to workgroup_sizeCaio Marcelo de Oliveira Filho9-71/+71
Acked-by: Emma Anholt <emma@anholt.net> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
2021-06-05nir: Add nir_intrinsic_load_back_face_agxAlyssa Rosenzweig1-0/+3
On AGX, the special register for front facing is inverted from its meaning in APIs. We need to lower load_front_face to inot(load_back_face). Doing this in the backend is trivial, but then we would miss out on algebraic optimizations for the inot. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
2021-06-04nir: define NIR_ALU_MAX_INPUTSHoe Hao Cheng1-2/+7
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11172>
2021-06-04nir/unsigned_upper_bound: don't require dominance metadataRhys Perry2-11/+2
Instead, determine if it's a merge or loop exit phi. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9808>
2021-05-31compiler/spirv: expand_to_vec4 -> nir_pad_vec4Mike Blumenkrantz1-20/+3
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10821>
2021-05-26nir/builder: add nir_maskMike Blumenkrantz1-0/+8
it's handy to have functions for generating masks Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10620>
2021-05-21nir/lower_io_to_vector: fix per vertex io handling for arraysTimothy Arceri1-8/+19
The pass was processing the per vertex index from the wrong end of the array deref chain. Fixes: bcd14756eec8 ("nir/lower_io_to_vector: add flat mode") Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10798>
2021-05-21nir/lower_tex: Add support for lowering YUYV formatsIan Romanick2-0/+24
v2: Rebase on bc438c91d9b ("nir/lower_tex: ignore texture_index if tex_instr has deref src") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
2021-05-21nir/lower_tex: Add support for lowering Y41x formatsIan Romanick2-0/+24
These are similar to AYUV, but the channel ordering is different... in such a way that there's no RGBA format that will make the channels line up right. v2: Rebase on bc438c91d9b ("nir/lower_tex: ignore texture_index if tex_instr has deref src") Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
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