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2017-01-25Update version to 17.0.0-rc2mesa-17.0.0-rc2Emil Velikov1-1/+1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-24i965/blorp: Make post draw flush more explicitTopi Pohjolainen2-5/+22
Blits do not need any special treatment as the target buffer object is added to render cache just as one does for normal draw. Color clears and resolves in turn require explicit "end of pipe synchronization". It is not clear what this means exactly but the assumption is that render cache flush with command stream stall should be sufficient. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 180653c357d19ca88f7895f59874a58fac99cc53)
2017-01-24i965/gen6: Issue direct depth stall and flush after depth clearTopi Pohjolainen1-1/+6
instead of calling unconditionally brw_emit_mi_flush() which does: brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 46b346899d98e29943f8cd74c25bcb8d2f868a49)
2017-01-24i965: Make depth clear flushing more explicitTopi Pohjolainen2-8/+57
Current blorp logic issues unconditional "flush everything" (see brw_emit_mi_flush()) after each render. For example, all blits issue this unconditionally which shouldn't be needed if they set render cache properly so that subsequent renders do necessary flushing before drawing. In case of piglit: ext_framebuffer_multisample-accuracy all_samples depth_draw small intel_hiz_exec() is always preceded by blorb blit and the unconditional flush looks to hide the lack of stall and flushes in depth clears. By removing the brw_emit_mi_flush() I get gpu hangs. This patch adds the stalls and flushes mandated by the spec and gets rid of those hangs. v2 (Jason, Ken): Document the rational for separating depth cache flush and stall on Gen7. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit e6da6943fed1228c551af1f0e1a405b6d67b41ae)
2017-01-24i965/blorp: Use the render cache mechanism instead of explicit flushingTopi Pohjolainen1-1/+7
by replacing brw_emit_mi_flush() with brw_render_cache_set_check_flush(). The latter splits the flush in two: brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); instead of int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL; } brw_emit_pipe_control_flush(brw, flags); v2 (Jason): Check that destination exists before trying to add to render cache. Depth clears and resolves don't have it. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 4840a53e902b0f2b9841d9dbb90e479a3688153d)
2017-01-24radeonsi: always set the TCL1_ACTION_ENA when invalidating L2Marek Olšák1-1/+2
Some CIK-VI docs say this is the default behavior on SI. That doesn't answer whether it's also the default behavior on CIK-VI. Cc: 17.0 13.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 573bf0940a08e18a511e338de478f30fd95a1590)
2017-01-24radv: don't resubmit the same cs over and over while tracingGrazvydas Ignotas1-2/+1
Fixes: 97dfff54 ("radv: Dump command buffer on hang.") Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> CC: <mesa-stable@lists.freedesktop.org> (cherry picked from commit f65b3641c3233f1697b96ea8126b578dae6de4f1)
2017-01-24swr: Align query results allocationGeorge Kyriazis2-4/+5
Some query results struct contents are declared as cache line aligned. Use aligned malloc, and align the whole struct, to be safe. Fixes crash when compiling with clang. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> (cherry picked from commit 00847e4f14dd237dfcdb2c3d15be1325a08ccf5a)
2017-01-24swr: Prune empty nodes in CalculateProcessorTopology.Bruce Cherniak1-0/+9
CalculateProcessorTopology tries to figure out system topology by parsing /proc/cpuinfo to determine the number of threads, cores, and NUMA nodes. There are some architectures where the "physical id" begins with 1 rather than 0, which was creating and empty "0" node and causing a crash in CreateThreadPool. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97102 Reviewed-By: George Kyriazis <george.kyriazis@intel.com> CC: <mesa-stable@lists.freedesktop.org> (cherry picked from commit b829206b0739925501bcc68233437d6d03b79795)
2017-01-24st/glsl_to_tgsi: use DDIV instead of DRCP + DMULNicolai Hähnle1-6/+3
Fixes GL45-CTS.gpu_shader_fp64.built_in_functions. v2: use DDIV unconditionally (Roland) Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Tested-by: Glenn Kennard <glenn.kennard@gmail.com> Tested-by: James Harvey <lothmordor@gmail.com> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit cfabbbcfd778cc404813c9f05a9ef79efe531980)
2017-01-24glsl: split DIV_TO_MUL_RCP into single- and double-precision flagsNicolai Hähnle2-9/+14
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Tested-by: Glenn Kennard <glenn.kennard@gmail.com> Tested-by: James Harvey <lothmordor@gmail.com> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit b71c415c3d288da4b5f533ece42f50f4f20a8c33)
2017-01-24r600: implement DDIVNicolai Hähnle1-0/+59
Tested-by: Glenn Kennard <glenn.kennard@gmail.com> Tested-by: James Harvey <lothmordor@gmail.com> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit e4f8f9a638c1ffb9b76840b088290f11f0f91813)
2017-01-24r600: factor out cayman_emit_unary_double_rawNicolai Hähnle1-20/+42
We will use it for DDIV. Tested-by: Glenn Kennard <glenn.kennard@gmail.com> Tested-by: James Harvey <lothmordor@gmail.com> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 488560cfe6ee2206f7a7f894694ebc43b419be61)
2017-01-24r600: double multiply can handle only one multiply at a timeNicolai Hähnle1-17/+19
It seems clear that trying to multiply two pairs of doubles would result in the temporary register getting overwritten by the second pair. So make the code more explicit. Tested-by: Glenn Kennard <glenn.kennard@gmail.com> Tested-by: James Harvey <lothmordor@gmail.com> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 76b02d2fe1df5351f67f53d07b37952043f0a84c)
2017-01-24freedreno/a5xx: set frag shader threadsizeRob Clark1-2/+7
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 31daeb5bf14334bc0d39f28c9102cd15d834abfc)
2017-01-24freedreno/a5xx: set fragcoordxy properlyRob Clark1-1/+1
What a3xx docs call IJPERSPCENTERREGID.. the xy coord passed into bary.f. We were incorrectly setting both this and gl_FragCoord.xy to the same register resulting in all sorts of hilarity. Fixes stk, vdrift, 0ad, probably a bunch others. Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 8d6af93e76bb9e592293b632b22b2b756cc0cae8)
2017-01-24freedreno/a5xx: fix psizeRob Clark2-8/+5
Note spritelist (POINTLIST_PSIZE) seems not to be a thing anymore on a5xx. Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6cc93bedc15d09395ab6a92a0a129d06a8cd8ae8)
2017-01-24freedreno/a5xx: srgb fixRob Clark1-1/+2
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 141a4f86d6b9c0c4dbde511b741576a103f8f7ff)
2017-01-24freedreno/a5xx: fix int vbosRob Clark1-1/+3
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 69fbb458cf59fbab5f6675ad256a266b04d54700)
2017-01-24freedreno/a5xx: fix clear for uint/sint formatsRob Clark1-19/+28
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 16671e970444f154ffa60d2aaadee4d065eb6103)
2017-01-24freedreno/a5xx: fix cull stateRob Clark1-5/+5
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4d9aa4f67d6316feea93901bf29b76a68c4333cd)
2017-01-24freedreno: update generated headersRob Clark6-13/+36
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4c39458460075f6c1ea9e4607769513b96c6dd82)
2017-01-24nir/search: Use the correct bit size for integer comparisonsJason Ekstrand1-32/+16
The previous code always compared integers as 64-bit. Due to variations in sign-extension in the code generated by nir_opt_algebraic.py, this meant that nir_search doesn't always do what you want. Instead, 32-bit values should be matched as 32-bit and 64-bit values should be matched as 64-bit. While we're here we unify the unsigned and signed paths. Now that we're using the right bit size, they should be the same since the only difference we had before was sign extension. This gets the UE4 bitfield_extract optimization working again. It had stopped working due to the constant 0xff00ff00 getting sign-extended when it shouldn't have. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Eric Anholt <eric@anholt.net> Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit bb96b034616d9d099752efb005b5c05e8644059c)
2017-01-24intel/blorp/copy: Properly handle clear colors for CCS_E imagesJason Ekstrand1-0/+82
In order to handle CCS_E, we stomp the image format to a UINT format and then do some bitcasting logic in the shader. This works fine since SKL render compression only considers the channel layout of the format and not the format itself. In order for this to work on images that have been fast-cleared, we need to also convert the clear color so that, when interpreted as UINT, it provides the same bit value as it would have in the original format. This fixes a bunch of OpenGL ES CTS tests for copy_image when we start using CCS more aggressively. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 817f9e3b17c784cbe40639a4b370edc762bd2513)
2017-01-20radv: fix include order for installed headers v2Andres Rodriguez1-4/+4
In situations where libdrm_amdgpu and mesa are installed to the same location, the mesa installed headers will take precedence over the git source headers. This is due to the AMDGPU_CFLAGS containing the install directory. This situation can cause build errors if the git version of a header is newer than the currently installed version of a header (e.g. git pull updates vulkan.h) Note: using the same install prefix for mesa and libdrm is probably a common occurrence since it is described in the radeonBuildHowTo wiki: https://www.x.org/wiki/radeonBuildHowTo/ v2: added sign-off Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit a3ad6a34c6ba222ec93a2cfd0cac205c62574eb7)
2017-01-20vulkan/wsi: clarify the severity of lack of DRI3 v2Andres Rodriguez1-2/+4
The current message sounds like a small warning, clarify that it can result in lack of presentation support and application crashes. v2: add "if they do" (Bas) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98263 Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Acked-by: Jason ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit e0674e740bf84085dec898ffd87bdeb2027e620f)
2017-01-20anv: don't require render target isl bit for depth/stencil surfacesLionel Landwerlin1-2/+5
Blorp can deal with depth/stencil surfaces blits/copies without the render target requirement. Also having both render target and depth/stencil requirement is incompatible from isl's point of view. This fixes an image creation issue in the high level quality settings of the Unity3D player, which requires a depth texture with src/dst transfer & 4x multisampling. v2: Simply aspect checking condition (Jason) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 74c23bde5b8155a84233265c56bedac8f38de14e)
2017-01-20spirv: don't assert with location decorations on non i/o variablesLionel Landwerlin1-1/+2
Some applications might add location decoration to samplers. Rather than raising an error it seems it would make more sense to just discard these decorations. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: 17.0 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 8a28e764d0e28d0d4dfa3b81b89fa3baf30e94f2)
2017-01-20gallium/hud: add missing break in hud_cpufreq_graph_install()Samuel Pitoiset1-0/+1
Fixes: e99b9395bef "gallium/hud: Add support for CPU frequency monitoring" Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (cherry picked from commit 383fc8e9f340e80695aca2cd585957af0e081eb9)
2017-01-20radeonsi: don't forget to add HTILE to the buffer list for texturingMarek Olšák1-6/+13
This fixes VM faults. Discovered by Samuel Pitoiset. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98975 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99450 Cc: 17.0 13.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> (cherry picked from commit e490b7812cae778c61004971d86dc8299b6cd240)
2017-01-20radeonsi: fix texture gather on stencil texturesNicolai Hähnle1-2/+16
At least on VI, texture gather doesn't work with a 24_8 data format, so use 8_8_8_8 and a modified swizzle instead. A bit of background: When creating a GL_STENCIL_INDEX8 texture, we select the X24S8 pipe format because we don't support stencil-only render targets properly. With mip-mapping this can lead to a setup where the tiling is incompatible with stencil texturing, and a flushed stencil texture is used. For the flushed stencil, a literal X24S8 is used because there were issues with an 8bpp DB->CB copy. Longer term, it would be good if we could get away from these workarounds, i.e. properly support an S8 format for stencil-only rendering and flushed stencil. Since stencil texturing is somewhat rare, it's not a high priority. Fixes GL45-CTS.texture_cube_map_array.sampling. Cc: 17.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> (cherry picked from commit 3cd092c41508dde2e6259f09df1736911a828548)
2017-01-20radeonsi: Always leave poly_offset in a valid stateZachary Michaels1-1/+3
This commit makes si_update_poly_offset set poly_offset to NULL if uses_poly_offset is false. This way poly_offset either points into the currently queued rasterizer, or it is NULL. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99451 Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit d7d32b3bfe86bd89d94d59393907bce1cb9dab7c)
2017-01-20mesa/main: fix meta caller of _mesa_ClampColorNicolai Hähnle1-1/+2
Since _mesa_ClampColor properly checks for support of the API function now, it's meta callers need to check support as well. Fixes: 963311b71f ("mesa/main: fix version/extension checks in _mesa_ClampColor") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99401 Tested-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit a7c635ec6589f600f0d52d0097774ea0b938de9f)
2017-01-20gallivm: use #ifdef not #if for PIPE_ARCH_BIG_ENDIANDave Airlie1-1/+1
This fixes the build on ppc/s390. Reviewed-by: Roland Scheidegger <sroland@vmware.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit ef71b867ee152d8161a8c7320e89843801236249)
2017-01-18Update version to 17.0.0-rc1mesa-17.0.0-rc1Emil Velikov1-1/+1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-18utils: really remove the __END_DECLS macroEmil Velikov1-1/+0
Fixes: d1efa09d342 "util: import sha1 implementation from OpenBSD" Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit ea8b2624c8da1061e93124a760cae2ffb5f027ad)
2017-01-18utils: build sha1/disk cache only with Android/AutoconfEmil Velikov6-0/+58
Earlier commit imported a SHA1 implementation and relaxed the SHA1 and disk cache handling, broking the Windows builds. Restrict things for now until we get to a proper fix. Fixes: d1efa09d342 "util: import sha1 implementation from OpenBSD" Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 9f8dc3bf03ec825bae7041858dda6ca2e9a34363)
2017-01-18util: import sha1 implementation from OpenBSD17.0-branchpointEmil Velikov12-466/+290
At the moment we support 5+ different implementations each with varying amount of bugs - from thread safely problems [1], to outright broken implementation(s) [2] In order to accommodate these we have 150+ lines of configure script and extra two configure toggles. Whist an actual implementation being ~200loc and our current compat wrapping ~250. Let's not forget that different people use different code paths, thus effectively makes it harder to test and debug since the default implementation is automatically detected. To minimise all these lovely experiences, import the "100% Public Domain" OpenBSD sha1 implementation. Clearly document any changes needed to get building correctly, since many/most of those can be upstreamed making future syncs easier. As an added bonus this will avoid all the 'fun' experiences trying to integrate it with the Android and SCons builds. v2: Manually expand __BEGIN_DECLS/__END_DECLS and document (Tapani). Furthermore it seems that some games (or surrounding runtime) static link against OpenSSL resulting in conflicts. For more information see the discussion thread [3] Bugzilla [1]: https://bugs.freedesktop.org/show_bug.cgi?id=94904 Bugzilla [2]: https://bugs.freedesktop.org/show_bug.cgi?id=97967 [3] https://lists.freedesktop.org/archives/mesa-dev/2017-January/140748.html Cc: Mark Janes <mark.a.janes@intel.com> Cc: Vinson Lee <vlee@freedesktop.org> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Jonathan Gray <jsg@jsg.id.au> Tested-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Tapani Pälli <tapani.palli@intel.com> (v1) Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
2017-01-18i965: Make brw_cache_item structure private to brw_program_cache.c.Kenneth Graunke2-19/+21
struct brw_cache_item is an implementation detail of the program cache. We don't need to make those internals available to the entire driver. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-01-18radeonsi: determine in advance which VBOs should be added to the buffer listMarek Olšák3-4/+11
v2: now it should be correct Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: use fewer pointer dereferences in upload_vertex_buffer_descriptorsMarek Olšák1-8/+9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: reject invalid vertex buffer indices at state creationMarek Olšák2-5/+6
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: use a global dirty mask for shader pointersMarek Olšák4-41/+51
Only vertex buffers use a separate bool flag. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: use a bitmask-based loop in si_decompress_texturesMarek Olšák3-7/+31
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: skip an unnecessary mutex lock for L2 prefetchesMarek Olšák1-5/+7
the mutex lock is inside util_range_add. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: si_cp_dma_prepare is a no-op for L2 prefetchesMarek Olšák2-5/+12
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: add SI_CPDMA_SKIP_BO_LIST_UPDATEMarek Olšák2-10/+15
the next commit will use it in a clever way, because the CP DMA prefetch doesn't need this. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: use the correct target machine when building shader variantsMarek Olšák2-14/+29
If the shader selector is created with a different context than the shader variant, we should use the calling context's target machine for the shader variant. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99419 Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18radeonsi: move shader pipe context state into a separate structureMarek Olšák2-14/+22
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-18i965: Fix SURFACE_STATE to handle non-zero aux offsetsBen Widawsky1-2/+1
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Daniel Stone <daniels@collabora.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 15:29:59 +0000