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2017-01-25Update version to 17.0.0-rc2mesa-17.0.0-rc2Emil Velikov1-1/+1
2017-01-24i965/blorp: Make post draw flush more explicitTopi Pohjolainen2-5/+22
2017-01-24i965/gen6: Issue direct depth stall and flush after depth clearTopi Pohjolainen1-1/+6
2017-01-24i965: Make depth clear flushing more explicitTopi Pohjolainen2-8/+57
2017-01-24i965/blorp: Use the render cache mechanism instead of explicit flushingTopi Pohjolainen1-1/+7
2017-01-24radeonsi: always set the TCL1_ACTION_ENA when invalidating L2Marek Olšák1-1/+2
2017-01-24radv: don't resubmit the same cs over and over while tracingGrazvydas Ignotas1-2/+1
2017-01-24swr: Align query results allocationGeorge Kyriazis2-4/+5
2017-01-24swr: Prune empty nodes in CalculateProcessorTopology.Bruce Cherniak1-0/+9
2017-01-24st/glsl_to_tgsi: use DDIV instead of DRCP + DMULNicolai Hähnle1-6/+3
2017-01-24glsl: split DIV_TO_MUL_RCP into single- and double-precision flagsNicolai Hähnle2-9/+14
2017-01-24r600: implement DDIVNicolai Hähnle1-0/+59
2017-01-24r600: factor out cayman_emit_unary_double_rawNicolai Hähnle1-20/+42
2017-01-24r600: double multiply can handle only one multiply at a timeNicolai Hähnle1-17/+19
2017-01-24freedreno/a5xx: set frag shader threadsizeRob Clark1-2/+7
2017-01-24freedreno/a5xx: set fragcoordxy properlyRob Clark1-1/+1
2017-01-24freedreno/a5xx: fix psizeRob Clark2-8/+5
2017-01-24freedreno/a5xx: srgb fixRob Clark1-1/+2
2017-01-24freedreno/a5xx: fix int vbosRob Clark1-1/+3
2017-01-24freedreno/a5xx: fix clear for uint/sint formatsRob Clark1-19/+28
2017-01-24freedreno/a5xx: fix cull stateRob Clark1-5/+5
2017-01-24freedreno: update generated headersRob Clark6-13/+36
2017-01-24nir/search: Use the correct bit size for integer comparisonsJason Ekstrand1-32/+16
2017-01-24intel/blorp/copy: Properly handle clear colors for CCS_E imagesJason Ekstrand1-0/+82
2017-01-20radv: fix include order for installed headers v2Andres Rodriguez1-4/+4
2017-01-20vulkan/wsi: clarify the severity of lack of DRI3 v2Andres Rodriguez1-2/+4
2017-01-20anv: don't require render target isl bit for depth/stencil surfacesLionel Landwerlin1-2/+5
2017-01-20spirv: don't assert with location decorations on non i/o variablesLionel Landwerlin1-1/+2
2017-01-20gallium/hud: add missing break in hud_cpufreq_graph_install()Samuel Pitoiset1-0/+1
2017-01-20radeonsi: don't forget to add HTILE to the buffer list for texturingMarek Olšák1-6/+13
2017-01-20radeonsi: fix texture gather on stencil texturesNicolai Hähnle1-2/+16
2017-01-20radeonsi: Always leave poly_offset in a valid stateZachary Michaels1-1/+3
2017-01-20mesa/main: fix meta caller of _mesa_ClampColorNicolai Hähnle1-1/+2
2017-01-20gallivm: use #ifdef not #if for PIPE_ARCH_BIG_ENDIANDave Airlie1-1/+1
2017-01-18Update version to 17.0.0-rc1mesa-17.0.0-rc1Emil Velikov1-1/+1
2017-01-18utils: really remove the __END_DECLS macroEmil Velikov1-1/+0
2017-01-18utils: build sha1/disk cache only with Android/AutoconfEmil Velikov6-0/+58
2017-01-18util: import sha1 implementation from OpenBSD17.0-branchpointEmil Velikov12-466/+290
2017-01-18i965: Make brw_cache_item structure private to brw_program_cache.c.Kenneth Graunke2-19/+21
2017-01-18radeonsi: determine in advance which VBOs should be added to the buffer listMarek Olšák3-4/+11
2017-01-18radeonsi: use fewer pointer dereferences in upload_vertex_buffer_descriptorsMarek Olšák1-8/+9
2017-01-18radeonsi: reject invalid vertex buffer indices at state creationMarek Olšák2-5/+6
2017-01-18radeonsi: use a global dirty mask for shader pointersMarek Olšák4-41/+51
2017-01-18radeonsi: use a bitmask-based loop in si_decompress_texturesMarek Olšák3-7/+31
2017-01-18radeonsi: skip an unnecessary mutex lock for L2 prefetchesMarek Olšák1-5/+7
2017-01-18radeonsi: si_cp_dma_prepare is a no-op for L2 prefetchesMarek Olšák2-5/+12
2017-01-18radeonsi: add SI_CPDMA_SKIP_BO_LIST_UPDATEMarek Olšák2-10/+15
2017-01-18radeonsi: use the correct target machine when building shader variantsMarek Olšák2-14/+29
2017-01-18radeonsi: move shader pipe context state into a separate structureMarek Olšák2-14/+22
2017-01-18i965: Fix SURFACE_STATE to handle non-zero aux offsetsBen Widawsky1-2/+1
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