diff options
Diffstat (limited to 'src/intel/vulkan/anv_blorp.c')
| -rw-r--r-- | src/intel/vulkan/anv_blorp.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index e0498c698ff..7d234e3d052 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1789,11 +1789,18 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * * Set CS stall bit to guarantee that the fast clear starts the execution * after the tile cache flush completed. + * + * There is no Bspec requirement to flush the data cache but the + * experiment shows that flusing the data cache helps to resolve the + * corruption. */ + unsigned wa_flush = intel_device_info_is_dg2(cmd_buffer->device->info) ? + ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0; anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT | - ANV_PIPE_TILE_CACHE_FLUSH_BIT, + ANV_PIPE_TILE_CACHE_FLUSH_BIT | + wa_flush, "before clear hiz_ccs_wt"); } |