diff options
| author | Sagar Ghuge <sagar.ghuge@intel.com> | 2023-07-04 19:06:24 -0700 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2023-11-14 08:30:59 +0000 |
| commit | 648c0c159d865a8a30f0b524b33db6d932e4e234 (patch) | |
| tree | 061355cd7b87489b2d2353dfc34a92c79698a51d /src/intel/vulkan/anv_blorp.c | |
| parent | e4db19afa72b3dc2a33acc6435f714176adc6df1 (diff) | |
anv: Flush data cache while clearing depth using HIZ_CCS_WT
Patch fxes ESO shadow pass ground corruption on Arc A750. In the colour
pass where the rendering corruption first appears, the depth resource
was used as a "PS - Texture". Immediately afterwards there's a Barrier
where it goes from
VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL =>
VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
immediately following that there's a Clear from vkCmdBeginRendering
which appears to be a HiZ clear. Things work when using AUX_USAGE_HIZ
but AUX_USAGE_HIZ_CCS_WT (XXX: and AUX_USAGE_HIZ_CCS?) doesn't work.
current thinking is this is related to 14015264727 where we had to add
HDC and DC flushes to CCS and MCS fast clears. Maybe HiZ clears with
CCS also have similar problems? The docs don't appear to indicate that
but the docs were also wrong for color clears until recently...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9277
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9444
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22717>
Diffstat (limited to 'src/intel/vulkan/anv_blorp.c')
| -rw-r--r-- | src/intel/vulkan/anv_blorp.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index e0498c698ff..7d234e3d052 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1789,11 +1789,18 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * * Set CS stall bit to guarantee that the fast clear starts the execution * after the tile cache flush completed. + * + * There is no Bspec requirement to flush the data cache but the + * experiment shows that flusing the data cache helps to resolve the + * corruption. */ + unsigned wa_flush = intel_device_info_is_dg2(cmd_buffer->device->info) ? + ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0; anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT | - ANV_PIPE_TILE_CACHE_FLUSH_BIT, + ANV_PIPE_TILE_CACHE_FLUSH_BIT | + wa_flush, "before clear hiz_ccs_wt"); } |