diff options
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_viewport.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_viewport.c | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index 41432755c64..0327d2f5d15 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -103,8 +103,10 @@ static void si_emit_cull_state(struct si_context *sctx) /* This will end up in SGPR6 as (value << 8), shifted by the hw. */ radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf, RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER); + radeon_begin(&sctx->gfx_cs); radeon_set_sh_reg(&sctx->gfx_cs, R_00B220_SPI_SHADER_PGM_LO_GS, sctx->small_prim_cull_info_address >> 8); + radeon_end(); /* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling. * @@ -213,18 +215,22 @@ static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs if (scissor) si_clip_scissor(&final, scissor); + radeon_begin(cs); + /* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_- * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0. */ if (ctx->chip_class == GFX6 && (final.maxx == 0 || final.maxy == 0)) { radeon_emit(cs, S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(cs, S_028254_BR_X(1) | S_028254_BR_Y(1)); + radeon_end(); return; } radeon_emit(cs, S_028250_TL_X(final.minx) | S_028250_TL_Y(final.miny) | S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(cs, S_028254_BR_X(final.maxx) | S_028254_BR_Y(final.maxy)); + radeon_end(); } #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176 @@ -350,7 +356,7 @@ static void si_emit_guardband(struct si_context *ctx) * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ - unsigned initial_cdw = ctx->gfx_cs.current.cdw; + radeon_begin(&ctx->gfx_cs); radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, fui(guardband_y), fui(discard_y), fui(guardband_x), fui(discard_x)); @@ -362,8 +368,7 @@ static void si_emit_guardband(struct si_context *ctx) ctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL, S_028BE4_PIX_CENTER(rs->half_pixel_center) | S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH + vp_as_scissor.quant_mode)); - if (initial_cdw != ctx->gfx_cs.current.cdw) - ctx->context_roll = true; + radeon_end_update_context_roll(ctx); } static void si_emit_scissors(struct si_context *ctx) @@ -376,7 +381,10 @@ static void si_emit_scissors(struct si_context *ctx) if (!ctx->vs_writes_viewport_index) { struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0]; + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2); + radeon_end(); + si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL); return; } @@ -384,7 +392,10 @@ static void si_emit_scissors(struct si_context *ctx) /* All registers in the array need to be updated if any of them is changed. * This is a hardware requirement. */ + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, SI_MAX_VIEWPORTS * 2); + radeon_end(); + for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) { si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i], scissor_enabled ? &states[i] : NULL); @@ -477,12 +488,14 @@ static void si_emit_one_viewport(struct si_context *ctx, struct pipe_viewport_st { struct radeon_cmdbuf *cs = &ctx->gfx_cs; + radeon_begin(cs); radeon_emit(cs, fui(state->scale[0])); radeon_emit(cs, fui(state->translate[0])); radeon_emit(cs, fui(state->scale[1])); radeon_emit(cs, fui(state->translate[1])); radeon_emit(cs, fui(state->scale[2])); radeon_emit(cs, fui(state->translate[2])); + radeon_end(); } static void si_emit_viewports(struct si_context *ctx) @@ -492,7 +505,10 @@ static void si_emit_viewports(struct si_context *ctx) /* The simple case: Only 1 viewport is active. */ if (!ctx->vs_writes_viewport_index) { + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6); + radeon_end(); + si_emit_one_viewport(ctx, &states[0]); return; } @@ -500,7 +516,10 @@ static void si_emit_viewports(struct si_context *ctx) /* All registers in the array need to be updated if any of them is changed. * This is a hardware requirement. */ + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE + 0, SI_MAX_VIEWPORTS * 6); + radeon_end(); + for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) si_emit_one_viewport(ctx, &states[i]); } @@ -528,21 +547,25 @@ static void si_emit_depth_ranges(struct si_context *ctx) if (!ctx->vs_writes_viewport_index) { si_viewport_zmin_zmax(&states[0], clip_halfz, window_space, &zmin, &zmax); + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); radeon_emit(cs, fui(zmin)); radeon_emit(cs, fui(zmax)); + radeon_end(); return; } /* All registers in the array need to be updated if any of them is changed. * This is a hardware requirement. */ + radeon_begin(cs); radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, SI_MAX_VIEWPORTS * 2); for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) { si_viewport_zmin_zmax(&states[i], clip_halfz, window_space, &zmin, &zmax); radeon_emit(cs, fui(zmin)); radeon_emit(cs, fui(zmax)); } + radeon_end(); } static void si_emit_viewport_states(struct si_context *ctx) @@ -631,16 +654,20 @@ static void si_emit_window_rectangles(struct si_context *sctx) else rule = outside[num_rectangles - 1]; + radeon_begin(cs); radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE, rule); - if (num_rectangles == 0) + if (num_rectangles == 0) { + radeon_end(); return; + } radeon_set_context_reg_seq(cs, R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2); for (unsigned i = 0; i < num_rectangles; i++) { radeon_emit(cs, S_028210_TL_X(rects[i].minx) | S_028210_TL_Y(rects[i].miny)); radeon_emit(cs, S_028214_BR_X(rects[i].maxx) | S_028214_BR_Y(rects[i].maxy)); } + radeon_end(); } static void si_set_window_rectangles(struct pipe_context *ctx, bool include, |