diff options
Diffstat (limited to 'src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h')
| -rw-r--r-- | src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h | 105 |
1 files changed, 104 insertions, 1 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h index 5a253017089..99f6bbc932f 100644 --- a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h @@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository https://github.com/olvaffe/envytools/ git clone https://github.com/olvaffe/envytools.git -Copyright (C) 2014 by the following authors: +Copyright (C) 2014-2015 by the following authors: - Chia-I Wu <olvaffe@gmail.com> (olv) Permission is hereby granted, free of charge, to any person obtaining @@ -67,6 +67,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_OPCODE_CALLA 0x2b #define GEN6_OPCODE_CALL 0x2c #define GEN6_OPCODE_RETURN 0x2d +#define GEN8_OPCODE_GOTO 0x2e #define GEN6_OPCODE_WAIT 0x30 #define GEN6_OPCODE_SEND 0x31 #define GEN6_OPCODE_SENDC 0x32 @@ -160,6 +161,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_MATH_INT_DIV 0xb #define GEN6_MATH_INT_DIV_QUOTIENT 0xc #define GEN6_MATH_INT_DIV_REMAINDER 0xd +#define GEN8_MATH_INVM 0xe +#define GEN8_MATH_RSQRTM 0xf #define GEN6_SFID_NULL 0x0 #define GEN6_SFID_SAMPLER 0x2 #define GEN6_SFID_GATEWAY 0x3 @@ -184,9 +187,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_TYPE_B 0x5 #define GEN7_TYPE_DF 0x6 #define GEN6_TYPE_F 0x7 +#define GEN8_TYPE_UQ 0x8 +#define GEN8_TYPE_Q 0x9 +#define GEN8_TYPE_HF 0xa #define GEN6_TYPE_UV_IMM 0x4 #define GEN6_TYPE_VF_IMM 0x5 #define GEN6_TYPE_V_IMM 0x6 +#define GEN8_TYPE_DF_IMM 0xa +#define GEN8_TYPE_HF_IMM 0xb #define GEN7_TYPE_F_3SRC 0x0 #define GEN7_TYPE_D_3SRC 0x1 #define GEN7_TYPE_UD_3SRC 0x2 @@ -227,6 +235,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INST_SATURATE (0x1 << 31) #define GEN6_INST_DEBUGCTRL (0x1 << 30) #define GEN6_INST_CMPTCTRL (0x1 << 29) +#define GEN8_INST_BRANCHCTRL (0x1 << 28) #define GEN6_INST_ACCWRCTRL (0x1 << 28) #define GEN6_INST_CONDMODIFIER__MASK 0x0f000000 #define GEN6_INST_CONDMODIFIER__SHIFT 24 @@ -247,6 +256,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INST_DEPCTRL__SHIFT 10 #define GEN6_INST_MASKCTRL__MASK 0x00000200 #define GEN6_INST_MASKCTRL__SHIFT 9 +#define GEN8_INST_NIBCTRL (0x1 << 11) +#define GEN8_INST_DEPCTRL__MASK 0x00000600 +#define GEN8_INST_DEPCTRL__SHIFT 9 #define GEN6_INST_ACCESSMODE__MASK 0x00000100 #define GEN6_INST_ACCESSMODE__SHIFT 8 #define GEN6_INST_OPCODE__MASK 0x0000007f @@ -263,12 +275,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INST_DST_ADDR_SUBREG__SHIFT 26 #define GEN6_INST_DST_ADDR_IMM__MASK 0x03ff0000 #define GEN6_INST_DST_ADDR_IMM__SHIFT 16 +#define GEN8_INST_DST_ADDR_SUBREG__MASK 0x1e000000 +#define GEN8_INST_DST_ADDR_SUBREG__SHIFT 25 +#define GEN8_INST_DST_ADDR_IMM__MASK 0x01ff0000 +#define GEN8_INST_DST_ADDR_IMM__SHIFT 16 #define GEN6_INST_DST_SUBREG_ALIGN16__MASK 0x00100000 #define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT 20 #define GEN6_INST_DST_SUBREG_ALIGN16__SHR 4 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK 0x03f00000 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR 4 +#define GEN8_INST_DST_ADDR_IMM_ALIGN16__MASK 0x01f00000 +#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20 +#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR 4 #define GEN6_INST_DST_WRITEMASK__MASK 0x000f0000 #define GEN6_INST_DST_WRITEMASK__SHIFT 16 #define GEN7_INST_NIBCTRL (0x1 << 15) @@ -284,10 +303,37 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INST_DST_TYPE__SHIFT 2 #define GEN6_INST_DST_FILE__MASK 0x00000003 #define GEN6_INST_DST_FILE__SHIFT 0 +#define GEN8_INST_DST_ADDR_IMM_BIT9__MASK 0x00008000 +#define GEN8_INST_DST_ADDR_IMM_BIT9__SHIFT 15 +#define GEN8_INST_DST_ADDR_IMM_BIT9__SHR 9 +#define GEN8_INST_SRC0_TYPE__MASK 0x00007800 +#define GEN8_INST_SRC0_TYPE__SHIFT 11 +#define GEN8_INST_SRC0_FILE__MASK 0x00000600 +#define GEN8_INST_SRC0_FILE__SHIFT 9 +#define GEN8_INST_DST_TYPE__MASK 0x000001e0 +#define GEN8_INST_DST_TYPE__SHIFT 5 +#define GEN8_INST_DST_FILE__MASK 0x00000018 +#define GEN8_INST_DST_FILE__SHIFT 3 +#define GEN8_INST_MASKCTRL__MASK 0x00000004 +#define GEN8_INST_MASKCTRL__SHIFT 2 +#define GEN8_INST_FLAG_REG__MASK 0x00000002 +#define GEN8_INST_FLAG_REG__SHIFT 1 +#define GEN8_INST_FLAG_SUBREG__MASK 0x00000001 +#define GEN8_INST_FLAG_SUBREG__SHIFT 0 #define GEN7_INST_FLAG_REG__MASK 0x04000000 #define GEN7_INST_FLAG_REG__SHIFT 26 #define GEN6_INST_FLAG_SUBREG__MASK 0x02000000 #define GEN6_INST_FLAG_SUBREG__SHIFT 25 +#define GEN8_INST_SRC0_ADDR_IMM_BIT9__MASK 0x80000000 +#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHIFT 31 +#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR 9 +#define GEN8_INST_SRC1_TYPE__MASK 0x78000000 +#define GEN8_INST_SRC1_TYPE__SHIFT 27 +#define GEN8_INST_SRC1_FILE__MASK 0x06000000 +#define GEN8_INST_SRC1_FILE__SHIFT 25 +#define GEN8_INST_SRC1_ADDR_IMM_BIT9__MASK 0x02000000 +#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHIFT 25 +#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR 9 #define GEN6_INST_SRC_VERTSTRIDE__MASK 0x01e00000 #define GEN6_INST_SRC_VERTSTRIDE__SHIFT 21 #define GEN6_INST_SRC_WIDTH__MASK 0x001c0000 @@ -310,12 +356,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INST_SRC_ADDR_SUBREG__SHIFT 10 #define GEN6_INST_SRC_ADDR_IMM__MASK 0x000003ff #define GEN6_INST_SRC_ADDR_IMM__SHIFT 0 +#define GEN8_INST_SRC_ADDR_SUBREG__MASK 0x00001e00 +#define GEN8_INST_SRC_ADDR_SUBREG__SHIFT 9 +#define GEN8_INST_SRC_ADDR_IMM__MASK 0x000001ff +#define GEN8_INST_SRC_ADDR_IMM__SHIFT 0 #define GEN6_INST_SRC_SUBREG_ALIGN16__MASK 0x00000010 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT 4 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHR 4 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000003f0 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR 4 +#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000001f0 +#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4 +#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR 4 #define GEN6_INST_SRC_SWIZZLE_Y__MASK 0x0000000c #define GEN6_INST_SRC_SWIZZLE_Y__SHIFT 2 #define GEN6_INST_SRC_SWIZZLE_X__MASK 0x00000003 @@ -343,6 +396,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_3SRC_FLAG_SUBREG__MASK 0x00000002 #define GEN6_3SRC_FLAG_SUBREG__SHIFT 1 #define GEN6_3SRC_DST_FILE_MRF (0x1 << 0) +#define GEN8_3SRC_DST_TYPE__MASK 0x0001c000 +#define GEN8_3SRC_DST_TYPE__SHIFT 14 +#define GEN8_3SRC_SRC_TYPE__MASK 0x00003800 +#define GEN8_3SRC_SRC_TYPE__SHIFT 11 +#define GEN8_3SRC_SRC2_NEGATE (0x1 << 10) +#define GEN8_3SRC_SRC2_ABSOLUTE (0x1 << 9) +#define GEN8_3SRC_SRC1_NEGATE (0x1 << 8) +#define GEN8_3SRC_SRC1_ABSOLUTE (0x1 << 7) +#define GEN8_3SRC_SRC0_NEGATE (0x1 << 6) +#define GEN8_3SRC_SRC0_ABSOLUTE (0x1 << 5) +#define GEN8_3SRC_MASKCTRL__MASK 0x00000004 +#define GEN8_3SRC_MASKCTRL__SHIFT 2 +#define GEN8_3SRC_FLAG_REG__MASK 0x00000002 +#define GEN8_3SRC_FLAG_REG__SHIFT 1 +#define GEN8_3SRC_FLAG_SUBREG__MASK 0x00000001 +#define GEN8_3SRC_FLAG_SUBREG__SHIFT 0 #define GEN6_3SRC_SRC_REG__MASK 0x000ff000 #define GEN6_3SRC_SRC_REG__SHIFT 12 #define GEN6_3SRC_SRC_SUBREG__MASK 0x00000e00 @@ -382,6 +451,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_COMPACT_DEBUGCTRL (0x1 << 7) #define GEN6_COMPACT_OPCODE__MASK 0x0000007f #define GEN6_COMPACT_OPCODE__SHIFT 0 +#define GEN8_COMPACT_3SRC_SRC2_REG__MASK 0xfe00000000000000ULL +#define GEN8_COMPACT_3SRC_SRC2_REG__SHIFT 57 +#define GEN8_COMPACT_3SRC_SRC2_REG__SHR 1 +#define GEN8_COMPACT_3SRC_SRC1_REG__MASK 0x01fc000000000000ULL +#define GEN8_COMPACT_3SRC_SRC1_REG__SHIFT 50 +#define GEN8_COMPACT_3SRC_SRC1_REG__SHR 1 +#define GEN8_COMPACT_3SRC_SRC0_REG__MASK 0x0003f80000000000ULL +#define GEN8_COMPACT_3SRC_SRC0_REG__SHIFT 43 +#define GEN8_COMPACT_3SRC_SRC0_REG__SHR 1 +#define GEN8_COMPACT_3SRC_SRC2_SUBREG__MASK 0x0000070000000000ULL +#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHIFT 40 +#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHR 2 +#define GEN8_COMPACT_3SRC_SRC1_SUBREG__MASK 0x000000e000000000ULL +#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHIFT 37 +#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHR 2 +#define GEN8_COMPACT_3SRC_SRC0_SUBREG__MASK 0x0000001c00000000ULL +#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHIFT 34 +#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHR 2 +#define GEN8_COMPACT_3SRC_SRC2_REPCTRL (0x1ULL << 33) +#define GEN8_COMPACT_3SRC_SRC1_REPCTRL (0x1ULL << 32) +#define GEN8_COMPACT_3SRC_SATURATE (0x1 << 31) +#define GEN8_COMPACT_3SRC_DEBUGCTRL (0x1 << 30) +#define GEN8_COMPACT_3SRC_CMPTCTRL (0x1 << 29) +#define GEN8_COMPACT_3SRC_SRC0_REPCTRL (0x1 << 28) +#define GEN8_COMPACT_3SRC_DST_REG__MASK 0x0007f000 +#define GEN8_COMPACT_3SRC_DST_REG__SHIFT 12 +#define GEN8_COMPACT_3SRC_SOURCE_INDEX__MASK 0x00000c00 +#define GEN8_COMPACT_3SRC_SOURCE_INDEX__SHIFT 10 +#define GEN8_COMPACT_3SRC_CONTROL_INDEX__MASK 0x00000300 +#define GEN8_COMPACT_3SRC_CONTROL_INDEX__SHIFT 8 +#define GEN8_COMPACT_3SRC_OPCODE__MASK 0x0000007f +#define GEN8_COMPACT_3SRC_OPCODE__SHIFT 0 @@ -400,4 +501,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + #endif /* GEN_EU_ISA_XML */ |