diff options
| author | Marcin Ślusarz <marcin.slusarz@intel.com> | 2020-07-24 20:13:00 +0200 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2020-08-05 22:23:21 +0200 |
| commit | d7158dcc12bb4ed0cae4998cdd6156b87e393077 (patch) | |
| tree | 5f9d3c94f3219ade91036ee43b08f2d9352e4e82 /src | |
| parent | 3af72354feef361980d0fb028e29d66f5525d8e0 (diff) | |
intel/vec4: fix out of bounds read
NIR_MAX_VEC_COMPONENTS was bumped from 4 to 16 in a8ec4082
(2019.03.09, merged 2019.12.21)
float[4] array was added in acd7796a
(2019.06.11, merged 2019.07.11)
Found by Coverity.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3014
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Fixes: a8ec4082a41 ("nir+vtn: vec8+vec16 support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6067>
(cherry picked from commit cb19fe24d361991104f8dcf54d1e807998766be1)
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/compiler/brw_vec4_nir.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 76446adcf54..b04b6a8e371 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -997,7 +997,7 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, case BRW_REGISTER_TYPE_F: { int first_comp = -1; - float f[4] = { 0.0f, 0.0f, 0.0f, 0.0f }; + float f[NIR_MAX_VEC_COMPONENTS] = { 0.0f }; bool is_scalar = true; for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) { |