diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2021-01-13 10:32:15 +0100 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-01-13 13:42:04 +0000 |
| commit | a4876f055c705a6ca4c083dbe54b9b181558c714 (patch) | |
| tree | 9a47829e3591fdc2546fb010242e6b0c0cd7b3d0 /src | |
| parent | 9f1fad94f9af42a09fa158080e63adede1d43c8e (diff) | |
ac/surface: store DCC mip info into the surface
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/common/ac_surface.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 8 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index fc29146d14a..49ec8f5685d 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1871,6 +1871,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ * - Flush TC L2 after rendering. */ for (unsigned i = 0; i < in->numMipLevels; i++) { + surf->u.gfx9.dcc_levels[i].offset = meta_mip_info[i].offset; + surf->u.gfx9.dcc_levels[i].size = meta_mip_info[i].sliceSize; + if (meta_mip_info[i].inMiptail) { /* GFX10 can only compress the first level * in the mip tail. diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 46400b29070..6590024ca07 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -149,6 +149,11 @@ struct gfx9_surf_meta_flags { unsigned max_compressed_block_size : 2; }; +struct gfx9_surf_level { + unsigned offset; + unsigned size; +}; + struct gfx9_surf_layout { struct gfx9_surf_flags surf; /* color or depth surface */ struct gfx9_surf_flags fmask; /* not added to surf_size */ @@ -194,6 +199,9 @@ struct gfx9_surf_layout { uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* Pitch of level in blocks, only valid for prt images. */ uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS]; + + /* DCC level info */ + struct gfx9_surf_level dcc_levels[RADEON_SURF_MAX_LEVELS]; }; struct radeon_surf { |