diff options
author | Emma Anholt <emma@anholt.net> | 2022-07-05 10:01:00 -0700 |
---|---|---|
committer | Marge Bot <emma+marge@anholt.net> | 2022-07-11 16:56:05 +0000 |
commit | 240a98297dc97f5f252b8cd9c30c6e727b93a1be (patch) | |
tree | dd03b09204a8d15100c2b9e5e39002591d59b791 /src | |
parent | 0e1fb2d9845a38f3152eb83155928aa85373bc0c (diff) |
freedreno: Rename the "SIZE" regs for interpolateAtOffset to "CENTERRHW"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
Diffstat (limited to 'src')
-rw-r--r-- | src/freedreno/registers/adreno/a5xx.xml | 2 | ||||
-rw-r--r-- | src/freedreno/registers/adreno/a6xx.xml | 9 | ||||
-rw-r--r-- | src/freedreno/vulkan/tu_pipeline.c | 4 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_program.c | 2 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_program.c | 4 |
5 files changed, 8 insertions, 13 deletions
diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml index 010f62e9d82..2ac5af5e48f 100644 --- a/src/freedreno/registers/adreno/a5xx.xml +++ b/src/freedreno/registers/adreno/a5xx.xml @@ -2638,7 +2638,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set <!-- SAMPLEID is loaded into a half-precision register: --> <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> - <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/> + <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> </reg32> <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG"> <!-- register loaded with position (bary.f) --> diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 40dfdbfd4a3..8af2dbce5a6 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -2000,7 +2000,7 @@ to upconvert to 32b float internally? <bitfield name="FACENESS" pos="2" type="boolean"/> <bitfield name="SAMPLEID" pos="3" type="boolean"/> <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> - <bitfield name="SIZE" pos="6" type="boolean"/> + <bitfield name="CENTERRHW" pos="6" type="boolean"/> <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> <bitfield name="FOVEATION" pos="8" type="boolean"/> </reg32> @@ -3554,12 +3554,7 @@ to upconvert to 32b float internally? <!-- SAMPLEID is loaded into a half-precision register: --> <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> - <!-- - SIZE is the "size" of the primitive, ie. what the i/j coords need - to be divided by to scale to a single fragment. It is probably - the longer of the two lines that form the tri (ie v0v1 and v0v2)? - --> - <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/> + <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> </reg32> <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG"> <!-- register loaded with position (bary.f) --> diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index c852a7a923f..9c90e3eb24b 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -1442,7 +1442,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs) tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) | A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) | A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) | - A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_CENTER_RHW])); + A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(ij_regid[IJ_PERSP_CENTER_RHW])); tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) | A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) | A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) | @@ -1497,7 +1497,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs) sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER) | CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) | CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) | - CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_SIZE) | + CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) | COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS)); tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1); diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c index 2fc6f308a65..fda5eb25bf4 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c @@ -518,7 +518,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) | A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) | A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) | - A5XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_CENTER_RHW])); + A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(ij_regid[IJ_PERSP_CENTER_RHW])); OUT_RING( ring, A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) | diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index e630ccc2dac..6eee94d8a10 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -840,7 +840,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx, OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) | A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) | A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) | - A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_CENTER_RHW])); + A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(ij_regid[IJ_PERSP_CENTER_RHW])); OUT_RING( ring, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) | @@ -925,7 +925,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx, OUT_RING(ring, CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) | CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) | - CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_SIZE) | + CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) | COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS)); OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1); |