diff options
| author | Rob Clark <robdclark@gmail.com> | 2017-12-18 13:34:18 -0500 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2017-12-19 15:00:18 -0500 |
| commit | 0536737983981b03fbe8bccd9f3a0f7ae81479b0 (patch) | |
| tree | 2247e5f2ba74c1ddd44928be67f449514a2e5cca /src | |
| parent | a1e18e87c775f16f4d66d3bd7de286bfee19fb3a (diff) | |
freedreno/a5xx: use vertex_id_zero_base
Cmdstream traces from blob make it clear that the blob driver dev's
*think* a5xx has a real (non-zero-based) vtxid. But reality claims
differently.
Fixes ./bin/gl-3.2-basevertex-vertexid and probably others.
This means draw-indirect is going to need some gymnastics to copy
base-vertex into uniform. (a4xx probably needs that too.)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_program.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/ir3/ir3_nir.c | 19 |
2 files changed, 1 insertions, 20 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c index aa4babdf5b1..81fe7d4b582 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c @@ -341,7 +341,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS); psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ); - vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID); + vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE); instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID); if (s[FS].v->color0_mrt) { diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_nir.c index 39d3bf15fde..9ab5e0f7f25 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c @@ -52,23 +52,6 @@ static const nir_shader_compiler_options options = { .lower_extract_word = true, }; -static const nir_shader_compiler_options options_5xx = { - .lower_fpow = true, - .lower_fsat = true, - .lower_scmp = true, - .lower_flrp32 = true, - .lower_flrp64 = true, - .lower_ffract = true, - .lower_fmod32 = true, - .lower_fmod64 = true, - .lower_fdiv = true, - .fuse_ffma = true, - .native_integers = true, - .vertex_id_zero_based = false, - .lower_extract_byte = true, - .lower_extract_word = true, -}; - struct nir_shader * ir3_tgsi_to_nir(const struct tgsi_token *tokens) { @@ -78,8 +61,6 @@ ir3_tgsi_to_nir(const struct tgsi_token *tokens) const nir_shader_compiler_options * ir3_get_compiler_options(struct ir3_compiler *compiler) { - if (compiler->gpu_id >= 500) - return &options_5xx; return &options; } |