diff options
| author | Icecream95 <ixn@disroot.org> | 2021-04-29 11:27:28 +1200 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2021-04-30 10:23:40 -0700 |
| commit | 4c0b3b5d9e39e2d3ba58bd54835645e68e4bce77 (patch) | |
| tree | 4b1554173bd8c47a431793e134fcfe5982861d6d /src/panfrost | |
| parent | baaf7cfb822e8fda8e238e265b84d03c20d03f99 (diff) | |
pan/mdg: Fix calculation of available work registers
Make the rmu variable signed; otherwise the MAX2 has no effect and
work_count can end up being larger than 16.
Fixes INSTR_OPERAND_FAULTs in SuperTuxKart.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707
Fixes: c6ed8bf77cb ("panfrost: Fix uniform_count on Midgard")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10507>
(cherry picked from commit f85b7aa5d409ffcc7e0ae013f43068a698d3517e)
Diffstat (limited to 'src/panfrost')
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index 4ff34238f06..1d93cc44f16 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -394,7 +394,7 @@ allocate_registers(compiler_context *ctx, bool *spilled) /* The number of vec4 work registers available depends on the number of * register-mapped uniforms and the shader stage. By ABI we limit blend * shaders to 8 registers, should be lower XXX */ - unsigned rmu = ctx->info->push.count / 4; + int rmu = ctx->info->push.count / 4; int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0); /* No register allocation to do with no SSA */ |