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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-09-26 13:13:32 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2010-09-28 15:58:20 +0800
commit81aae67e58f7c3123724e629a81e2c937864e3be (patch)
tree2079db8f03f0a1a059a7d3c9170087b3046061f5 /src/mesa/drivers/dri/i965/brw_wm_glsl.c
parent956f866030f7bea5fc4a2de28c72e60bdc3a5b3d (diff)
i965: fix const register count for sandybridge
Sandybridge's PS constant buffer payload size is decided from push const buffer command, incorrect size would cause wrong data in payload for position and vertex attributes. This fixes coefficients for tex2d/tex3d.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_glsl.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_glsl.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 1cbd5d2b55a..55aceea9b5c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -342,8 +342,8 @@ static void prealloc_reg(struct brw_wm_compile *c)
}
}
/* number of constant regs used (each reg is float[8]) */
- c->nr_creg = 2 * ((4 * nr_params + 15) / 16);
- reg_index += c->nr_creg;
+ c->nr_creg = ALIGN(nr_params, 2) / 2;
+ reg_index += c->nr_creg;
}
}