path: root/src/gallium/drivers/radeonsi/si_pipe.h
diff options
authorPierre-Eric Pelloux-Prayer <>2021-01-26 17:46:44 +0100
committerMarge Bot <>2021-02-17 09:11:46 +0000
commitbddc0e023c2c87d3248691ea62b77626704cc5a4 (patch)
treee6513e21118af5e2c6e0895a29f4394d5bfb6330 /src/gallium/drivers/radeonsi/si_pipe.h
parenta8373b3d3876afa960ead3378adacc43afcec6ed (diff)
radeonsi: fix read from compute / write from draw sync
A compute dispatch should see the result of a previous draw command. radeonsi was missing this implicit sync, causing rendering artifacts: the compute shader was reading from a texture still being written to by the previous draw. Framebuffer BOs are marked with RADEON_USAGE_NEEDS_IMPLICIT_SYNC, so compute jobs will sync. v2: use RADEON_USAGE_NEEDS_IMPLICIT_SYNC v3: unconditionally make CB coherent after a flush Reviewed-by: Zoltán Böszörményi <> (v3) Reviewed-by: Marek Olšák <> (v3) Cc: mesa-stable Closes: Closes: Closes: Part-of: <>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.h')
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 27da51eaff8..2aa13948fba 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1266,6 +1266,8 @@ struct si_context {
struct list_head shader_query_buffers;
unsigned num_active_shader_queries;
+ bool force_cb_shader_coherent;
/* Statistics gathering for the DCC enablement heuristic. It can't be
* in si_texture because si_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
@@ -1745,6 +1747,7 @@ static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned
bool shaders_read_metadata, bool dcc_pipe_aligned)
+ sctx->force_cb_shader_coherent = false;
if (sctx->chip_class >= GFX10) {
if (sctx->screen->info.tcc_harvested)