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authorMarek Olšák <marek.olsak@amd.com>2016-10-23 13:08:46 +0200
committerMarek Olšák <marek.olsak@amd.com>2017-03-30 14:44:33 +0200
commitba2e7c68ce8d37ebd666614a47abb33502b38ce5 (patch)
tree383f02c8864eccdcb98416ae65beb00f455717d0 /src/gallium/drivers/r600/r600_state.c
parent641b79774ae5f094cf6268b298cbc40d2718e9e8 (diff)
gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/r600/r600_state.c')
-rw-r--r--src/gallium/drivers/r600/r600_state.c64
1 files changed, 32 insertions, 32 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 9ca113ac883..1f7e9b3aa52 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -723,7 +723,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
width = width_first_level;
height = height_first_level;
depth = u_minify(texture->depth0, offset_level);
- pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
+ pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
@@ -733,7 +733,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
} else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
depth = texture->array_size / 6;
- switch (tmp->surface.level[offset_level].mode) {
+ switch (tmp->surface.u.legacy.level[offset_level].mode) {
default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
@@ -755,11 +755,11 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
S_038004_TEX_DEPTH(depth - 1) |
S_038004_DATA_FORMAT(format));
- view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
+ view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
if (offset_level >= tmp->resource.b.b.last_level) {
- view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
} else {
- view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
}
view->tex_resource_words[4] = (word4 |
S_038010_REQUEST_SIZE(1) |
@@ -824,17 +824,17 @@ static void r600_init_color_surface(struct r600_context *rctx,
assert(rtex);
}
- offset = rtex->surface.level[level].offset;
+ offset = rtex->surface.u.legacy.level[level].offset;
color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
- pitch = rtex->surface.level[level].nblk_x / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
+ slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
color_info = 0;
- switch (rtex->surface.level[level].mode) {
+ switch (rtex->surface.u.legacy.level[level].mode) {
default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
@@ -1032,13 +1032,13 @@ static void r600_init_depth_surface(struct r600_context *rctx,
unsigned level, pitch, slice, format, offset, array_mode;
level = surf->base.u.tex.level;
- offset = rtex->surface.level[level].offset;
- pitch = rtex->surface.level[level].nblk_x / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ offset = rtex->surface.u.legacy.level[level].offset;
+ pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
+ slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
- switch (rtex->surface.level[level].mode) {
+ switch (rtex->surface.u.legacy.level[level].mode) {
case RADEON_SURF_MODE_2D:
array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
break;
@@ -1057,7 +1057,7 @@ static void r600_init_depth_surface(struct r600_context *rctx,
surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
- surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
+ surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
@@ -2834,8 +2834,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
uint64_t base, addr;
- dst_mode = rdst->surface.level[dst_level].mode;
- src_mode = rsrc->surface.level[src_level].mode;
+ dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
+ src_mode = rsrc->surface.u.legacy.level[src_level].mode;
assert(dst_mode != src_mode);
y = 0;
@@ -2845,7 +2845,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
/* T2L */
array_mode = r600_array_mode(src_mode);
- slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
+ slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@@ -2857,14 +2857,14 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = src_x;
y = src_y;
z = src_z;
- base = rsrc->surface.level[src_level].offset;
- addr = rdst->surface.level[dst_level].offset;
- addr += rdst->surface.level[dst_level].slice_size * dst_z;
+ base = rsrc->surface.u.legacy.level[src_level].offset;
+ addr = rdst->surface.u.legacy.level[dst_level].offset;
+ addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
addr += dst_y * pitch + dst_x * bpp;
} else {
/* L2T */
array_mode = r600_array_mode(dst_mode);
- slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
+ slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@@ -2876,9 +2876,9 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = dst_x;
y = dst_y;
z = dst_z;
- base = rdst->surface.level[dst_level].offset;
- addr = rsrc->surface.level[src_level].offset;
- addr += rsrc->surface.level[src_level].slice_size * src_z;
+ base = rdst->surface.u.legacy.level[dst_level].offset;
+ addr = rsrc->surface.u.legacy.level[src_level].offset;
+ addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
addr += src_y * pitch + src_x * bpp;
}
/* check that we are in dw/base alignment constraint */
@@ -2956,14 +2956,14 @@ static void r600_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
- dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
- src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
+ dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
+ src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
- dst_mode = rdst->surface.level[dst_level].mode;
- src_mode = rsrc->surface.level[src_level].mode;
+ dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
+ src_mode = rsrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* strict requirement on r6xx/r7xx */
@@ -2982,11 +2982,11 @@ static void r600_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
- src_offset= rsrc->surface.level[src_level].offset;
- src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
+ src_offset= rsrc->surface.u.legacy.level[src_level].offset;
+ src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
- dst_offset = rdst->surface.level[dst_level].offset;
- dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
+ dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
+ dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
size = src_box->height * src_pitch;
/* must be dw aligned */