nv50/ir: fix surface lowering when values get shared accross operations

With nir I encountered the case where the same value can be written to from
multiple surface operations. This caused some weird messups with the unions
as the def.rewrite operations caused unrelated instructions to get new their
value replaced as well.

In order to replace def.rewrite, we have to create a new temp value, write
to that one instead and move to the original value.

Fixes: 869e32593a9 ("gm107/ir: fix loading z offset for layered 3d image bindings")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11053>

1 files changed, 15 insertions, 13 deletions

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 83634f1e34d..3b6daa31d46 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2328,15 +2328,15 @@ NVC0LoweringPass::insertOOBSurfaceOpResult(TexInstruction *su)
    bld.setPosition(su, true);
 
    for (unsigned i = 0; su->defExists(i); ++i) {
-      ValueDef &def = su->def(i);
+      Value *def = su->getDef(i);
+      Value *newDef = bld.getSSA();
+      su->setDef(i, newDef);
 
       Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
       assert(su->cc == CC_NOT_P);
       mov->setPredicate(CC_P, su->getPredicate());
-      Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), NULL, mov->getDef(0));
-
-      def.replace(uni->getDef(0), false);
-      uni->setSrc(0, def.get());
+      Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), newDef, mov->getDef(0));
+      bld.mkMov(def, uni->getDef(0));
    }
 }
 
@@ -2699,10 +2699,12 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
       for (unsigned i = 0; su->defExists(i); ++i) {
          assert(i < 4);
 
-         ValueDef &def = su->def(i);
+         Value *def = su->getDef(i);
+         Value *newDef = bld.getSSA();
          ValueDef &def2 = su2d->def(i);
          Instruction *mov = NULL;
 
+         su->setDef(i, newDef);
          if (pred) {
             mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
             mov->setPredicate(CC_P, pred->getDef(0));
@@ -2710,11 +2712,10 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
 
          Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
                                       bld.getSSA(),
-                                      NULL, def2.get());
-         def.replace(uni->getDef(0), false);
-         uni->setSrc(0, def.get());
+                                      newDef, def2.get());
          if (mov)
             uni->setSrc(2, mov->getDef(0));
+         bld.mkMov(def, uni->getDef(0));
       }
    } else if (pred) {
       // Create a UNION so that RA assigns the same registers
@@ -2722,16 +2723,17 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
       for (unsigned i = 0; su->defExists(i); ++i) {
          assert(i < 4);
 
-         ValueDef &def = su->def(i);
+         Value *def = su->getDef(i);
+         Value *newDef = bld.getSSA();
+         su->setDef(i, newDef);
 
          Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
          mov->setPredicate(CC_P, pred->getDef(0));
 
          Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
                                       bld.getSSA(),
-                                      NULL, mov->getDef(0));
-         def.replace(uni->getDef(0), false);
-         uni->setSrc(0, def.get());
+                                      newDef, mov->getDef(0));
+         bld.mkMov(def, uni->getDef(0));
       }
    }