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authorMarek Olšák <marek.olsak@amd.com>2020-09-16 21:48:18 -0400
committerMarge Bot <eric+marge@anholt.net>2020-09-24 12:29:11 +0000
commit21174dedec43df155309653764d76b4acd4d5f86 (patch)
tree397a406ec675fe40bf3b8de9574eb6d88e0d7e07 /src/gallium/drivers/nouveau/codegen
parentc58b46edf0e96f927c3d7401229479046e57dc7d (diff)
nir: split fuse_ffma into fuse_ffma16/32/64
AMD wants different behavior for each bit size Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index c466d249e58..c5e54779ad7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -3207,7 +3207,9 @@ nvir_nir_shader_compiler_options(int chipset)
nir_shader_compiler_options op = {};
op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
op.lower_ffma = false;
- op.fuse_ffma = false; /* nir doesn't track mad vs fma */
+ op.fuse_ffma16 = false; /* nir doesn't track mad vs fma */
+ op.fuse_ffma32 = false; /* nir doesn't track mad vs fma */
+ op.fuse_ffma64 = false; /* nir doesn't track mad vs fma */
op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET);
op.lower_flrp32 = true;
op.lower_flrp64 = true;