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authorBen Skeggs <bskeggs@redhat.com>2020-06-07 09:52:35 +1000
committerMarge Bot <eric+marge@anholt.net>2020-06-10 22:52:42 +0000
commit78103abe8784e788c7d04b807bc47527b504121e (patch)
tree2ea2eae8d8847d42f8ed44cce62c2ccfc63d7fa0 /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parentcacf2961091b92b281b3fb9a98309fded10c1f33 (diff)
nvir/gv100: initial support
v2: - add TargetGV100::isBarrierRequired() for OP_BREV - use NV50_IR_SUBOP_LOP3_LUT() convenience macro where it makes sense - separated out nir_lower_idiv into its own commit - make use of the shared function to generate compiler options - disable lower_fpow, nir's lowering is broken v3: - use replaceCvt() instead of custom NEG/ABS/SAT lowering v4: - remove WAR from peephole, not needed now we're using replaceCvt() Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Acked-by: Karol Herbst <kherbst@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 8e6b9775d79..f100445e9d0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -898,6 +898,8 @@ NVC0LoweringPass::visit(Function *fn)
gpEmitAddress = bld.loadImm(NULL, 0)->asLValue();
if (fn->cfgExit) {
bld.setPosition(BasicBlock::get(fn->cfgExit)->getExit(), false);
+ if (prog->getTarget()->getChipset() >= NVISA_GV100_CHIPSET)
+ bld.mkOp1(OP_FINAL, TYPE_NONE, NULL, gpEmitAddress)->fixed = 1;
bld.mkMovToReg(0, gpEmitAddress);
}
}