diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2020-07-17 22:51:34 +0200 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2020-07-20 11:23:19 +0000 |
| commit | d1bba2eee79beceff785e4e00108ba46dd167ef3 (patch) | |
| tree | 4a0ec18d16c954afe09ea13ed973b5224d33715d /src/amd/vulkan/si_cmd_buffer.c | |
| parent | d2a3ca289f5686c6afc238a9530efa16560d83fe (diff) | |
radv: disable CPU caching for IBS to reduce fetch latency
AMDGPU_GEM_CREATE_CPU_GTT_USWC should be faster when CPU reads
are unexpected (because they aren't cached).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5959>
Diffstat (limited to 'src/amd/vulkan/si_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 553ea2dfa83..3ec23fc93a5 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -530,7 +530,8 @@ cik_create_gfx_config(struct radv_device *device) RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS| RADEON_FLAG_NO_INTERPROCESS_SHARING | - RADEON_FLAG_READ_ONLY, + RADEON_FLAG_READ_ONLY | + RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS); if (!device->gfx_init) goto fail; |