path: root/src/amd/vulkan/si_cmd_buffer.c
AgeCommit message (Expand)AuthorFilesLines
4 hoursradv: Refactor cs_domain to be a winsys function.Bas Nieuwenhuizen1-6/+5
5 daysradv: Format.Bas Nieuwenhuizen1-1845/+1692
5 daysradv: use explicit VRS mode when configuring PA_CL_VRS_CNTLSamuel Pitoiset1-1/+1
12 daysamd: fix parsing the last dword of DMA_DATA packetsMarek Olšák1-7/+7
2021-03-22radv: enable VRS 2x2 coarse shading for flat shading on GFX10.3+Samuel Pitoiset1-9/+0
2021-02-19radv: emit the trap handler registers earlierSamuel Pitoiset1-0/+41
2021-02-11radv: use a more relaxed alignment for upload buffer allocationsRhys Perry1-1/+1
2021-02-08radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirectionSamuel Pitoiset1-1/+1
2021-01-26radv: remove radv_util.hSamuel Pitoiset1-1/+0
2021-01-26radv: add support for emitting PS_DONE/CS_DONE on GFX6-8Samuel Pitoiset1-14/+42
2021-01-19radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9Samuel Pitoiset1-17/+6
2021-01-15radv: do not invalidate the L2 metadata cache on compute queuesSamuel Pitoiset1-0/+1
2021-01-13radv: Use L2 coherency on GFX9+.Bas Nieuwenhuizen1-11/+20
2021-01-13radv: Use L2 for CP DMA on GFX9+.Bas Nieuwenhuizen1-4/+13
2021-01-04radv: Use VRAM for the initial gfx cmdbuffer.Bas Nieuwenhuizen1-1/+2
2020-12-14radv: implement VK_KHR_fragment_shading_rateSamuel Pitoiset1-0/+9
2020-12-07radv: set the predication boolean as 32-bit if necessarySamuel Pitoiset1-2/+5
2020-11-30radv: only mask 1 CU for GS/VS waves on GFX10.3Samuel Pitoiset1-5/+11
2020-11-30radv: only disable CU2 & CU3 when NGG is enabledSamuel Pitoiset1-1/+5
2020-11-18ac: rename num_render_backends -> max_render_backendsMarek Olšák1-2/+2
2020-10-23amd: replace 0x028848 with the register definitionMarek Olšák1-1/+3
2020-09-28radv: Record cache flushes for RGP.Bas Nieuwenhuizen1-5/+64
2020-09-28radv: Include flushes in the barrier.Bas Nieuwenhuizen1-1/+5
2020-09-24radv: add a tweak for PS wave CU utilization for gfx10.3Samuel Pitoiset1-2/+15
2020-09-21Revert "radv: emit {CB,DB}_RMI_L2_CACHE_CONTROL at framebuffer time"Bas Nieuwenhuizen1-0/+31
2020-09-01amd/registers: switch to new generated register definitionsMarek Olšák1-1/+1
2020-08-28radv: emit {CB,DB}_RMI_L2_CACHE_CONTROL at framebuffer timeSamuel Pitoiset1-31/+0
2020-08-12radv: fix emitting the border color pointer on the compute queueSamuel Pitoiset1-7/+20
2020-08-11radv: limit LATE_ALLOC_GS to prevent a GPU hang on GFX10Samuel Pitoiset1-0/+4
2020-08-11radv/gfx10: add missing initialization of registersSamuel Pitoiset1-1/+29
2020-08-05radv: fix sample shading on GFX 10.3Samuel Pitoiset1-0/+1
2020-07-24radv: emit more invariant registers as part of the initial gfx stateSamuel Pitoiset1-0/+20
2020-07-20radv: disable CPU caching for IBS to reduce fetch latencySamuel Pitoiset1-1/+2
2020-07-13radv: add support for dynamic primitive topologySamuel Pitoiset1-2/+2
2020-07-09radv: compute prim_vertex_count at draw timeSamuel Pitoiset1-2/+28
2020-07-09radv: adjust IA_MULTI_VGT_PARAM.PARTIAL_VS_WAVE at draw timeSamuel Pitoiset1-0/+11
2020-07-09radv: adjust IA_MULTI_VGT_PARAM.WD_SWITCH_ON_EOP at draw timeSamuel Pitoiset1-1/+14
2020-07-02radv: fix wide points and linesSamuel Pitoiset1-1/+1
2020-06-26amd: add proper definitions for NOP packetsMarek Olšák1-2/+2
2020-06-19radv: add support for Sienna CichlidSamuel Pitoiset1-0/+4
2020-05-26amd: replace SH -> SA (shader array) in commentsMarek Olšák1-2/+2
2020-05-26ac/gpu_info: replace num_good_cu_per_sh with min/max_good_cu_per_saMarek Olšák1-1/+1
2020-05-23ac: update register and packet definitions for preemptionMarek Olšák1-2/+2
2020-05-15radv: Implement VK_EXT_custom_border_colorJoshua Ashton1-0/+10
2020-04-25radv: Pass logical device to si_emit_graphicsJoshua Ashton1-2/+4
2020-04-23radv: simplify checking for Navi1x chipsSamuel Pitoiset1-3/+1
2020-04-18Fix promotion of floats to doublesAlbert Astals Cid1-4/+4
2020-03-27radv: stop including files from mesa/mainMarek Olšák1-1/+0
2020-03-12radv: use ac_gpu_info::use_late_allocSamuel Pitoiset1-4/+6
2020-03-12radv: rewrite late alloc computationSamuel Pitoiset1-34/+43