diff options
Diffstat (limited to 'src/gallium/drivers/radeonsi')
23 files changed, 16520 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/Android.mk b/src/gallium/drivers/radeonsi/Android.mk new file mode 100644 index 00000000000..f7e01a3f658 --- /dev/null +++ b/src/gallium/drivers/radeonsi/Android.mk @@ -0,0 +1,38 @@ +# Mesa 3-D graphics library +# +# Copyright (C) 2010-2011 Chia-I Wu <olvaffe@gmail.com> +# Copyright (C) 2010-2011 LunarG Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +LOCAL_PATH := $(call my-dir) + +# get C_SOURCES +include $(LOCAL_PATH)/Makefile.sources + +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(C_SOURCES) + +LOCAL_C_INCLUDES := + +LOCAL_MODULE := libmesa_pipe_radeonsi + +include $(GALLIUM_COMMON_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/src/gallium/drivers/radeonsi/Makefile b/src/gallium/drivers/radeonsi/Makefile new file mode 100644 index 00000000000..90f6f472730 --- /dev/null +++ b/src/gallium/drivers/radeonsi/Makefile @@ -0,0 +1,24 @@ +TOP = ../../../.. +include $(TOP)/configs/current + +LIBNAME = radeonsi + +LIBRARY_INCLUDES = \ + -I$(TOP)/include \ + -I$(TOP)/src/gallium/drivers/radeon/ + + +# get C_SOURCES +include Makefile.sources + +LIBRADEON = $(TOP)/src/gallium/drivers/radeon/libradeon.a + +EXTRA_OBJECTS = \ + $(LIBRADEON) + +CFLAGS+=$(RADEON_CFLAGS) + +include ../../Makefile.template + +# FIXME: Remove when this driver is converted to automake. +all: default diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources new file mode 100644 index 00000000000..394cfe93e07 --- /dev/null +++ b/src/gallium/drivers/radeonsi/Makefile.sources @@ -0,0 +1,13 @@ +C_SOURCES := \ + r600_blit.c \ + r600_buffer.c \ + r600_hw_context.c \ + radeonsi_pipe.c \ + r600_query.c \ + r600_resource.c \ + radeonsi_shader.c \ + r600_texture.c \ + evergreen_hw_context.c \ + evergreen_state.c \ + r600_translate.c \ + r600_state_common.c diff --git a/src/gallium/drivers/radeonsi/SConscript b/src/gallium/drivers/radeonsi/SConscript new file mode 100644 index 00000000000..f2d2bec6e42 --- /dev/null +++ b/src/gallium/drivers/radeonsi/SConscript @@ -0,0 +1,17 @@ +Import('*') + +env = env.Clone() + +env.Append(CPPPATH = [ + '#/include', + '#/src/gallium/drivers/radeon', +]) + +radeonsi = env.ConvenienceLibrary( + target = 'radeonsi', + source = env.ParseSourceList('Makefile.sources', 'C_SOURCES') + ) + +env.Alias('radeonsi', radeonsi) + +Export('radeonsi') diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c b/src/gallium/drivers/radeonsi/evergreen_hw_context.c new file mode 100644 index 00000000000..549673f4a0b --- /dev/null +++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c @@ -0,0 +1,561 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include "r600.h" +#include "r600_hw_context_priv.h" +#include "radeonsi_pipe.h" +#include "sid.h" +#include "util/u_memory.h" +#include <errno.h> + +#define GROUP_FORCE_NEW_BLOCK 0 + +static const struct r600_reg si_config_reg_list[] = { + {R_0088B0_VGT_VTX_VECT_EJECT_REG, REG_FLAG_FLUSH_CHANGE}, + {R_0088C8_VGT_ESGS_RING_SIZE, REG_FLAG_FLUSH_CHANGE}, + {R_0088CC_VGT_GSVS_RING_SIZE, REG_FLAG_FLUSH_CHANGE}, + {R_008958_VGT_PRIMITIVE_TYPE, 0}, + {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE}, + {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE}, + {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE}, +}; + +static const struct r600_reg si_context_reg_list[] = { + {R_028000_DB_RENDER_CONTROL, 0}, + {R_028004_DB_COUNT_CONTROL, 0}, + {R_028008_DB_DEPTH_VIEW, 0}, + {R_02800C_DB_RENDER_OVERRIDE, 0}, + {R_028010_DB_RENDER_OVERRIDE2, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028020_DB_DEPTH_BOUNDS_MIN, 0}, + {R_028024_DB_DEPTH_BOUNDS_MAX, 0}, + {R_028028_DB_STENCIL_CLEAR, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_02803C_DB_DEPTH_INFO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028040_DB_Z_INFO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028044_DB_STENCIL_INFO, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028058_DB_DEPTH_SIZE, 0}, + {R_02805C_DB_DEPTH_SLICE, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0}, + {R_028230_PA_SC_EDGERULE, 0}, + {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0}, + {R_028238_CB_TARGET_MASK, 0}, + {R_02823C_CB_SHADER_MASK, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0}, + {R_028350_PA_SC_RASTER_CONFIG, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0}, + {R_028408_VGT_INDX_OFFSET, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028414_CB_BLEND_RED, 0}, + {R_028418_CB_BLEND_GREEN, 0}, + {R_02841C_CB_BLEND_BLUE, 0}, + {R_028420_CB_BLEND_ALPHA, 0}, + {R_028430_DB_STENCILREFMASK, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0}, + {R_0285BC_PA_CL_UCP_0_X, 0}, + {R_0285C0_PA_CL_UCP_0_Y, 0}, + {R_0285C4_PA_CL_UCP_0_Z, 0}, + {R_0285C8_PA_CL_UCP_0_W, 0}, + {R_0285CC_PA_CL_UCP_1_X, 0}, + {R_0285D0_PA_CL_UCP_1_Y, 0}, + {R_0285D4_PA_CL_UCP_1_Z, 0}, + {R_0285D8_PA_CL_UCP_1_W, 0}, + {R_0285DC_PA_CL_UCP_2_X, 0}, + {R_0285E0_PA_CL_UCP_2_Y, 0}, + {R_0285E4_PA_CL_UCP_2_Z, 0}, + {R_0285E8_PA_CL_UCP_2_W, 0}, + {R_0285EC_PA_CL_UCP_3_X, 0}, + {R_0285F0_PA_CL_UCP_3_Y, 0}, + {R_0285F4_PA_CL_UCP_3_Z, 0}, + {R_0285F8_PA_CL_UCP_3_W, 0}, + {R_0285FC_PA_CL_UCP_4_X, 0}, + {R_028600_PA_CL_UCP_4_Y, 0}, + {R_028604_PA_CL_UCP_4_Z, 0}, + {R_028608_PA_CL_UCP_4_W, 0}, + {R_02860C_PA_CL_UCP_5_X, 0}, + {R_028610_PA_CL_UCP_5_Y, 0}, + {R_028614_PA_CL_UCP_5_Z, 0}, + {R_028618_PA_CL_UCP_5_W, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0}, + {R_0286CC_SPI_PS_INPUT_ENA, 0}, + {R_0286D0_SPI_PS_INPUT_ADDR, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0}, + {R_0286D8_SPI_PS_IN_CONTROL, 0}, + {R_0286E0_SPI_BARYC_CNTL, 0}, + {R_02870C_SPI_SHADER_POS_FORMAT, 0}, + {R_028710_SPI_SHADER_Z_FORMAT, 0}, + {R_028714_SPI_SHADER_COL_FORMAT, 0}, + {R_028780_CB_BLEND0_CONTROL, 0}, + {R_028784_CB_BLEND1_CONTROL, 0}, + {R_028788_CB_BLEND2_CONTROL, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0}, + {R_028790_CB_BLEND4_CONTROL, 0}, + {R_028794_CB_BLEND5_CONTROL, 0}, + {R_028798_CB_BLEND6_CONTROL, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0}, + {R_0287D4_PA_CL_POINT_X_RAD, 0}, + {R_0287D8_PA_CL_POINT_Y_RAD, 0}, + {R_0287DC_PA_CL_POINT_SIZE, 0}, + {R_0287E0_PA_CL_POINT_CULL_RAD, 0}, + {R_028800_DB_DEPTH_CONTROL, 0}, + {R_028804_DB_EQAA, 0}, + {R_028808_CB_COLOR_CONTROL, 0}, + {R_02880C_DB_SHADER_CONTROL, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0}, + {R_028818_PA_CL_VTE_CNTL, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0}, + {R_028824_PA_SU_LINE_STIPPLE_CNTL, 0}, + {R_028828_PA_SU_LINE_STIPPLE_SCALE, 0}, + {R_02882C_PA_SU_PRIM_FILTER_CNTL, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0}, + {R_028A14_VGT_HOS_CNTL, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0}, + {R_028A2C_VGT_GROUP_DECR, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0}, + {R_028A40_VGT_GS_MODE, 0}, + {R_028A48_PA_SC_MODE_CNTL_0, 0}, + {R_028A4C_PA_SC_MODE_CNTL_1, 0}, + {R_028A50_VGT_ENHANCE, 0}, + {R_028A54_VGT_GS_PER_ES, 0}, + {R_028A58_VGT_ES_PER_GS, 0}, + {R_028A5C_VGT_GS_PER_VS, 0}, + {R_028A60_VGT_GSVS_RING_OFFSET_1, 0}, + {R_028A64_VGT_GSVS_RING_OFFSET_2, 0}, + {R_028A68_VGT_GSVS_RING_OFFSET_3, 0}, + {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0}, + {R_028A70_IA_ENHANCE, 0}, + {R_028A84_VGT_PRIMITIVEID_EN, 0}, + {R_028A8C_VGT_PRIMITIVEID_RESET, 0}, + {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0}, + {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0}, + {R_028AA8_IA_MULTI_VGT_PARAM, 0}, + {R_028AAC_VGT_ESGS_RING_ITEMSIZE, 0}, + {R_028AB0_VGT_GSVS_RING_ITEMSIZE, 0}, + {R_028AB4_VGT_REUSE_OFF, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0}, + {R_028ABC_DB_HTILE_SURFACE, 0}, + {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0}, + {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0}, + {R_028AC8_DB_PRELOAD_CONTROL, 0}, + {R_028B54_VGT_SHADER_STAGES_EN, 0}, + {R_028B70_DB_ALPHA_TO_MASK, 0}, + {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0}, + {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0}, + {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0}, + {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0}, + {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0}, + {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0}, + {R_028B94_VGT_STRMOUT_CONFIG, 0}, + {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0}, + {R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0}, + {R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0}, + {R_028BDC_PA_SC_LINE_CNTL, 0}, + {R_028BE0_PA_SC_AA_CONFIG, 0}, + {R_028BE4_PA_SU_VTX_CNTL, 0}, + {R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0}, + {R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0}, + {R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0}, + {R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0}, + {R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0}, + {R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0}, + {R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0}, + {R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0}, + {R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0}, + {R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0}, + {R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0}, + {R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0}, + {R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0}, + {R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0}, + {R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0}, + {R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0}, + {R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0}, + {R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0}, + {R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0}, + {R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0}, + {R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO}, + {R_028C64_CB_COLOR0_PITCH, 0}, + {R_028C68_CB_COLOR0_SLICE, 0}, + {R_028C6C_CB_COLOR0_VIEW, 0}, + {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO}, + {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO}, + {R_028CA0_CB_COLOR1_PITCH, 0}, + {R_028CA4_CB_COLOR1_SLICE, 0}, + {R_028CA8_CB_COLOR1_VIEW, 0}, + {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO}, + {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO}, + {R_028CDC_CB_COLOR2_PITCH, 0}, + {R_028CE0_CB_COLOR2_SLICE, 0}, + {R_028CE4_CB_COLOR2_VIEW, 0}, + {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO}, + {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO}, + {R_028D18_CB_COLOR3_PITCH, 0}, + {R_028D1C_CB_COLOR3_SLICE, 0}, + {R_028D20_CB_COLOR3_VIEW, 0}, + {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO}, + {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO}, + {R_028D54_CB_COLOR4_PITCH, 0}, + {R_028D58_CB_COLOR4_SLICE, 0}, + {R_028D5C_CB_COLOR4_VIEW, 0}, + {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO}, + {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO}, + {R_028D90_CB_COLOR5_PITCH, 0}, + {R_028D94_CB_COLOR5_SLICE, 0}, + {R_028D98_CB_COLOR5_VIEW, 0}, + {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO}, + {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO}, + {R_028DCC_CB_COLOR6_PITCH, 0}, + {R_028DD0_CB_COLOR6_SLICE, 0}, + {R_028DD4_CB_COLOR6_VIEW, 0}, + {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO}, + {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO}, + {R_028E08_CB_COLOR7_PITCH, 0}, + {R_028E0C_CB_COLOR7_SLICE, 0}, + {R_028E10_CB_COLOR7_VIEW, 0}, + {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO}, + {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO}, +}; + +static const struct r600_reg si_sh_reg_list[] = { + {R_00B020_SPI_SHADER_PGM_LO_PS, REG_FLAG_NEED_BO}, + {R_00B024_SPI_SHADER_PGM_HI_PS, REG_FLAG_NEED_BO}, + {R_00B028_SPI_SHADER_PGM_RSRC1_PS, 0}, + {R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B030_SPI_SHADER_USER_DATA_PS_0, REG_FLAG_NEED_BO}, + {R_00B034_SPI_SHADER_USER_DATA_PS_1, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B038_SPI_SHADER_USER_DATA_PS_2, REG_FLAG_NEED_BO}, + {R_00B03C_SPI_SHADER_USER_DATA_PS_3, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B040_SPI_SHADER_USER_DATA_PS_4, REG_FLAG_NEED_BO}, + {R_00B044_SPI_SHADER_USER_DATA_PS_5, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B048_SPI_SHADER_USER_DATA_PS_6, REG_FLAG_NEED_BO}, + {R_00B04C_SPI_SHADER_USER_DATA_PS_7, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B050_SPI_SHADER_USER_DATA_PS_8, REG_FLAG_NEED_BO}, + {R_00B054_SPI_SHADER_USER_DATA_PS_9, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B058_SPI_SHADER_USER_DATA_PS_10, REG_FLAG_NEED_BO}, + {R_00B05C_SPI_SHADER_USER_DATA_PS_11, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B060_SPI_SHADER_USER_DATA_PS_12, REG_FLAG_NEED_BO}, + {R_00B064_SPI_SHADER_USER_DATA_PS_13, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B068_SPI_SHADER_USER_DATA_PS_14, REG_FLAG_NEED_BO}, + {R_00B06C_SPI_SHADER_USER_DATA_PS_15, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B120_SPI_SHADER_PGM_LO_VS, REG_FLAG_NEED_BO}, + {R_00B124_SPI_SHADER_PGM_HI_VS, REG_FLAG_NEED_BO}, + {R_00B128_SPI_SHADER_PGM_RSRC1_VS, 0}, + {R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B130_SPI_SHADER_USER_DATA_VS_0, REG_FLAG_NEED_BO}, + {R_00B134_SPI_SHADER_USER_DATA_VS_1, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B138_SPI_SHADER_USER_DATA_VS_2, REG_FLAG_NEED_BO}, + {R_00B13C_SPI_SHADER_USER_DATA_VS_3, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B140_SPI_SHADER_USER_DATA_VS_4, REG_FLAG_NEED_BO}, + {R_00B144_SPI_SHADER_USER_DATA_VS_5, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B148_SPI_SHADER_USER_DATA_VS_6, REG_FLAG_NEED_BO}, + {R_00B14C_SPI_SHADER_USER_DATA_VS_7, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B150_SPI_SHADER_USER_DATA_VS_8, REG_FLAG_NEED_BO}, + {R_00B154_SPI_SHADER_USER_DATA_VS_9, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B158_SPI_SHADER_USER_DATA_VS_10, REG_FLAG_NEED_BO}, + {R_00B15C_SPI_SHADER_USER_DATA_VS_11, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B160_SPI_SHADER_USER_DATA_VS_12, REG_FLAG_NEED_BO}, + {R_00B164_SPI_SHADER_USER_DATA_VS_13, 0}, + {GROUP_FORCE_NEW_BLOCK, 0}, + {R_00B168_SPI_SHADER_USER_DATA_VS_14, REG_FLAG_NEED_BO}, + {R_00B16C_SPI_SHADER_USER_DATA_VS_15, 0}, +}; + +int si_context_init(struct r600_context *ctx) +{ + int r; + + LIST_INITHEAD(&ctx->active_query_list); + + /* init dirty list */ + LIST_INITHEAD(&ctx->dirty); + LIST_INITHEAD(&ctx->enable_list); + + ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); + if (!ctx->range) { + r = -ENOMEM; + goto out_err; + } + + /* add blocks */ + r = r600_context_add_block(ctx, si_config_reg_list, + Elements(si_config_reg_list), PKT3_SET_CONFIG_REG, SI_CONFIG_REG_OFFSET); + if (r) + goto out_err; + r = r600_context_add_block(ctx, si_context_reg_list, + Elements(si_context_reg_list), PKT3_SET_CONTEXT_REG, SI_CONTEXT_REG_OFFSET); + if (r) + goto out_err; + r = r600_context_add_block(ctx, si_sh_reg_list, + Elements(si_sh_reg_list), PKT3_SET_SH_REG, SI_SH_REG_OFFSET); + if (r) + goto out_err; + + + /* PS SAMPLER */ + /* VS SAMPLER */ + + /* PS SAMPLER BORDER */ + /* VS SAMPLER BORDER */ + + /* PS RESOURCES */ + /* VS RESOURCES */ + + ctx->cs = ctx->ws->cs_create(ctx->ws); + + r600_init_cs(ctx); + ctx->max_db = 8; + return 0; +out_err: + r600_context_fini(ctx); + return r; +} + +static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + + if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) + return; + + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + + ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; +} + +void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +{ + struct radeon_winsys_cs *cs = ctx->cs; + unsigned ndwords = 7; + uint32_t *pm4; + uint64_t va; + + if (draw->indices) { + ndwords = 11; + } + if (ctx->num_cs_dw_queries_suspend) + ndwords += 6; + + /* when increasing ndwords, bump the max limit too */ + assert(ndwords <= R600_MAX_DRAW_CS_DWORDS); + + /* queries need some special values + * (this is non-zero if any query is active) */ + if (ctx->num_cs_dw_queries_suspend) { + pm4 = &cs->buf[cs->cdw]; + pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + pm4[1] = (R_028004_DB_COUNT_CONTROL - SI_CONTEXT_REG_OFFSET) >> 2; + pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1); + pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - SI_CONTEXT_REG_OFFSET) >> 2; + pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1); + cs->cdw += 6; + ndwords -= 6; + } + + /* draw packet */ + pm4 = &cs->buf[cs->cdw]; + pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing); + pm4[1] = draw->vgt_index_type; + pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing); + pm4[3] = draw->vgt_num_instances; + if (draw->indices) { + va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices); + va += draw->indices_bo_offset; + pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing); + pm4[5] = va; + pm4[6] = (va >> 32UL) & 0xFF; + pm4[7] = draw->vgt_num_indices; + pm4[8] = draw->vgt_draw_initiator; + pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); + pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ); + } else { + pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing); + pm4[5] = draw->vgt_num_indices; + pm4[6] = draw->vgt_draw_initiator; + } + cs->cdw += ndwords; +} + +void evergreen_flush_vgt_streamout(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); + cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = 0; + + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); + + cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); + cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ + cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */ + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */ + cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */ + cs->buf[cs->cdw++] = 4; /* poll interval */ +} + +void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) +{ + struct radeon_winsys_cs *cs = ctx->cs; + + if (buffer_enable_bit) { + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1); + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit); + } else { + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0); + } +} diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c b/src/gallium/drivers/radeonsi/evergreen_state.c new file mode 100644 index 00000000000..5049c7b2db6 --- /dev/null +++ b/src/gallium/drivers/radeonsi/evergreen_state.c @@ -0,0 +1,2169 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* TODO: + * - fix mask for depth control & cull for query + */ +#include <stdio.h> +#include <errno.h> +#include "pipe/p_defines.h" +#include "pipe/p_state.h" +#include "pipe/p_context.h" +#include "tgsi/tgsi_scan.h" +#include "tgsi/tgsi_parse.h" +#include "tgsi/tgsi_util.h" +#include "util/u_blitter.h" +#include "util/u_double_list.h" +#include "util/u_transfer.h" +#include "util/u_surface.h" +#include "util/u_pack_color.h" +#include "util/u_memory.h" +#include "util/u_inlines.h" +#include "util/u_framebuffer.h" +#include "pipebuffer/pb_buffer.h" +#include "r600.h" +#include "sid.h" +#include "r600_resource.h" +#include "radeonsi_pipe.h" + +static uint32_t si_translate_blend_function(int blend_func) +{ + switch (blend_func) { + case PIPE_BLEND_ADD: + return V_028780_COMB_DST_PLUS_SRC; + case PIPE_BLEND_SUBTRACT: + return V_028780_COMB_SRC_MINUS_DST; + case PIPE_BLEND_REVERSE_SUBTRACT: + return V_028780_COMB_DST_MINUS_SRC; + case PIPE_BLEND_MIN: + return V_028780_COMB_MIN_DST_SRC; + case PIPE_BLEND_MAX: + return V_028780_COMB_MAX_DST_SRC; + default: + R600_ERR("Unknown blend function %d\n", blend_func); + assert(0); + break; + } + return 0; +} + +static uint32_t si_translate_blend_factor(int blend_fact) +{ + switch (blend_fact) { + case PIPE_BLENDFACTOR_ONE: + return V_028780_BLEND_ONE; + case PIPE_BLENDFACTOR_SRC_COLOR: + return V_028780_BLEND_SRC_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA: + return V_028780_BLEND_SRC_ALPHA; + case PIPE_BLENDFACTOR_DST_ALPHA: + return V_028780_BLEND_DST_ALPHA; + case PIPE_BLENDFACTOR_DST_COLOR: + return V_028780_BLEND_DST_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: + return V_028780_BLEND_SRC_ALPHA_SATURATE; + case PIPE_BLENDFACTOR_CONST_COLOR: + return V_028780_BLEND_CONSTANT_COLOR; + case PIPE_BLENDFACTOR_CONST_ALPHA: + return V_028780_BLEND_CONSTANT_ALPHA; + case PIPE_BLENDFACTOR_ZERO: + return V_028780_BLEND_ZERO; + case PIPE_BLENDFACTOR_INV_SRC_COLOR: + return V_028780_BLEND_ONE_MINUS_SRC_COLOR; + case PIPE_BLENDFACTOR_INV_SRC_ALPHA: + return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_ALPHA: + return V_028780_BLEND_ONE_MINUS_DST_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_COLOR: + return V_028780_BLEND_ONE_MINUS_DST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_COLOR: + return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_ALPHA: + return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; + case PIPE_BLENDFACTOR_SRC1_COLOR: + return V_028780_BLEND_SRC1_COLOR; + case PIPE_BLENDFACTOR_SRC1_ALPHA: + return V_028780_BLEND_SRC1_ALPHA; + case PIPE_BLENDFACTOR_INV_SRC1_COLOR: + return V_028780_BLEND_INV_SRC1_COLOR; + case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: + return V_028780_BLEND_INV_SRC1_ALPHA; + default: + R600_ERR("Bad blend factor %d not supported!\n", blend_fact); + assert(0); + break; + } + return 0; +} + +#if 0 +static uint32_t r600_translate_stencil_op(int s_op) +{ + switch (s_op) { + case PIPE_STENCIL_OP_KEEP: + return V_028800_STENCIL_KEEP; + case PIPE_STENCIL_OP_ZERO: + return V_028800_STENCIL_ZERO; + case PIPE_STENCIL_OP_REPLACE: + return V_028800_STENCIL_REPLACE; + case PIPE_STENCIL_OP_INCR: + return V_028800_STENCIL_INCR; + case PIPE_STENCIL_OP_DECR: + return V_028800_STENCIL_DECR; + case PIPE_STENCIL_OP_INCR_WRAP: + return V_028800_STENCIL_INCR_WRAP; + case PIPE_STENCIL_OP_DECR_WRAP: + return V_028800_STENCIL_DECR_WRAP; + case PIPE_STENCIL_OP_INVERT: + return V_028800_STENCIL_INVERT; + default: + R600_ERR("Unknown stencil op %d", s_op); + assert(0); + break; + } + return 0; +} +#endif + +static uint32_t si_translate_fill(uint32_t func) +{ + switch(func) { + case PIPE_POLYGON_MODE_FILL: + return V_028814_X_DRAW_TRIANGLES; + case PIPE_POLYGON_MODE_LINE: + return V_028814_X_DRAW_LINES; + case PIPE_POLYGON_MODE_POINT: + return V_028814_X_DRAW_POINTS; + default: + assert(0); + return V_028814_X_DRAW_POINTS; + } +} + +/* translates straight */ +static uint32_t si_translate_ds_func(int func) +{ + return func; +} + +static unsigned si_tex_wrap(unsigned wrap) +{ + switch (wrap) { + default: + case PIPE_TEX_WRAP_REPEAT: + return V_008F30_SQ_TEX_WRAP; + case PIPE_TEX_WRAP_CLAMP: + return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: + return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: + return V_008F30_SQ_TEX_CLAMP_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: + return V_008F30_SQ_TEX_MIRROR; + case PIPE_TEX_WRAP_MIRROR_CLAMP: + return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: + return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: + return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; + } +} + +static unsigned si_tex_filter(unsigned filter) +{ + switch (filter) { + default: + case PIPE_TEX_FILTER_NEAREST: + return V_008F38_SQ_TEX_XY_FILTER_POINT; + case PIPE_TEX_FILTER_LINEAR: + return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; + } +} + +static unsigned si_tex_mipfilter(unsigned filter) +{ + switch (filter) { + case PIPE_TEX_MIPFILTER_NEAREST: + return V_008F38_SQ_TEX_Z_FILTER_POINT; + case PIPE_TEX_MIPFILTER_LINEAR: + return V_008F38_SQ_TEX_Z_FILTER_LINEAR; + default: + case PIPE_TEX_MIPFILTER_NONE: + return V_008F38_SQ_TEX_Z_FILTER_NONE; + } +} + +static unsigned si_tex_compare(unsigned compare) +{ + switch (compare) { + default: + case PIPE_FUNC_NEVER: + return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; + case PIPE_FUNC_LESS: + return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; + case PIPE_FUNC_EQUAL: + return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; + case PIPE_FUNC_LEQUAL: + return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; + case PIPE_FUNC_GREATER: + return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; + case PIPE_FUNC_NOTEQUAL: + return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; + case PIPE_FUNC_ALWAYS: + return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; + } +} + +static unsigned si_tex_dim(unsigned dim) +{ + switch (dim) { + default: + case PIPE_TEXTURE_1D: + return V_008F1C_SQ_RSRC_IMG_1D; + case PIPE_TEXTURE_1D_ARRAY: + return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; + case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_RECT: + return V_008F1C_SQ_RSRC_IMG_2D; + case PIPE_TEXTURE_2D_ARRAY: + return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; + case PIPE_TEXTURE_3D: + return V_008F1C_SQ_RSRC_IMG_3D; + case PIPE_TEXTURE_CUBE: + return V_008F1C_SQ_RSRC_IMG_CUBE; + } +} + +static uint32_t si_translate_dbformat(enum pipe_format format) +{ + switch (format) { + case PIPE_FORMAT_Z16_UNORM: + return V_028040_Z_16; + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + return V_028040_Z_24; /* XXX no longer supported on SI */ + case PIPE_FORMAT_Z32_FLOAT: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + return V_028040_Z_32_FLOAT; + default: + return ~0U; + } +} + +static uint32_t si_translate_colorswap(enum pipe_format format) +{ + switch (format) { + /* 8-bit buffers. */ + case PIPE_FORMAT_L4A4_UNORM: + case PIPE_FORMAT_A4R4_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_A8_UINT: + case PIPE_FORMAT_A8_SINT: + case PIPE_FORMAT_R4A4_UNORM: + return V_028C70_SWAP_ALT_REV; + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_I8_UINT: + case PIPE_FORMAT_I8_SINT: + case PIPE_FORMAT_L8_UINT: + case PIPE_FORMAT_L8_SINT: + case PIPE_FORMAT_L8_SRGB: + case PIPE_FORMAT_R8_UNORM: + case PIPE_FORMAT_R8_SNORM: + case PIPE_FORMAT_R8_UINT: + case PIPE_FORMAT_R8_SINT: + return V_028C70_SWAP_STD; + + /* 16-bit buffers. */ + case PIPE_FORMAT_B5G6R5_UNORM: + return V_028C70_SWAP_STD_REV; + + case PIPE_FORMAT_B5G5R5A1_UNORM: + case PIPE_FORMAT_B5G5R5X1_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_B4G4R4A4_UNORM: + case PIPE_FORMAT_B4G4R4X4_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_Z16_UNORM: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_L8A8_UNORM: + case PIPE_FORMAT_L8A8_UINT: + case PIPE_FORMAT_L8A8_SINT: + case PIPE_FORMAT_L8A8_SRGB: + return V_028C70_SWAP_ALT; + case PIPE_FORMAT_R8G8_UNORM: + case PIPE_FORMAT_R8G8_UINT: + case PIPE_FORMAT_R8G8_SINT: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_R16_UNORM: + case PIPE_FORMAT_R16_UINT: + case PIPE_FORMAT_R16_SINT: + case PIPE_FORMAT_R16_FLOAT: + return V_028C70_SWAP_STD; + + /* 32-bit buffers. */ + case PIPE_FORMAT_A8B8G8R8_SRGB: + return V_028C70_SWAP_STD_REV; + case PIPE_FORMAT_B8G8R8A8_SRGB: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_B8G8R8A8_UNORM: + case PIPE_FORMAT_B8G8R8X8_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + return V_028C70_SWAP_ALT_REV; + case PIPE_FORMAT_R8G8B8A8_SNORM: + case PIPE_FORMAT_R8G8B8A8_UNORM: + case PIPE_FORMAT_R8G8B8A8_SSCALED: + case PIPE_FORMAT_R8G8B8A8_USCALED: + case PIPE_FORMAT_R8G8B8A8_SINT: + case PIPE_FORMAT_R8G8B8A8_UINT: + case PIPE_FORMAT_R8G8B8X8_UNORM: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_A8B8G8R8_UNORM: + case PIPE_FORMAT_X8B8G8R8_UNORM: + /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ + return V_028C70_SWAP_STD_REV; + + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_X8Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10X2_SNORM: + case PIPE_FORMAT_R10SG10SB10SA2U_NORM: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_B10G10R10A2_UNORM: + case PIPE_FORMAT_B10G10R10A2_UINT: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_R11G11B10_FLOAT: + case PIPE_FORMAT_R32_FLOAT: + case PIPE_FORMAT_R32_UINT: + case PIPE_FORMAT_R32_SINT: + case PIPE_FORMAT_Z32_FLOAT: + case PIPE_FORMAT_R16G16_FLOAT: + case PIPE_FORMAT_R16G16_UNORM: + case PIPE_FORMAT_R16G16_UINT: + case PIPE_FORMAT_R16G16_SINT: + return V_028C70_SWAP_STD; + + /* 64-bit buffers. */ + case PIPE_FORMAT_R32G32_FLOAT: + case PIPE_FORMAT_R32G32_UINT: + case PIPE_FORMAT_R32G32_SINT: + case PIPE_FORMAT_R16G16B16A16_UNORM: + case PIPE_FORMAT_R16G16B16A16_SNORM: + case PIPE_FORMAT_R16G16B16A16_USCALED: + case PIPE_FORMAT_R16G16B16A16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_UINT: + case PIPE_FORMAT_R16G16B16A16_SINT: + case PIPE_FORMAT_R16G16B16A16_FLOAT: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + + /* 128-bit buffers. */ + case PIPE_FORMAT_R32G32B32A32_FLOAT: + case PIPE_FORMAT_R32G32B32A32_SNORM: + case PIPE_FORMAT_R32G32B32A32_UNORM: + case PIPE_FORMAT_R32G32B32A32_SSCALED: + case PIPE_FORMAT_R32G32B32A32_USCALED: + case PIPE_FORMAT_R32G32B32A32_SINT: + case PIPE_FORMAT_R32G32B32A32_UINT: + return V_028C70_SWAP_STD; + default: + R600_ERR("unsupported colorswap format %d\n", format); + return ~0U; + } + return ~0U; +} + +static uint32_t si_translate_colorformat(enum pipe_format format) +{ + switch (format) { + /* 8-bit buffers. */ + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_A8_UINT: + case PIPE_FORMAT_A8_SINT: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_I8_UINT: + case PIPE_FORMAT_I8_SINT: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_L8_UINT: + case PIPE_FORMAT_L8_SINT: + case PIPE_FORMAT_L8_SRGB: + case PIPE_FORMAT_R8_UNORM: + case PIPE_FORMAT_R8_SNORM: + case PIPE_FORMAT_R8_UINT: + case PIPE_FORMAT_R8_SINT: + return V_028C70_COLOR_8; + + /* 16-bit buffers. */ + case PIPE_FORMAT_B5G6R5_UNORM: + return V_028C70_COLOR_5_6_5; + + case PIPE_FORMAT_B5G5R5A1_UNORM: + case PIPE_FORMAT_B5G5R5X1_UNORM: + return V_028C70_COLOR_1_5_5_5; + + case PIPE_FORMAT_B4G4R4A4_UNORM: + case PIPE_FORMAT_B4G4R4X4_UNORM: + return V_028C70_COLOR_4_4_4_4; + + case PIPE_FORMAT_L8A8_UNORM: + case PIPE_FORMAT_L8A8_UINT: + case PIPE_FORMAT_L8A8_SINT: + case PIPE_FORMAT_L8A8_SRGB: + case PIPE_FORMAT_R8G8_UNORM: + case PIPE_FORMAT_R8G8_UINT: + case PIPE_FORMAT_R8G8_SINT: + return V_028C70_COLOR_8_8; + + case PIPE_FORMAT_Z16_UNORM: + case PIPE_FORMAT_R16_UNORM: + case PIPE_FORMAT_R16_UINT: + case PIPE_FORMAT_R16_SINT: + case PIPE_FORMAT_R16_FLOAT: + case PIPE_FORMAT_R16G16_FLOAT: + return V_028C70_COLOR_16; + + /* 32-bit buffers. */ + case PIPE_FORMAT_A8B8G8R8_SRGB: + case PIPE_FORMAT_A8B8G8R8_UNORM: + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_B8G8R8A8_SRGB: + case PIPE_FORMAT_B8G8R8A8_UNORM: + case PIPE_FORMAT_B8G8R8X8_UNORM: + case PIPE_FORMAT_R8G8B8A8_SNORM: + case PIPE_FORMAT_R8G8B8A8_UNORM: + case PIPE_FORMAT_R8G8B8X8_UNORM: + case PIPE_FORMAT_R8SG8SB8UX8U_NORM: + case PIPE_FORMAT_X8B8G8R8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + case PIPE_FORMAT_R8G8B8_UNORM: + case PIPE_FORMAT_R8G8B8A8_SSCALED: + case PIPE_FORMAT_R8G8B8A8_USCALED: + case PIPE_FORMAT_R8G8B8A8_SINT: + case PIPE_FORMAT_R8G8B8A8_UINT: + return V_028C70_COLOR_8_8_8_8; + + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10X2_SNORM: + case PIPE_FORMAT_B10G10R10A2_UNORM: + case PIPE_FORMAT_B10G10R10A2_UINT: + case PIPE_FORMAT_R10SG10SB10SA2U_NORM: + return V_028C70_COLOR_2_10_10_10; + + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + return V_028C70_COLOR_8_24; + + case PIPE_FORMAT_X8Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + return V_028C70_COLOR_24_8; + + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + return V_028C70_COLOR_X24_8_32_FLOAT; + + case PIPE_FORMAT_R32_FLOAT: + case PIPE_FORMAT_Z32_FLOAT: + return V_028C70_COLOR_32; + + case PIPE_FORMAT_R16G16_SSCALED: + case PIPE_FORMAT_R16G16_UNORM: + case PIPE_FORMAT_R16G16_UINT: + case PIPE_FORMAT_R16G16_SINT: + return V_028C70_COLOR_16_16; + + case PIPE_FORMAT_R11G11B10_FLOAT: + return V_028C70_COLOR_10_11_11; + + /* 64-bit buffers. */ + case PIPE_FORMAT_R16G16B16_USCALED: + case PIPE_FORMAT_R16G16B16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_UINT: + case PIPE_FORMAT_R16G16B16A16_SINT: + case PIPE_FORMAT_R16G16B16A16_USCALED: + case PIPE_FORMAT_R16G16B16A16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_UNORM: + case PIPE_FORMAT_R16G16B16A16_SNORM: + case PIPE_FORMAT_R16G16B16_FLOAT: + case PIPE_FORMAT_R16G16B16A16_FLOAT: + return V_028C70_COLOR_16_16_16_16; + + case PIPE_FORMAT_R32G32_FLOAT: + case PIPE_FORMAT_R32G32_USCALED: + case PIPE_FORMAT_R32G32_SSCALED: + case PIPE_FORMAT_R32G32_SINT: + case PIPE_FORMAT_R32G32_UINT: + return V_028C70_COLOR_32_32; + + /* 128-bit buffers. */ + case PIPE_FORMAT_R32G32B32A32_SNORM: + case PIPE_FORMAT_R32G32B32A32_UNORM: + case PIPE_FORMAT_R32G32B32A32_SSCALED: + case PIPE_FORMAT_R32G32B32A32_USCALED: + case PIPE_FORMAT_R32G32B32A32_SINT: + case PIPE_FORMAT_R32G32B32A32_UINT: + case PIPE_FORMAT_R32G32B32A32_FLOAT: + return V_028C70_COLOR_32_32_32_32; + + /* YUV buffers. */ + case PIPE_FORMAT_UYVY: + case PIPE_FORMAT_YUYV: + /* 96-bit buffers. */ + case PIPE_FORMAT_R32G32B32_FLOAT: + /* 8-bit buffers. */ + case PIPE_FORMAT_L4A4_UNORM: + case PIPE_FORMAT_R4A4_UNORM: + case PIPE_FORMAT_A4R4_UNORM: + default: + return ~0U; /* Unsupported. */ + } +} + +static uint32_t si_colorformat_endian_swap(uint32_t colorformat) +{ + if (R600_BIG_ENDIAN) { + switch(colorformat) { + /* 8-bit buffers. */ + case V_028C70_COLOR_8: + return V_028C70_ENDIAN_NONE; + + /* 16-bit buffers. */ + case V_028C70_COLOR_5_6_5: + case V_028C70_COLOR_1_5_5_5: + case V_028C70_COLOR_4_4_4_4: + case V_028C70_COLOR_16: + case V_028C70_COLOR_8_8: + return V_028C70_ENDIAN_8IN16; + + /* 32-bit buffers. */ + case V_028C70_COLOR_8_8_8_8: + case V_028C70_COLOR_2_10_10_10: + case V_028C70_COLOR_8_24: + case V_028C70_COLOR_24_8: + case V_028C70_COLOR_16_16: + return V_028C70_ENDIAN_8IN32; + + /* 64-bit buffers. */ + case V_028C70_COLOR_16_16_16_16: + return V_028C70_ENDIAN_8IN16; + + case V_028C70_COLOR_32_32: + return V_028C70_ENDIAN_8IN32; + + /* 128-bit buffers. */ + case V_028C70_COLOR_32_32_32_32: + return V_028C70_ENDIAN_8IN32; + default: + return V_028C70_ENDIAN_NONE; /* Unsupported. */ + } + } else { + return V_028C70_ENDIAN_NONE; + } +} + +static uint32_t si_translate_texformat(struct pipe_screen *screen, + enum pipe_format format, + const struct util_format_description *desc, + int first_non_void) +{ + boolean uniform = TRUE; + int i; + + /* Colorspace (return non-RGB formats directly). */ + switch (desc->colorspace) { + /* Depth stencil formats */ + case UTIL_FORMAT_COLORSPACE_ZS: + switch (format) { + case PIPE_FORMAT_Z16_UNORM: + return V_008F14_IMG_DATA_FORMAT_16; + case PIPE_FORMAT_X24S8_UINT: + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + return V_008F14_IMG_DATA_FORMAT_24_8; + case PIPE_FORMAT_S8X24_UINT: + case PIPE_FORMAT_X8Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + return V_008F14_IMG_DATA_FORMAT_8_24; + case PIPE_FORMAT_S8_UINT: + return V_008F14_IMG_DATA_FORMAT_8; + case PIPE_FORMAT_Z32_FLOAT: + return V_008F14_IMG_DATA_FORMAT_32; + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + return V_008F14_IMG_DATA_FORMAT_X24_8_32; + default: + goto out_unknown; + } + + case UTIL_FORMAT_COLORSPACE_YUV: + goto out_unknown; /* TODO */ + + case UTIL_FORMAT_COLORSPACE_SRGB: + break; + + default: + break; + } + + /* TODO compressed formats */ + + if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { + return V_008F14_IMG_DATA_FORMAT_5_9_9_9; + } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { + return V_008F14_IMG_DATA_FORMAT_10_11_11; + } + + /* R8G8Bx_SNORM - TODO CxV8U8 */ + + /* See whether the components are of the same size. */ + for (i = 1; i < desc->nr_channels; i++) { + uniform = uniform && desc->channel[0].size == desc->channel[i].size; + } + + /* Non-uniform formats. */ + if (!uniform) { + switch(desc->nr_channels) { + case 3: + if (desc->channel[0].size == 5 && + desc->channel[1].size == 6 && + desc->channel[2].size == 5) { + return V_008F14_IMG_DATA_FORMAT_5_6_5; + } + goto out_unknown; + case 4: + if (desc->channel[0].size == 5 && + desc->channel[1].size == 5 && + desc->channel[2].size == 5 && + desc->channel[3].size == 1) { + return V_008F14_IMG_DATA_FORMAT_1_5_5_5; + } + if (desc->channel[0].size == 10 && + desc->channel[1].size == 10 && + desc->channel[2].size == 10 && + desc->channel[3].size == 2) { + return V_008F14_IMG_DATA_FORMAT_2_10_10_10; + } + goto out_unknown; + } + goto out_unknown; + } + + if (first_non_void < 0 || first_non_void > 3) + goto out_unknown; + + /* uniform formats */ + switch (desc->channel[first_non_void].size) { + case 4: + switch (desc->nr_channels) { + case 2: + return V_008F14_IMG_DATA_FORMAT_4_4; + case 4: + return V_008F14_IMG_DATA_FORMAT_4_4_4_4; + } + break; + case 8: + switch (desc->nr_channels) { + case 1: + return V_008F14_IMG_DATA_FORMAT_8; + case 2: + return V_008F14_IMG_DATA_FORMAT_8_8; + case 4: + return V_008F14_IMG_DATA_FORMAT_8_8_8_8; + } + break; + case 16: + switch (desc->nr_channels) { + case 1: + return V_008F14_IMG_DATA_FORMAT_16; + case 2: + return V_008F14_IMG_DATA_FORMAT_16_16; + case 4: + return V_008F14_IMG_DATA_FORMAT_16_16_16_16; + } + break; + case 32: + switch (desc->nr_channels) { + case 1: + return V_008F14_IMG_DATA_FORMAT_32; + case 2: + return V_008F14_IMG_DATA_FORMAT_32_32; + case 3: + return V_008F14_IMG_DATA_FORMAT_32_32_32; + case 4: + return V_008F14_IMG_DATA_FORMAT_32_32_32_32; + } + } + +out_unknown: + /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ + return ~0; +} + +static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) +{ + return si_translate_texformat(screen, format, util_format_description(format), + util_format_get_first_non_void_channel(format)) != ~0U; +} + +uint32_t si_translate_vertexformat(struct pipe_screen *screen, + enum pipe_format format, + const struct util_format_description *desc, + int first_non_void) +{ + uint32_t result = si_translate_texformat(screen, format, desc, first_non_void); + + if (result == V_008F0C_BUF_DATA_FORMAT_INVALID || + result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32) + result = ~0; + + return result; +} + +static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) +{ + return si_translate_vertexformat(screen, format, util_format_description(format), + util_format_get_first_non_void_channel(format)) != ~0U; +} + +static bool r600_is_colorbuffer_format_supported(enum pipe_format format) +{ + return si_translate_colorformat(format) != ~0U && + si_translate_colorswap(format) != ~0U; +} + +static bool r600_is_zs_format_supported(enum pipe_format format) +{ + return si_translate_dbformat(format) != ~0U; +} + +boolean si_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned sample_count, + unsigned usage) +{ + unsigned retval = 0; + + if (target >= PIPE_MAX_TEXTURE_TYPES) { + R600_ERR("r600: unsupported texture type %d\n", target); + return FALSE; + } + + if (!util_format_is_supported(format, usage)) + return FALSE; + + /* Multisample */ + if (sample_count > 1) + return FALSE; + + if ((usage & PIPE_BIND_SAMPLER_VIEW) && + si_is_sampler_format_supported(screen, format)) { + retval |= PIPE_BIND_SAMPLER_VIEW; + } + + if ((usage & (PIPE_BIND_RENDER_TARGET | + PIPE_BIND_DISPLAY_TARGET | + PIPE_BIND_SCANOUT | + PIPE_BIND_SHARED)) && + r600_is_colorbuffer_format_supported(format)) { + retval |= usage & + (PIPE_BIND_RENDER_TARGET | + PIPE_BIND_DISPLAY_TARGET | + PIPE_BIND_SCANOUT | + PIPE_BIND_SHARED); + } + + if ((usage & PIPE_BIND_DEPTH_STENCIL) && + r600_is_zs_format_supported(format)) { + retval |= PIPE_BIND_DEPTH_STENCIL; + } + + if ((usage & PIPE_BIND_VERTEX_BUFFER) && + si_is_vertex_format_supported(screen, format)) { + retval |= PIPE_BIND_VERTEX_BUFFER; + } + + if (usage & PIPE_BIND_TRANSFER_READ) + retval |= PIPE_BIND_TRANSFER_READ; + if (usage & PIPE_BIND_TRANSFER_WRITE) + retval |= PIPE_BIND_TRANSFER_WRITE; + + return retval == usage; +} + +static void evergreen_set_blend_color(struct pipe_context *ctx, + const struct pipe_blend_color *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + + if (rstate == NULL) + return; + + rstate->id = R600_PIPE_STATE_BLEND_COLOR; + r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0); + + free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); + rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; + r600_context_pipe_state_set(rctx, rstate); +} + +static void *evergreen_create_blend_state(struct pipe_context *ctx, + const struct pipe_blend_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); + struct r600_pipe_state *rstate; + uint32_t color_control, target_mask; + /* FIXME there is more then 8 framebuffer */ + unsigned blend_cntl[8]; + + if (blend == NULL) { + return NULL; + } + + rstate = &blend->rstate; + + rstate->id = R600_PIPE_STATE_BLEND; + + target_mask = 0; + color_control = S_028808_MODE(V_028808_CB_NORMAL); + if (state->logicop_enable) { + color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); + } else { + color_control |= S_028808_ROP3(0xcc); + } + /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ + if (state->independent_blend_enable) { + for (int i = 0; i < 8; i++) { + target_mask |= (state->rt[i].colormask << (4 * i)); + } + } else { + for (int i = 0; i < 8; i++) { + target_mask |= (state->rt[0].colormask << (4 * i)); + } + } + blend->cb_target_mask = target_mask; + + r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, + color_control, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0); + + for (int i = 0; i < 8; i++) { + /* state->rt entries > 0 only written if independent blending */ + const int j = state->independent_blend_enable ? i : 0; + + unsigned eqRGB = state->rt[j].rgb_func; + unsigned srcRGB = state->rt[j].rgb_src_factor; + unsigned dstRGB = state->rt[j].rgb_dst_factor; + unsigned eqA = state->rt[j].alpha_func; + unsigned srcA = state->rt[j].alpha_src_factor; + unsigned dstA = state->rt[j].alpha_dst_factor; + + blend_cntl[i] = 0; + if (!state->rt[j].blend_enable) + continue; + + blend_cntl[i] |= S_028780_ENABLE(1); + blend_cntl[i] |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); + blend_cntl[i] |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); + blend_cntl[i] |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); + + if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { + blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1); + blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); + blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); + blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); + } + } + for (int i = 0; i < 8; i++) { + r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0); + } + + return rstate; +} + +static void *evergreen_create_dsa_state(struct pipe_context *ctx, + const struct pipe_depth_stencil_alpha_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); + unsigned db_depth_control, alpha_test_control, alpha_ref; + unsigned db_render_override, db_render_control; + struct r600_pipe_state *rstate; + + if (dsa == NULL) { + return NULL; + } + + dsa->valuemask[0] = state->stencil[0].valuemask; + dsa->valuemask[1] = state->stencil[1].valuemask; + dsa->writemask[0] = state->stencil[0].writemask; + dsa->writemask[1] = state->stencil[1].writemask; + + rstate = &dsa->rstate; + + rstate->id = R600_PIPE_STATE_DSA; + db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | + S_028800_Z_WRITE_ENABLE(state->depth.writemask) | + S_028800_ZFUNC(state->depth.func); + + /* stencil */ + if (state->stencil[0].enabled) { + db_depth_control |= S_028800_STENCIL_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func)); + //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); + //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); + //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); + + if (state->stencil[1].enabled) { + db_depth_control |= S_028800_BACKFACE_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func)); + //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); + //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); + //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); + } + } + + /* alpha */ + alpha_test_control = 0; + alpha_ref = 0; + if (state->alpha.enabled) { + //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); + //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); + alpha_ref = fui(state->alpha.ref_value); + } + dsa->alpha_ref = alpha_ref; + + /* misc */ + db_render_control = 0; + db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | + S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | + S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); + /* TODO db_render_override depends on query */ + r600_pipe_state_add_reg(rstate, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0); + //r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0); + r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0); + dsa->db_render_override = db_render_override; + + return rstate; +} + +static void *evergreen_create_rs_state(struct pipe_context *ctx, + const struct pipe_rasterizer_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); + struct r600_pipe_state *rstate; + unsigned tmp; + unsigned prov_vtx = 1, polygon_dual_mode; + unsigned clip_rule; + float psize_min, psize_max; + + if (rs == NULL) { + return NULL; + } + + polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || + state->fill_back != PIPE_POLYGON_MODE_FILL); + + if (state->flatshade_first) + prov_vtx = 0; + + rstate = &rs->rstate; + rs->flatshade = state->flatshade; + rs->sprite_coord_enable = state->sprite_coord_enable; + rs->pa_sc_line_stipple = state->line_stipple_enable ? + S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | + S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; + rs->pa_su_sc_mode_cntl = + S_028814_PROVOKING_VTX_LAST(prov_vtx) | + S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | + S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | + S_028814_FACE(!state->front_ccw) | + S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | + S_028814_POLY_MODE(polygon_dual_mode) | + S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | + S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); + rs->pa_cl_clip_cntl = + S_028810_PS_UCP_MODE(3) | + S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | + S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | + S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); + rs->pa_cl_vs_out_cntl = + S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | + S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); + + clip_rule = state->scissor ? 0xAAAA : 0xFFFF; + + /* offset */ + rs->offset_units = state->offset_units; + rs->offset_scale = state->offset_scale * 12.0f; + + rstate->id = R600_PIPE_STATE_RASTERIZER; + tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade); + if (state->sprite_coord_enable) { + tmp |= S_0286D4_PNT_SPRITE_ENA(1) | + S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | + S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | + S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | + S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); + if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { + tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); + } + } + r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0); + /* point size 12.4 fixed point */ + tmp = (unsigned)(state->point_size * 8.0); + r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0); + + if (state->point_size_per_vertex) { + psize_min = util_get_min_point_size(state); + psize_max = 8192; + } else { + /* Force the point size to be as if the vertex output was disabled. */ + psize_min = state->point_size; + psize_max = state->point_size; + } + /* Divide by two, because 0.5 = 1 pixel. */ + r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, + S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | + S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)), + NULL, 0); + + tmp = (unsigned)state->line_width * 8; + r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, + S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable), + NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL, + S_028BE4_PIX_CENTER(state->gl_rasterization_rules), + NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0); + r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0); + return rstate; +} + +static void *si_create_sampler_state(struct pipe_context *ctx, + const struct pipe_sampler_state *state) +{ + struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); + union util_color uc; + unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; + unsigned border_color_type; + + if (rstate == NULL) { + return NULL; + } + + util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + switch (uc.ui) { + case 0x000000FF: /* opaque black */ + border_color_type = 0; + break; + case 0x00000000: /* transparent black */ + border_color_type = 1; + break; + case 0xFFFFFFFF: /* white */ + border_color_type = 1; + break; + default: /* Use border color pointer */ + border_color_type = 3; + } + + rstate->val[0] = si_tex_wrap(state->wrap_s) | + si_tex_wrap(state->wrap_t) << 3 | + si_tex_wrap(state->wrap_r) << 6 | + (state->max_anisotropy & 0x7) << 9 | /* XXX */ + si_tex_compare(state->compare_func) << 12 | + !state->normalized_coords << 15 | + aniso_flag_offset << 16 | /* XXX */ + !state->seamless_cube_map << 28 | + si_tex_mipfilter(state->min_mip_filter) << 29; + rstate->val[1] = S_FIXED(CLAMP(state->min_lod, 0, 15), 8) | + S_FIXED(CLAMP(state->max_lod, 0, 15), 8) << 12; + rstate->val[2] = S_FIXED(CLAMP(state->lod_bias, -16, 16), 8) | + si_tex_filter(state->mag_img_filter) << 20 | + si_tex_filter(state->min_img_filter) << 22; + rstate->val[3] = border_color_type << 30; + +#if 0 + if (border_color_type == 3) { + r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0); + } +#endif + return rstate; +} + +static void si_delete_sampler_state(struct pipe_context *ctx, + void *state) +{ + free(state); +} + +static unsigned si_map_swizzle(unsigned swizzle) +{ + switch (swizzle) { + case UTIL_FORMAT_SWIZZLE_Y: + return V_008F1C_SQ_SEL_Y; + case UTIL_FORMAT_SWIZZLE_Z: + return V_008F1C_SQ_SEL_Z; + case UTIL_FORMAT_SWIZZLE_W: + return V_008F1C_SQ_SEL_W; + case UTIL_FORMAT_SWIZZLE_0: + return V_008F1C_SQ_SEL_0; + case UTIL_FORMAT_SWIZZLE_1: + return V_008F1C_SQ_SEL_1; + default: /* UTIL_FORMAT_SWIZZLE_X */ + return V_008F1C_SQ_SEL_X; + } +} + +static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state) +{ + struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); + struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; + const struct util_format_description *desc = util_format_description(state->format); + unsigned format, num_format, endian; + uint32_t pitch = 0; + unsigned char state_swizzle[4], swizzle[4], array_mode = 0, tile_type = 0; + unsigned height, depth; + int first_non_void; + uint64_t va; + + if (view == NULL) + return NULL; + + /* initialize base object */ + view->base = *state; + view->base.texture = NULL; + pipe_reference(NULL, &texture->reference); + view->base.texture = texture; + view->base.reference.count = 1; + view->base.context = ctx; + + state_swizzle[0] = state->swizzle_r; + state_swizzle[1] = state->swizzle_g; + state_swizzle[2] = state->swizzle_b; + state_swizzle[3] = state->swizzle_a; + util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); + + first_non_void = util_format_get_first_non_void_channel(state->format); + switch (desc->channel[first_non_void].type) { + case UTIL_FORMAT_TYPE_FLOAT: + num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; + break; + case UTIL_FORMAT_TYPE_FIXED: + num_format = V_008F14_IMG_NUM_FORMAT_USCALED; /* XXX */ + break; + case UTIL_FORMAT_TYPE_SIGNED: + num_format = V_008F14_IMG_NUM_FORMAT_SNORM; + break; + case UTIL_FORMAT_TYPE_UNSIGNED: + default: + num_format = V_008F14_IMG_NUM_FORMAT_UNORM; + } + + format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void); + if (format == ~0) { + format = 0; + } + + if (tmp->depth && !tmp->is_flushing_texture) { + r600_texture_depth_flush(ctx, texture, TRUE); + tmp = tmp->flushed_depth_texture; + } + + endian = si_colorformat_endian_swap(format); + + height = texture->height0; + depth = texture->depth0; + + pitch = align(tmp->pitch_in_blocks[0] * + util_format_get_blockwidth(state->format), 8); + array_mode = tmp->array_mode[0]; + tile_type = tmp->tile_type; + + if (texture->target == PIPE_TEXTURE_1D_ARRAY) { + height = 1; + depth = texture->array_size; + } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { + depth = texture->array_size; + } + + va = r600_resource_va(ctx->screen, texture); + view->state[0] = (va + tmp->offset[0]) >> 8; + view->state[1] = ((va + tmp->offset[0]) >> 40) & 0xff; + view->state[1] |= (S_008F14_DATA_FORMAT(format) | + S_008F14_NUM_FORMAT(num_format)); + view->state[2] = (S_008F18_WIDTH(texture->width0 - 1) | + S_008F18_HEIGHT(height - 1)); + view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | + S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | + S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | + S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | + S_008F1C_BASE_LEVEL(state->u.tex.first_level) | + S_008F1C_LAST_LEVEL(state->u.tex.last_level) | + S_008F1C_TYPE(si_tex_dim(texture->target))); + view->state[4] = (S_008F20_DEPTH(depth - 1) | + S_008F20_PITCH((pitch / 8) - 1)); + view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | + S_008F24_LAST_ARRAY(state->u.tex.last_layer)); + view->state[6] = 0; + view->state[7] = 0; + + return &view->base; +} + +static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, + struct pipe_sampler_view **views) +{ +} + +static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, + struct pipe_sampler_view **views) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; + struct r600_pipe_state *rstate = &rctx->ps_samplers.rstate; + struct r600_resource *bo; + int i; + int has_depth = 0; + uint64_t va; + char *ptr; + + if (!count) + goto out; + + r600_inval_texture_cache(rctx); + + bo = (struct r600_resource*) + pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, + count * sizeof(resource[0]->state)); + ptr = rctx->ws->buffer_map(bo->buf, rctx->cs, PIPE_TRANSFER_WRITE); + + for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) { + pipe_sampler_view_reference( + (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], + views[i]); + + if (resource[i]) { + if (((struct r600_resource_texture *)resource[i]->base.texture)->depth) + has_depth = 1; + + memcpy(ptr, resource[i]->state, sizeof(resource[0]->state)); + } else + memset(ptr, 0, sizeof(resource[0]->state)); + } + + rctx->ws->buffer_unmap(bo->buf); + + for (i = count; i < NUM_TEX_UNITS; i++) { + if (rctx->ps_samplers.views[i]) + pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); + } + + va = r600_resource_va(ctx->screen, (void *)bo); + r600_pipe_state_add_reg(rstate, R_00B040_SPI_SHADER_USER_DATA_PS_4, va, bo, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32, NULL, 0); + r600_context_pipe_state_set(rctx, rstate); + +out: + rctx->have_depth_texture = has_depth; + rctx->ps_samplers.n_views = count; +} + +static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; + struct r600_pipe_state *rstate = &rctx->ps_samplers.rstate; + struct r600_resource *bo; + uint64_t va; + char *ptr; + int i; + + if (!count) + goto out; + + r600_inval_texture_cache(rctx); + + bo = (struct r600_resource*) + pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, + count * sizeof(rstates[0]->val)); + ptr = rctx->ws->buffer_map(bo->buf, rctx->cs, PIPE_TRANSFER_WRITE); + + for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) { + memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val)); + } + + rctx->ws->buffer_unmap(bo->buf); + + va = r600_resource_va(ctx->screen, (void *)bo); + r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32, NULL, 0); + r600_context_pipe_state_set(rctx, rstate); + +out: + rctx->ps_samplers.n_samplers = count; +} + +static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) +{ +} + +static void evergreen_set_clip_state(struct pipe_context *ctx, + const struct pipe_clip_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + + if (rstate == NULL) + return; + + rctx->clip = *state; + rstate->id = R600_PIPE_STATE_CLIP; + for (int i = 0; i < 6; i++) { + r600_pipe_state_add_reg(rstate, + R_0285BC_PA_CL_UCP_0_X + i * 16, + fui(state->ucp[i][0]), NULL, 0); + r600_pipe_state_add_reg(rstate, + R_0285C0_PA_CL_UCP_0_Y + i * 16, + fui(state->ucp[i][1]) , NULL, 0); + r600_pipe_state_add_reg(rstate, + R_0285C4_PA_CL_UCP_0_Z + i * 16, + fui(state->ucp[i][2]), NULL, 0); + r600_pipe_state_add_reg(rstate, + R_0285C8_PA_CL_UCP_0_W + i * 16, + fui(state->ucp[i][3]), NULL, 0); + } + + free(rctx->states[R600_PIPE_STATE_CLIP]); + rctx->states[R600_PIPE_STATE_CLIP] = rstate; + r600_context_pipe_state_set(rctx, rstate); +} + +static void evergreen_set_polygon_stipple(struct pipe_context *ctx, + const struct pipe_poly_stipple *state) +{ +} + +static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) +{ +} + +static void evergreen_set_scissor_state(struct pipe_context *ctx, + const struct pipe_scissor_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + uint32_t tl, br; + + if (rstate == NULL) + return; + + rstate->id = R600_PIPE_STATE_SCISSOR; + tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); + br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); + r600_pipe_state_add_reg(rstate, + R_028210_PA_SC_CLIPRECT_0_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028214_PA_SC_CLIPRECT_0_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028218_PA_SC_CLIPRECT_1_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_02821C_PA_SC_CLIPRECT_1_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028220_PA_SC_CLIPRECT_2_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028224_PA_SC_CLIPRECT_2_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028228_PA_SC_CLIPRECT_3_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_02822C_PA_SC_CLIPRECT_3_BR, br, + NULL, 0); + + free(rctx->states[R600_PIPE_STATE_SCISSOR]); + rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; + r600_context_pipe_state_set(rctx, rstate); +} + +static void evergreen_set_viewport_state(struct pipe_context *ctx, + const struct pipe_viewport_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + + if (rstate == NULL) + return; + + rctx->viewport = *state; + rstate->id = R600_PIPE_STATE_VIEWPORT; + r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028350_PA_SC_RASTER_CONFIG, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0); + + free(rctx->states[R600_PIPE_STATE_VIEWPORT]); + rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; + r600_context_pipe_state_set(rctx, rstate); +} + +static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, + const struct pipe_framebuffer_state *state, int cb) +{ + struct r600_resource_texture *rtex; + struct r600_surface *surf; + unsigned level = state->cbufs[cb]->u.tex.level; + unsigned pitch, slice; + unsigned color_info; + unsigned format, swap, ntype, endian; + uint64_t offset; + unsigned tile_type; + const struct util_format_description *desc; + int i; + unsigned blend_clamp = 0, blend_bypass = 0; + + surf = (struct r600_surface *)state->cbufs[cb]; + rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; + + if (rtex->depth) + rctx->have_depth_fb = TRUE; + + if (rtex->depth && !rtex->is_flushing_texture) { + r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); + rtex = rtex->flushed_depth_texture; + } + + /* XXX quite sure for dx10+ hw don't need any offset hacks */ + offset = r600_texture_get_offset(rtex, + level, state->cbufs[cb]->u.tex.first_layer); + pitch = rtex->pitch_in_blocks[level] / 8 - 1; + slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; + desc = util_format_description(surf->base.format); + for (i = 0; i < 4; i++) { + if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { + break; + } + } + if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { + ntype = V_028C70_NUMBER_FLOAT; + } else { + ntype = V_028C70_NUMBER_UNORM; + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) + ntype = V_028C70_NUMBER_SRGB; + else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { + if (desc->channel[i].normalized) + ntype = V_028C70_NUMBER_SNORM; + else if (desc->channel[i].pure_integer) + ntype = V_028C70_NUMBER_SINT; + } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { + if (desc->channel[i].normalized) + ntype = V_028C70_NUMBER_UNORM; + else if (desc->channel[i].pure_integer) + ntype = V_028C70_NUMBER_UINT; + } + } + + format = si_translate_colorformat(surf->base.format); + swap = si_translate_colorswap(surf->base.format); + if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) { + endian = V_028C70_ENDIAN_NONE; + } else { + endian = si_colorformat_endian_swap(format); + } + + /* blend clamp should be set for all NORM/SRGB types */ + if (ntype == V_028C70_NUMBER_UNORM || + ntype == V_028C70_NUMBER_SNORM || + ntype == V_028C70_NUMBER_SRGB) + blend_clamp = 1; + + /* set blend bypass according to docs if SINT/UINT or + 8/24 COLOR variants */ + if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || + format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || + format == V_028C70_COLOR_X24_8_32_FLOAT) { + blend_clamp = 0; + blend_bypass = 1; + } + + color_info = S_028C70_FORMAT(format) | + S_028C70_COMP_SWAP(swap) | + //S_028C70_ARRAY_MODE(rtex->array_mode[level]) | + S_028C70_BLEND_CLAMP(blend_clamp) | + S_028C70_BLEND_BYPASS(blend_bypass) | + S_028C70_NUMBER_TYPE(ntype) | + S_028C70_ENDIAN(endian); + + color_info |= S_028C70_LINEAR_GENERAL(1); + + rctx->alpha_ref_dirty = true; + + offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); + offset >>= 8; + + /* FIXME handle enabling of CB beyond BASE8 which has different offset */ + r600_pipe_state_add_reg(rstate, + R_028C60_CB_COLOR0_BASE + cb * 0x3C, + offset, &rtex->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, + R_028C64_CB_COLOR0_PITCH + cb * 0x3C, + S_028C64_TILE_MAX(pitch), + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028C68_CB_COLOR0_SLICE + cb * 0x3C, + S_028C68_TILE_MAX(slice), + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, + 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028C70_CB_COLOR0_INFO + cb * 0x3C, + color_info, &rtex->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, + R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, + 0, + &rtex->resource, RADEON_USAGE_READWRITE); +} + +static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate, + const struct pipe_framebuffer_state *state) +{ + struct r600_resource_texture *rtex; + struct r600_surface *surf; + unsigned level, first_layer, pitch, slice, format, array_mode; + uint64_t offset; + + if (state->zsbuf == NULL) { + r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0); + return; + } + + surf = (struct r600_surface *)state->zsbuf; + level = surf->base.u.tex.level; + rtex = (struct r600_resource_texture*)surf->base.texture; + + /* XXX remove this once tiling is properly supported */ + array_mode = 0;/*rtex->array_mode[level] ? rtex->array_mode[level] : + V_028C70_ARRAY_1D_TILED_THIN1;*/ + + first_layer = surf->base.u.tex.first_layer; + offset = r600_texture_get_offset(rtex, level, first_layer); + pitch = rtex->pitch_in_blocks[level] / 8 - 1; + slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; + format = si_translate_dbformat(rtex->real_format); + + offset += r600_resource_va(rctx->context.screen, surf->base.texture); + offset >>= 8; + + r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE, + offset, &rtex->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE, + offset, &rtex->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, NULL, 0); + + if (rtex->stencil) { + uint64_t stencil_offset = + r600_texture_get_offset(rtex->stencil, level, first_layer); + + stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil); + stencil_offset >>= 8; + + r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE, + stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE, + stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE); + r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, + 1, NULL, 0); + } else { + r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, + 0, NULL, 0); + } + + r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, + /*S_028040_ARRAY_MODE(array_mode) |*/ S_028040_FORMAT(format), + NULL, 0); + r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, + S_028058_PITCH_TILE_MAX(pitch), + NULL, 0); + r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, + S_02805C_SLICE_TILE_MAX(slice), + NULL, 0); +} + +static void evergreen_set_framebuffer_state(struct pipe_context *ctx, + const struct pipe_framebuffer_state *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + uint32_t shader_mask, tl, br; + int tl_x, tl_y, br_x, br_y; + + if (rstate == NULL) + return; + + r600_flush_framebuffer(rctx, false); + + /* unreference old buffer and reference new one */ + rstate->id = R600_PIPE_STATE_FRAMEBUFFER; + + util_copy_framebuffer_state(&rctx->framebuffer, state); + + /* build states */ + rctx->have_depth_fb = 0; + rctx->nr_cbufs = state->nr_cbufs; + for (int i = 0; i < state->nr_cbufs; i++) { + evergreen_cb(rctx, rstate, state, i); + } + evergreen_db(rctx, rstate, state); + + shader_mask = 0; + for (int i = 0; i < state->nr_cbufs; i++) { + shader_mask |= 0xf << (i * 4); + } + tl_x = 0; + tl_y = 0; + br_x = state->width; + br_y = state->height; +#if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */ + /* EG hw workaround */ + if (br_x == 0) + tl_x = 1; + if (br_y == 0) + tl_y = 1; + /* cayman hw workaround */ + if (rctx->chip_class == CAYMAN) { + if (br_x == 1 && br_y == 1) + br_x = 2; + } +#endif + tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); + br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); + + r600_pipe_state_add_reg(rstate, + R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028244_PA_SC_GENERIC_SCISSOR_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028034_PA_SC_SCREEN_SCISSOR_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028208_PA_SC_WINDOW_SCISSOR_BR, br, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, + NULL, 0); + + r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, + shader_mask, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG, + 0x00000000, NULL, 0); + + free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); + rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; + r600_context_pipe_state_set(rctx, rstate); + + if (state->zsbuf) { + cayman_polygon_offset_update(rctx); + } +} + +void cayman_init_state_functions(struct r600_context *rctx) +{ + rctx->context.create_blend_state = evergreen_create_blend_state; + rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state; + rctx->context.create_fs_state = si_create_shader_state; + rctx->context.create_rasterizer_state = evergreen_create_rs_state; + rctx->context.create_sampler_state = si_create_sampler_state; + rctx->context.create_sampler_view = evergreen_create_sampler_view; + rctx->context.create_vertex_elements_state = si_create_vertex_elements; + rctx->context.create_vs_state = si_create_shader_state; + rctx->context.bind_blend_state = r600_bind_blend_state; + rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; + rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler; + rctx->context.bind_fs_state = r600_bind_ps_shader; + rctx->context.bind_rasterizer_state = r600_bind_rs_state; + rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; + rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler; + rctx->context.bind_vs_state = r600_bind_vs_shader; + rctx->context.delete_blend_state = r600_delete_state; + rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; + rctx->context.delete_fs_state = r600_delete_ps_shader; + rctx->context.delete_rasterizer_state = r600_delete_rs_state; + rctx->context.delete_sampler_state = si_delete_sampler_state; + rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; + rctx->context.delete_vs_state = r600_delete_vs_shader; + rctx->context.set_blend_color = evergreen_set_blend_color; + rctx->context.set_clip_state = evergreen_set_clip_state; + rctx->context.set_constant_buffer = r600_set_constant_buffer; + rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view; + rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state; + rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple; + rctx->context.set_sample_mask = evergreen_set_sample_mask; + rctx->context.set_scissor_state = evergreen_set_scissor_state; + rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; + rctx->context.set_vertex_buffers = r600_set_vertex_buffers; + rctx->context.set_index_buffer = r600_set_index_buffer; + rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view; + rctx->context.set_viewport_state = evergreen_set_viewport_state; + rctx->context.sampler_view_destroy = r600_sampler_view_destroy; + rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; + rctx->context.texture_barrier = r600_texture_barrier; + rctx->context.create_stream_output_target = r600_create_so_target; + rctx->context.stream_output_target_destroy = r600_so_target_destroy; + rctx->context.set_stream_output_targets = r600_set_so_targets; +} + +void si_init_config(struct r600_context *rctx) +{ + struct r600_pipe_state *rstate = &rctx->config; + unsigned tmp; + + r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0); + + r600_pipe_state_add_reg(rstate, R_028804_DB_EQAA, 0x110000, NULL, 0); + r600_context_pipe_state_set(rctx, rstate); +} + +void cayman_polygon_offset_update(struct r600_context *rctx) +{ + struct r600_pipe_state state; + + state.id = R600_PIPE_STATE_POLYGON_OFFSET; + state.nregs = 0; + if (rctx->rasterizer && rctx->framebuffer.zsbuf) { + float offset_units = rctx->rasterizer->offset_units; + unsigned offset_db_fmt_cntl = 0, depth; + + switch (rctx->framebuffer.zsbuf->texture->format) { + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + depth = -24; + offset_units *= 2.0f; + break; + case PIPE_FORMAT_Z32_FLOAT: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + depth = -23; + offset_units *= 1.0f; + offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); + break; + case PIPE_FORMAT_Z16_UNORM: + depth = -16; + offset_units *= 4.0f; + break; + default: + return; + } + /* FIXME some of those reg can be computed with cso */ + offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); + r600_pipe_state_add_reg(&state, + R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, + fui(rctx->rasterizer->offset_scale), NULL, 0); + r600_pipe_state_add_reg(&state, + R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, + fui(offset_units), NULL, 0); + r600_pipe_state_add_reg(&state, + R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, + fui(rctx->rasterizer->offset_scale), NULL, 0); + r600_pipe_state_add_reg(&state, + R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, + fui(offset_units), NULL, 0); + r600_pipe_state_add_reg(&state, + R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, + offset_db_fmt_cntl, NULL, 0); + r600_context_pipe_state_set(rctx, &state); + } +} + +void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = &shader->rstate; + struct r600_shader *rshader = &shader->shader; + unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control; + int pos_index = -1, face_index = -1; + int ninterp = 0; + boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; + unsigned spi_baryc_cntl; + uint64_t va; + + if (si_pipe_shader_create(ctx, shader)) + return; + + rstate->nregs = 0; + + db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); + for (i = 0; i < rshader->ninput; i++) { + /* evergreen NUM_INTERP only contains values interpolated into the LDS, + POSITION goes via GPRs from the SC so isn't counted */ + if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) + pos_index = i; + else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) + face_index = i; + else { + ninterp++; + if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) + have_linear = TRUE; + if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) + have_perspective = TRUE; + if (rshader->input[i].centroid) + have_centroid = TRUE; + } + } + + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) + db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); + if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) + db_shader_control |= 0; // XXX OP_VAL or TEST_VAL? + } + if (rshader->uses_kill) + db_shader_control |= S_02880C_KILL_ENABLE(1); + + exports_ps = 0; + num_cout = 0; + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || + rshader->output[i].name == TGSI_SEMANTIC_STENCIL) + exports_ps |= 1; + else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { + if (rshader->fs_write_all) + num_cout = rshader->nr_cbufs; + else + num_cout++; + } + } + if (!exports_ps) { + /* always at least export 1 component per pixel */ + exports_ps = 2; + } + + if (ninterp == 0) { + ninterp = 1; + have_perspective = TRUE; + } + + if (!have_perspective && !have_linear) + have_perspective = TRUE; + + spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp); + + spi_baryc_cntl = 0; + if (have_perspective) + spi_baryc_cntl |= have_centroid ? + S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1); + if (have_linear) + spi_baryc_cntl |= have_centroid ? + S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1); + + r600_pipe_state_add_reg(rstate, + R_0286E0_SPI_BARYC_CNTL, + spi_baryc_cntl, + NULL, 0); + + r600_pipe_state_add_reg(rstate, + R_0286CC_SPI_PS_INPUT_ENA, + shader->spi_ps_input_ena, + NULL, 0); + + r600_pipe_state_add_reg(rstate, + R_0286D0_SPI_PS_INPUT_ADDR, + shader->spi_ps_input_ena, + NULL, 0); + + r600_pipe_state_add_reg(rstate, + R_0286D8_SPI_PS_IN_CONTROL, + spi_ps_in_control, + NULL, 0); + + /* XXX: Depends on Z buffer format? */ + r600_pipe_state_add_reg(rstate, + R_028710_SPI_SHADER_Z_FORMAT, + 0, + NULL, 0); + + /* XXX: Depends on color buffer format? */ + r600_pipe_state_add_reg(rstate, + R_028714_SPI_SHADER_COL_FORMAT, + S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR), + NULL, 0); + + va = r600_resource_va(ctx->screen, (void *)shader->bo); + r600_pipe_state_add_reg(rstate, + R_00B020_SPI_SHADER_PGM_LO_PS, + va >> 8, + shader->bo, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, + R_00B024_SPI_SHADER_PGM_HI_PS, + va >> 40, + shader->bo, RADEON_USAGE_READ); + + /* Last 2 reserved SGPRs are used for VCC */ + /* XXX: Hard-coding 2 SGPRs for constant buffer */ + r600_pipe_state_add_reg(rstate, + R_00B028_SPI_SHADER_PGM_RSRC1_PS, + S_00B028_VGPRS(shader->num_vgprs / 4) | + S_00B028_SGPRS((shader->num_sgprs + 2 + 2 + 1) / 8), + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_00B02C_SPI_SHADER_PGM_RSRC2_PS, + S_00B02C_USER_SGPR(6), + NULL, 0); + + r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, + db_shader_control, + NULL, 0); + + shader->sprite_coord_enable = rctx->sprite_coord_enable; +} + +void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = &shader->rstate; + struct r600_shader *rshader = &shader->shader; + unsigned nparams, i; + uint64_t va; + + if (si_pipe_shader_create(ctx, shader)) + return; + + /* clear previous register */ + rstate->nregs = 0; + + /* Certain attributes (position, psize, etc.) don't count as params. + * VS is required to export at least one param and r600_shader_from_tgsi() + * takes care of adding a dummy export. + */ + for (nparams = 0, i = 0 ; i < rshader->noutput; i++) { + if (rshader->output[i].name != TGSI_SEMANTIC_POSITION) + nparams++; + } + if (nparams < 1) + nparams = 1; + + r600_pipe_state_add_reg(rstate, + R_0286C4_SPI_VS_OUT_CONFIG, + S_0286C4_VS_EXPORT_COUNT(nparams - 1), + NULL, 0); + + r600_pipe_state_add_reg(rstate, + R_02870C_SPI_SHADER_POS_FORMAT, + S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | + S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | + S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | + S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP), + NULL, 0); + + va = r600_resource_va(ctx->screen, (void *)shader->bo); + r600_pipe_state_add_reg(rstate, + R_00B120_SPI_SHADER_PGM_LO_VS, + va >> 8, + shader->bo, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, + R_00B124_SPI_SHADER_PGM_HI_VS, + va >> 40, + shader->bo, RADEON_USAGE_READ); + + /* Last 2 reserved SGPRs are used for VCC */ + /* XXX: Hard-coding 2 SGPRs for constant buffer */ + r600_pipe_state_add_reg(rstate, + R_00B128_SPI_SHADER_PGM_RSRC1_VS, + S_00B128_VGPRS(shader->num_vgprs / 4) | + S_00B128_SGPRS((shader->num_sgprs + 2 + 2 + 2) / 8), + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_00B12C_SPI_SHADER_PGM_RSRC2_VS, + S_00B12C_USER_SGPR(2 + 2), + NULL, 0); +} + +void si_update_spi_map(struct r600_context *rctx) +{ + struct r600_shader *ps = &rctx->ps_shader->shader; + struct r600_shader *vs = &rctx->vs_shader->shader; + struct r600_pipe_state *rstate = &rctx->spi; + unsigned i, j, tmp; + + rstate->nregs = 0; + + for (i = 0; i < ps->ninput; i++) { + tmp = 0; + + if (ps->input[i].name == TGSI_SEMANTIC_COLOR || + ps->input[i].name == TGSI_SEMANTIC_BCOLOR || + ps->input[i].name == TGSI_SEMANTIC_POSITION) { + tmp |= S_028644_FLAT_SHADE(1); + } + + if (ps->input[i].name == TGSI_SEMANTIC_GENERIC && + rctx->sprite_coord_enable & (1 << ps->input[i].sid)) { + tmp |= S_028644_PT_SPRITE_TEX(1); + } + + for (j = 0; j < vs->noutput; j++) { + if (ps->input[i].name == vs->output[j].name && + ps->input[i].sid == vs->output[j].sid) { + tmp |= S_028644_OFFSET(ps->input[i].sid); + break; + } + } + + if (j == vs->noutput) { + /* No corresponding output found, load defaults into input */ + tmp |= S_028644_OFFSET(0x20); + } + + r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, + tmp, NULL, 0); + } + + if (rstate->nregs > 0) + r600_context_pipe_state_set(rctx, rstate); +} + +void *cayman_create_db_flush_dsa(struct r600_context *rctx) +{ + struct pipe_depth_stencil_alpha_state dsa; + struct r600_pipe_state *rstate; + + memset(&dsa, 0, sizeof(dsa)); + + rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); + r600_pipe_state_add_reg(rstate, + R_028000_DB_RENDER_CONTROL, + S_028000_DEPTH_COPY(1) | + S_028000_STENCIL_COPY(1) | + S_028000_COPY_CENTROID(1), + NULL, 0); + return rstate; +} diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h new file mode 100644 index 00000000000..56915ab966f --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600.h @@ -0,0 +1,245 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600_H +#define R600_H + +#include "../../winsys/radeon/drm/radeon_winsys.h" +#include "util/u_double_list.h" +#include "util/u_vbuf.h" + +#define R600_ERR(fmt, args...) \ + fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) + +struct winsys_handle; + +enum radeon_family { + CHIP_UNKNOWN, + CHIP_CAYMAN, + CHIP_TAHITI, + CHIP_PITCAIRN, + CHIP_VERDE, + CHIP_LAST, +}; + +enum chip_class { + CAYMAN, + TAHITI, +}; + +struct r600_tiling_info { + unsigned num_channels; + unsigned num_banks; + unsigned group_bytes; +}; + +struct r600_resource { + struct u_vbuf_resource b; + + /* Winsys objects. */ + struct pb_buffer *buf; + struct radeon_winsys_cs_handle *cs_buf; + + /* Resource state. */ + unsigned domains; +}; + +/* R600/R700 STATES */ +#define R600_GROUP_MAX 16 +#define R600_BLOCK_MAX_BO 32 +#define R600_BLOCK_MAX_REG 128 + +/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ +/* there is a block entry for each register so 512 blocks */ +/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ +/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ +#define RANGE_OFFSET_START 0x8000 +#define HASH_SHIFT 9 +#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ + +#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) +#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) + +struct r600_pipe_reg { + uint32_t value; + struct r600_block *block; + struct r600_resource *bo; + enum radeon_bo_usage bo_usage; + uint32_t id; +}; + +struct r600_pipe_state { + unsigned id; + unsigned nregs; + struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; +}; + +#define R600_BLOCK_STATUS_ENABLED (1 << 0) +#define R600_BLOCK_STATUS_DIRTY (1 << 1) + +struct r600_block_reloc { + struct r600_resource *bo; + enum radeon_bo_usage bo_usage; + unsigned bo_pm4_index; +}; + +struct r600_block { + struct list_head list; + struct list_head enable_list; + unsigned status; + unsigned flags; + unsigned start_offset; + unsigned pm4_ndwords; + unsigned nbo; + uint16_t nreg; + uint16_t nreg_dirty; + uint32_t *reg; + uint32_t pm4[R600_BLOCK_MAX_REG]; + unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; + struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; +}; + +struct r600_range { + struct r600_block **blocks; +}; + +struct r600_query { + union { + uint64_t u64; + boolean b; + struct pipe_query_data_so_statistics so; + } result; + /* The kind of query */ + unsigned type; + /* Offset of the first result for current query */ + unsigned results_start; + /* Offset of the next free result after current query data */ + unsigned results_end; + /* Size of the result in memory for both begin_query and end_query, + * this can be one or two numbers, or it could even be a size of a structure. */ + unsigned result_size; + /* The buffer where query results are stored. It's used as a ring, + * data blocks for current query are stored sequentially from + * results_start to results_end, with wrapping on the buffer end */ + struct r600_resource *buffer; + /* The number of dwords for begin_query or end_query. */ + unsigned num_cs_dw; + /* linked list of queries */ + struct list_head list; +}; + +struct r600_so_target { + struct pipe_stream_output_target b; + + /* The buffer where BUFFER_FILLED_SIZE is stored. */ + struct r600_resource *filled_size; + unsigned stride; + unsigned so_index; +}; + +#define R600_CONTEXT_DRAW_PENDING (1 << 0) +#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) +#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) + +struct r600_draw { + uint32_t vgt_num_indices; + uint32_t vgt_num_instances; + uint32_t vgt_index_type; + uint32_t vgt_draw_initiator; + uint32_t indices_bo_offset; + unsigned db_render_override; + unsigned db_render_control; + struct r600_resource *indices; +}; + +struct r600_context; +struct r600_screen; + +void r600_get_backend_mask(struct r600_context *ctx); +void r600_context_fini(struct r600_context *ctx); +void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); +void r600_context_flush(struct r600_context *ctx, unsigned flags); +void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); + +struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); +void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); +boolean r600_context_query_result(struct r600_context *ctx, + struct r600_query *query, + boolean wait, void *vresult); +void r600_query_begin(struct r600_context *ctx, struct r600_query *query); +void r600_query_end(struct r600_context *ctx, struct r600_query *query); +void r600_context_queries_suspend(struct r600_context *ctx); +void r600_context_queries_resume(struct r600_context *ctx); +void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, + int flag_wait); +void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, + unsigned offset, unsigned value); +void r600_inval_shader_cache(struct r600_context *ctx); +void r600_inval_texture_cache(struct r600_context *ctx); +void r600_inval_vertex_cache(struct r600_context *ctx); +void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now); + +void r600_context_streamout_begin(struct r600_context *ctx); +void r600_context_streamout_end(struct r600_context *ctx); +void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t); +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block); +void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block); + +int si_context_init(struct r600_context *ctx); +void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); + +void _r600_pipe_state_add_reg(struct r600_context *ctx, + struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + uint32_t range_id, uint32_t block_id, + struct r600_resource *bo, + enum radeon_bo_usage usage); + +void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + struct r600_resource *bo, + enum radeon_bo_usage usage); + +#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage) + +static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, + uint32_t value) +{ + state->regs[state->nregs].value = value; + state->nregs++; +} + +static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, + uint32_t value, struct r600_resource *bo, + enum radeon_bo_usage usage) +{ + state->regs[state->nregs].value = value; + state->regs[state->nregs].bo = bo; + state->regs[state->nregs].bo_usage = usage; + state->nregs++; +} + +#endif diff --git a/src/gallium/drivers/radeonsi/r600_blit.c b/src/gallium/drivers/radeonsi/r600_blit.c new file mode 100644 index 00000000000..65158089acb --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_blit.c @@ -0,0 +1,379 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include "util/u_surface.h" +#include "util/u_blitter.h" +#include "util/u_format.h" +#include "radeonsi_pipe.h" + +enum r600_blitter_op /* bitmask */ +{ + R600_SAVE_TEXTURES = 1, + R600_SAVE_FRAMEBUFFER = 2, + R600_DISABLE_RENDER_COND = 4, + + R600_CLEAR = 0, + + R600_CLEAR_SURFACE = R600_SAVE_FRAMEBUFFER, + + R600_COPY = R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES | + R600_DISABLE_RENDER_COND, + + R600_DECOMPRESS = R600_SAVE_FRAMEBUFFER | R600_DISABLE_RENDER_COND, +}; + +static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + r600_context_queries_suspend(rctx); + + util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]); + util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]); + if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) { + util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref); + } + util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]); + util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); + util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); + util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements); + if (rctx->states[R600_PIPE_STATE_VIEWPORT]) { + util_blitter_save_viewport(rctx->blitter, &rctx->viewport); + } + util_blitter_save_vertex_buffers(rctx->blitter, + rctx->vbuf_mgr->nr_vertex_buffers, + rctx->vbuf_mgr->vertex_buffer); + util_blitter_save_so_targets(rctx->blitter, rctx->num_so_targets, + (struct pipe_stream_output_target**)rctx->so_targets); + + if (op & R600_SAVE_FRAMEBUFFER) + util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer); + + if (op & R600_SAVE_TEXTURES) { + util_blitter_save_fragment_sampler_states( + rctx->blitter, rctx->ps_samplers.n_samplers, + (void**)rctx->ps_samplers.samplers); + + util_blitter_save_fragment_sampler_views( + rctx->blitter, rctx->ps_samplers.n_views, + (struct pipe_sampler_view**)rctx->ps_samplers.views); + } + + if ((op & R600_DISABLE_RENDER_COND) && rctx->current_render_cond) { + rctx->saved_render_cond = rctx->current_render_cond; + rctx->saved_render_cond_mode = rctx->current_render_cond_mode; + rctx->context.render_condition(&rctx->context, NULL, 0); + } + +} + +static void r600_blitter_end(struct pipe_context *ctx) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + if (rctx->saved_render_cond) { + rctx->context.render_condition(&rctx->context, + rctx->saved_render_cond, + rctx->saved_render_cond_mode); + rctx->saved_render_cond = NULL; + } + r600_context_queries_resume(rctx); +} + +static unsigned u_num_layers(struct pipe_resource *r, unsigned level) +{ + switch (r->target) { + case PIPE_TEXTURE_CUBE: + return 6; + case PIPE_TEXTURE_3D: + return u_minify(r->depth0, level); + case PIPE_TEXTURE_1D_ARRAY: + return r->array_size; + case PIPE_TEXTURE_2D_ARRAY: + return r->array_size; + default: + return 1; + } +} + +void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + unsigned layer, level; + float depth = 1.0f; + + if (!texture->dirty_db) + return; + + for (level = 0; level <= texture->resource.b.b.b.last_level; level++) { + unsigned num_layers = u_num_layers(&texture->resource.b.b.b, level); + + for (layer = 0; layer < num_layers; layer++) { + struct pipe_surface *zsurf, *cbsurf, surf_tmpl; + + surf_tmpl.format = texture->real_format; + surf_tmpl.u.tex.level = level; + surf_tmpl.u.tex.first_layer = layer; + surf_tmpl.u.tex.last_layer = layer; + surf_tmpl.usage = PIPE_BIND_DEPTH_STENCIL; + + zsurf = ctx->create_surface(ctx, &texture->resource.b.b.b, &surf_tmpl); + + surf_tmpl.format = texture->flushed_depth_texture->real_format; + surf_tmpl.usage = PIPE_BIND_RENDER_TARGET; + cbsurf = ctx->create_surface(ctx, + (struct pipe_resource*)texture->flushed_depth_texture, &surf_tmpl); + + r600_blitter_begin(ctx, R600_DECOMPRESS); + util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth); + r600_blitter_end(ctx); + + pipe_surface_reference(&zsurf, NULL); + pipe_surface_reference(&cbsurf, NULL); + } + } + + texture->dirty_db = FALSE; +} + +void r600_flush_depth_textures(struct r600_context *rctx) +{ + unsigned int i; + + /* FIXME: This handles fragment shader textures only. */ + + for (i = 0; i < rctx->ps_samplers.n_views; ++i) { + struct si_pipe_sampler_view *view; + struct r600_resource_texture *tex; + + view = rctx->ps_samplers.views[i]; + if (!view) continue; + + tex = (struct r600_resource_texture *)view->base.texture; + if (!tex->depth) + continue; + + if (tex->is_flushing_texture) + continue; + + r600_blit_uncompress_depth(&rctx->context, tex); + } + + /* also check CB here */ + for (i = 0; i < rctx->framebuffer.nr_cbufs; i++) { + struct r600_resource_texture *tex; + tex = (struct r600_resource_texture *)rctx->framebuffer.cbufs[i]->texture; + + if (!tex->depth) + continue; + + if (tex->is_flushing_texture) + continue; + + r600_blit_uncompress_depth(&rctx->context, tex); + } +} + +static void r600_clear(struct pipe_context *ctx, unsigned buffers, + const union pipe_color_union *color, + double depth, unsigned stencil) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct pipe_framebuffer_state *fb = &rctx->framebuffer; + + r600_blitter_begin(ctx, R600_CLEAR); + util_blitter_clear(rctx->blitter, fb->width, fb->height, + fb->nr_cbufs, buffers, fb->nr_cbufs ? fb->cbufs[0]->format : PIPE_FORMAT_NONE, + color, depth, stencil); + r600_blitter_end(ctx); +} + +static void r600_clear_render_target(struct pipe_context *ctx, + struct pipe_surface *dst, + const union pipe_color_union *color, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + r600_blitter_begin(ctx, R600_CLEAR_SURFACE); + util_blitter_clear_render_target(rctx->blitter, dst, color, + dstx, dsty, width, height); + r600_blitter_end(ctx); +} + +static void r600_clear_depth_stencil(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned clear_flags, + double depth, + unsigned stencil, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + r600_blitter_begin(ctx, R600_CLEAR_SURFACE); + util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, + dstx, dsty, width, height); + r600_blitter_end(ctx); +} + + + +/* Copy a block of pixels from one surface to another using HW. */ +static void r600_hw_copy_region(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dstx, unsigned dsty, unsigned dstz, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + r600_blitter_begin(ctx, R600_COPY); + util_blitter_copy_texture(rctx->blitter, dst, dst_level, dstx, dsty, dstz, + src, src_level, src_box, TRUE); + r600_blitter_end(ctx); +} + +struct texture_orig_info { + unsigned format; + unsigned width0; + unsigned height0; +}; + +static void r600_compressed_to_blittable(struct pipe_resource *tex, + unsigned level, + struct texture_orig_info *orig) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex; + unsigned pixsize = util_format_get_blocksize(rtex->real_format); + int new_format; + int new_height, new_width; + + orig->format = tex->format; + orig->width0 = tex->width0; + orig->height0 = tex->height0; + + if (pixsize == 8) + new_format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */ + else + new_format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */ + + new_width = util_format_get_nblocksx(tex->format, orig->width0); + new_height = util_format_get_nblocksy(tex->format, orig->height0); + + tex->width0 = new_width; + tex->height0 = new_height; + tex->format = new_format; +} + +static void r600_reset_blittable_to_compressed(struct pipe_resource *tex, + struct texture_orig_info *orig) +{ + tex->format = orig->format; + tex->width0 = orig->width0; + tex->height0 = orig->height0; +} + +static void r600_resource_copy_region(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dstx, unsigned dsty, unsigned dstz, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box) +{ + struct r600_resource_texture *rsrc = (struct r600_resource_texture*)src; + struct texture_orig_info orig_info[2]; + struct pipe_box sbox; + const struct pipe_box *psbox; + boolean restore_orig[2]; + + memset(orig_info, 0, sizeof(orig_info)); + + /* Fallback for buffers. */ + if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { + util_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, + src, src_level, src_box); + return; + } + + if (rsrc->depth && !rsrc->is_flushing_texture) + r600_texture_depth_flush(ctx, src, FALSE); + + restore_orig[0] = restore_orig[1] = FALSE; + + if (util_format_is_compressed(src->format)) { + r600_compressed_to_blittable(src, src_level, &orig_info[0]); + restore_orig[0] = TRUE; + sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x); + sbox.y = util_format_get_nblocksy(orig_info[0].format, src_box->y); + sbox.z = src_box->z; + sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width); + sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height); + sbox.depth = src_box->depth; + psbox=&sbox; + } else + psbox=src_box; + + if (util_format_is_compressed(dst->format)) { + r600_compressed_to_blittable(dst, dst_level, &orig_info[1]); + restore_orig[1] = TRUE; + /* translate the dst box as well */ + dstx = util_format_get_nblocksx(orig_info[1].format, dstx); + dsty = util_format_get_nblocksy(orig_info[1].format, dsty); + } + + r600_hw_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, + src, src_level, psbox); + + if (restore_orig[0]) + r600_reset_blittable_to_compressed(src, &orig_info[0]); + + if (restore_orig[1]) + r600_reset_blittable_to_compressed(dst, &orig_info[1]); +} + +void r600_init_blit_functions(struct r600_context *rctx) +{ + rctx->context.clear = r600_clear; + rctx->context.clear_render_target = r600_clear_render_target; + rctx->context.clear_depth_stencil = r600_clear_depth_stencil; + rctx->context.resource_copy_region = r600_resource_copy_region; +} + +void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture) +{ + struct pipe_box sbox; + + sbox.x = sbox.y = sbox.z = 0; + sbox.width = texture->resource.b.b.b.width0; + sbox.height = texture->resource.b.b.b.height0; + /* XXX that might be wrong */ + sbox.depth = 1; + + r600_hw_copy_region(ctx, (struct pipe_resource *)texture, 0, + 0, 0, 0, + (struct pipe_resource *)texture->flushed_depth_texture, 0, + &sbox); +} diff --git a/src/gallium/drivers/radeonsi/r600_buffer.c b/src/gallium/drivers/radeonsi/r600_buffer.c new file mode 100644 index 00000000000..bb885df8dcd --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_buffer.c @@ -0,0 +1,282 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson <MostAwesomeDude@gmail.com> + */ +#include <byteswap.h> + +#include "pipe/p_screen.h" +#include "util/u_format.h" +#include "util/u_math.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include "util/u_upload_mgr.h" + +#include "r600.h" +#include "radeonsi_pipe.h" + +static void r600_buffer_destroy(struct pipe_screen *screen, + struct pipe_resource *buf) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct r600_resource *rbuffer = r600_resource(buf); + + pb_reference(&rbuffer->buf, NULL); + util_slab_free(&rscreen->pool_buffers, rbuffer); +} + +static struct pipe_transfer *r600_get_transfer(struct pipe_context *ctx, + struct pipe_resource *resource, + unsigned level, + unsigned usage, + const struct pipe_box *box) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers); + + transfer->resource = resource; + transfer->level = level; + transfer->usage = usage; + transfer->box = *box; + transfer->stride = 0; + transfer->layer_stride = 0; + transfer->data = NULL; + + /* Note strides are zero, this is ok for buffers, but not for + * textures 2d & higher at least. + */ + return transfer; +} + +static void *r600_buffer_transfer_map(struct pipe_context *pipe, + struct pipe_transfer *transfer) +{ + struct r600_resource *rbuffer = r600_resource(transfer->resource); + struct r600_context *rctx = (struct r600_context*)pipe; + uint8_t *data; + + if (rbuffer->b.user_ptr) + return (uint8_t*)rbuffer->b.user_ptr + transfer->box.x; + + data = rctx->ws->buffer_map(rbuffer->buf, rctx->cs, transfer->usage); + if (!data) + return NULL; + + return (uint8_t*)data + transfer->box.x; +} + +static void r600_buffer_transfer_unmap(struct pipe_context *pipe, + struct pipe_transfer *transfer) +{ + struct r600_resource *rbuffer = r600_resource(transfer->resource); + struct r600_context *rctx = (struct r600_context*)pipe; + + if (rbuffer->b.user_ptr) + return; + + rctx->ws->buffer_unmap(rbuffer->buf); +} + +static void r600_buffer_transfer_flush_region(struct pipe_context *pipe, + struct pipe_transfer *transfer, + const struct pipe_box *box) +{ +} + +static void r600_transfer_destroy(struct pipe_context *ctx, + struct pipe_transfer *transfer) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + util_slab_free(&rctx->pool_transfers, transfer); +} + +static void r600_buffer_transfer_inline_write(struct pipe_context *pipe, + struct pipe_resource *resource, + unsigned level, + unsigned usage, + const struct pipe_box *box, + const void *data, + unsigned stride, + unsigned layer_stride) +{ + struct r600_context *rctx = (struct r600_context*)pipe; + struct r600_resource *rbuffer = r600_resource(resource); + uint8_t *map = NULL; + + assert(rbuffer->b.user_ptr == NULL); + + map = rctx->ws->buffer_map(rbuffer->buf, rctx->cs, + PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_RANGE | usage); + + memcpy(map + box->x, data, box->width); + + rctx->ws->buffer_unmap(rbuffer->buf); +} + +static const struct u_resource_vtbl r600_buffer_vtbl = +{ + u_default_resource_get_handle, /* get_handle */ + r600_buffer_destroy, /* resource_destroy */ + r600_get_transfer, /* get_transfer */ + r600_transfer_destroy, /* transfer_destroy */ + r600_buffer_transfer_map, /* transfer_map */ + r600_buffer_transfer_flush_region, /* transfer_flush_region */ + r600_buffer_transfer_unmap, /* transfer_unmap */ + r600_buffer_transfer_inline_write /* transfer_inline_write */ +}; + +bool r600_init_resource(struct r600_screen *rscreen, + struct r600_resource *res, + unsigned size, unsigned alignment, + unsigned bind, unsigned usage) +{ + uint32_t initial_domain, domains; + + /* Staging resources particpate in transfers and blits only + * and are used for uploads and downloads from regular + * resources. We generate them internally for some transfers. + */ + if (usage == PIPE_USAGE_STAGING) { + domains = RADEON_DOMAIN_GTT; + initial_domain = RADEON_DOMAIN_GTT; + } else { + domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; + + switch(usage) { + case PIPE_USAGE_DYNAMIC: + case PIPE_USAGE_STREAM: + case PIPE_USAGE_STAGING: + initial_domain = RADEON_DOMAIN_GTT; + break; + case PIPE_USAGE_DEFAULT: + case PIPE_USAGE_STATIC: + case PIPE_USAGE_IMMUTABLE: + default: + initial_domain = RADEON_DOMAIN_VRAM; + break; + } + } + + res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, bind, initial_domain); + if (!res->buf) { + return false; + } + + res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf); + res->domains = domains; + return true; +} + +struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, + const struct pipe_resource *templ) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct r600_resource *rbuffer; + /* XXX We probably want a different alignment for buffers and textures. */ + unsigned alignment = 4096; + + rbuffer = util_slab_alloc(&rscreen->pool_buffers); + + rbuffer->b.b.b = *templ; + pipe_reference_init(&rbuffer->b.b.b.reference, 1); + rbuffer->b.b.b.screen = screen; + rbuffer->b.b.vtbl = &r600_buffer_vtbl; + rbuffer->b.user_ptr = NULL; + + if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, templ->bind, templ->usage)) { + util_slab_free(&rscreen->pool_buffers, rbuffer); + return NULL; + } + return &rbuffer->b.b.b; +} + +struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, + void *ptr, unsigned bytes, + unsigned bind) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct r600_resource *rbuffer; + + rbuffer = util_slab_alloc(&rscreen->pool_buffers); + + pipe_reference_init(&rbuffer->b.b.b.reference, 1); + rbuffer->b.b.vtbl = &r600_buffer_vtbl; + rbuffer->b.b.b.screen = screen; + rbuffer->b.b.b.target = PIPE_BUFFER; + rbuffer->b.b.b.format = PIPE_FORMAT_R8_UNORM; + rbuffer->b.b.b.usage = PIPE_USAGE_IMMUTABLE; + rbuffer->b.b.b.bind = bind; + rbuffer->b.b.b.width0 = bytes; + rbuffer->b.b.b.height0 = 1; + rbuffer->b.b.b.depth0 = 1; + rbuffer->b.b.b.array_size = 1; + rbuffer->b.b.b.flags = 0; + rbuffer->b.user_ptr = ptr; + rbuffer->buf = NULL; + return &rbuffer->b.b.b; +} + +void r600_upload_index_buffer(struct r600_context *rctx, + struct pipe_index_buffer *ib, unsigned count) +{ + struct r600_resource *rbuffer = r600_resource(ib->buffer); + + u_upload_data(rctx->vbuf_mgr->uploader, 0, count * ib->index_size, + rbuffer->b.user_ptr, &ib->offset, &ib->buffer); +} + +void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer, + uint32_t *const_offset) +{ + if ((*rbuffer)->b.user_ptr) { + uint8_t *ptr = (*rbuffer)->b.user_ptr; + unsigned size = (*rbuffer)->b.b.b.width0; + + *rbuffer = NULL; + + if (R600_BIG_ENDIAN) { + uint32_t *tmpPtr; + unsigned i; + + if (!(tmpPtr = malloc(size))) { + R600_ERR("Failed to allocate BE swap buffer.\n"); + return; + } + + for (i = 0; i < size / 4; ++i) { + tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); + } + + u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, const_offset, + (struct pipe_resource**)rbuffer); + + free(tmpPtr); + } else { + u_upload_data(rctx->vbuf_mgr->uploader, 0, size, ptr, const_offset, + (struct pipe_resource**)rbuffer); + } + } else { + *const_offset = 0; + } +} diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c new file mode 100644 index 00000000000..494b0d34283 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c @@ -0,0 +1,1151 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include "r600_hw_context_priv.h" +#include "radeonsi_pipe.h" +#include "sid.h" +#include "util/u_memory.h" +#include <errno.h> + +#define GROUP_FORCE_NEW_BLOCK 0 + +/* Get backends mask */ +void r600_get_backend_mask(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + struct r600_resource *buffer; + uint32_t *results; + unsigned num_backends = ctx->screen->info.r600_num_backends; + unsigned i, mask = 0; + + /* if backend_map query is supported by the kernel */ + if (ctx->screen->info.r600_backend_map_valid) { + unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; + unsigned backend_map = ctx->screen->info.r600_backend_map; + unsigned item_width, item_mask; + + if (ctx->chip_class >= CAYMAN) { + item_width = 4; + item_mask = 0x7; + } + + while(num_tile_pipes--) { + i = backend_map & item_mask; + mask |= (1<<i); + backend_map >>= item_width; + } + if (mask != 0) { + ctx->backend_mask = mask; + return; + } + } + + /* otherwise backup path for older kernels */ + + /* create buffer for event data */ + buffer = (struct r600_resource*) + pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, + PIPE_USAGE_STAGING, ctx->max_db*16); + if (!buffer) + goto err; + + /* initialize buffer with zeroes */ + results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); + if (results) { + uint64_t va = 0; + + memset(results, 0, ctx->max_db * 4 * 4); + ctx->ws->buffer_unmap(buffer->buf); + + /* emit EVENT_WRITE for ZPASS_DONE */ + va = r600_resource_va(&ctx->screen->screen, (void *)buffer); + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = va >> 32; + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); + + /* analyze results */ + results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ); + if (results) { + for(i = 0; i < ctx->max_db; i++) { + /* at least highest bit will be set if backend is used */ + if (results[i*4 + 1]) + mask |= (1<<i); + } + ctx->ws->buffer_unmap(buffer->buf); + } + } + + pipe_resource_reference((struct pipe_resource**)&buffer, NULL); + + if (mask != 0) { + ctx->backend_mask = mask; + return; + } + +err: + /* fallback to old method - set num_backends lower bits to 1 */ + ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); + return; +} + +static inline void r600_context_ps_partial_flush(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + + if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) + return; + + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + + ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; +} + +void r600_init_cs(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + + /* All asics require this one */ + cs->buf[cs->cdw++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0); + cs->buf[cs->cdw++] = 0x80000000; + cs->buf[cs->cdw++] = 0x80000000; + + ctx->init_dwords = cs->cdw; +} + +static void r600_init_block(struct r600_context *ctx, + struct r600_block *block, + const struct r600_reg *reg, int index, int nreg, + unsigned opcode, unsigned offset_base) +{ + int i = index; + int j, n = nreg; + + /* initialize block */ + block->flags = 0; + block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ + block->start_offset = reg[i].offset; + block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); + block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; + block->reg = &block->pm4[block->pm4_ndwords]; + block->pm4_ndwords += n; + block->nreg = n; + block->nreg_dirty = n; + LIST_INITHEAD(&block->list); + LIST_INITHEAD(&block->enable_list); + + for (j = 0; j < n; j++) { + if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { + block->flags |= REG_FLAG_DIRTY_ALWAYS; + } + if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { + if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); + LIST_ADDTAIL(&block->list,&ctx->dirty); + } + } + if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { + block->flags |= REG_FLAG_FLUSH_CHANGE; + } + + if (reg[i+j].flags & REG_FLAG_NEED_BO) { + block->nbo++; + assert(block->nbo < R600_BLOCK_MAX_BO); + block->pm4_bo_index[j] = block->nbo; + block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0); + block->pm4[block->pm4_ndwords++] = 0x00000000; + block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; + } + } + /* check that we stay in limit */ + assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); +} + +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base) +{ + struct r600_block *block; + struct r600_range *range; + int offset; + + for (unsigned i = 0, n = 0; i < nreg; i += n) { + /* ignore new block balise */ + if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { + n = 1; + continue; + } + + /* register that need relocation are in their own group */ + /* find number of consecutive registers */ + n = 0; + offset = reg[i].offset; + while (reg[i + n].offset == offset) { + n++; + offset += 4; + if ((n + i) >= nreg) + break; + if (n >= (R600_BLOCK_MAX_REG - 2)) + break; + } + + /* allocate new block */ + block = calloc(1, sizeof(struct r600_block)); + if (block == NULL) { + return -ENOMEM; + } + ctx->nblocks++; + for (int j = 0; j < n; j++) { + range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)]; + /* create block table if it doesn't exist */ + if (!range->blocks) + range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); + if (!range->blocks) + return -1; + + range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block; + } + + r600_init_block(ctx, block, reg, i, n, opcode, offset_base); + + } + return 0; +} + + +/* initialize */ +void r600_context_fini(struct r600_context *ctx) +{ + struct r600_block *block; + struct r600_range *range; + + for (int i = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0; j < (1 << HASH_SHIFT); j++) { + block = ctx->range[i].blocks[j]; + if (block) { + for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { + range = &ctx->range[CTX_RANGE_ID(offset)]; + range->blocks[CTX_BLOCK_ID(offset)] = NULL; + } + for (int k = 1; k <= block->nbo; k++) { + pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); + } + free(block); + } + } + free(ctx->range[i].blocks); + } + free(ctx->range); + free(ctx->blocks); + ctx->ws->cs_destroy(ctx->cs); +} + +int r600_setup_block_table(struct r600_context *ctx) +{ + /* setup block table */ + int c = 0; + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + if (!ctx->blocks) + return -ENOMEM; + for (int i = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { + if (!ctx->range[i].blocks[j]) + continue; + + add = 1; + for (int k = 0; k < c; k++) { + if (ctx->blocks[k] == ctx->range[i].blocks[j]) { + add = 0; + break; + } + } + if (add) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg) - 1; + } + } + } + + return 0; +} + +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, + boolean count_draw_in) +{ + struct r600_atom *state; + + /* The number of dwords we already used in the CS so far. */ + num_dw += ctx->cs->cdw; + + if (count_draw_in) { + /* The number of dwords all the dirty states would take. */ + LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) { + num_dw += state->num_dw; + } + + num_dw += ctx->pm4_dirty_cdwords; + + /* The upper-bound of how much a draw command would take. */ + num_dw += R600_MAX_DRAW_CS_DWORDS; + } + + /* Count in queries_suspend. */ + num_dw += ctx->num_cs_dw_queries_suspend; + + /* Count in streamout_end at the end of CS. */ + num_dw += ctx->num_cs_dw_streamout_end; + + /* Count in render_condition(NULL) at the end of CS. */ + if (ctx->predicate_drawing) { + num_dw += 3; + } + + /* Count in framebuffer cache flushes at the end of CS. */ + num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */ + + /* Save 16 dwords for the fence mechanism. */ + num_dw += 16; + + /* Flush if there's not enough space. */ + if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { + radeonsi_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); + } +} + +void r600_context_dirty_block(struct r600_context *ctx, + struct r600_block *block, + int dirty, int index) +{ + if ((index + 1) > block->nreg_dirty) + block->nreg_dirty = index + 1; + + if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords; + if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); + } + LIST_ADDTAIL(&block->list,&ctx->dirty); + + if (block->flags & REG_FLAG_FLUSH_CHANGE) { + r600_context_ps_partial_flush(ctx); + } + } +} + +void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) +{ + struct r600_block *block; + int dirty; + for (int i = 0; i < state->nregs; i++) { + unsigned id, reloc_id; + struct r600_pipe_reg *reg = &state->regs[i]; + + block = reg->block; + id = reg->id; + + dirty = block->status & R600_BLOCK_STATUS_DIRTY; + + if (reg->value != block->reg[id]) { + block->reg[id] = reg->value; + dirty |= R600_BLOCK_STATUS_DIRTY; + } + if (block->flags & REG_FLAG_DIRTY_ALWAYS) + dirty |= R600_BLOCK_STATUS_DIRTY; + if (block->pm4_bo_index[id]) { + /* find relocation */ + reloc_id = block->pm4_bo_index[id]; + pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b.b); + block->reloc[reloc_id].bo_usage = reg->bo_usage; + /* always force dirty for relocs for now */ + dirty |= R600_BLOCK_STATUS_DIRTY; + } + + if (dirty) + r600_context_dirty_block(ctx, block, dirty, id); + } +} + +struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(offset)]; + block = range->blocks[CTX_BLOCK_ID(offset)]; + offset -= block->start_offset; + id = block->pm4_bo_index[offset >> 2]; + if (block->reloc[id].bo) { + return block->reloc[id].bo; + } + return NULL; +} + +void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) +{ + struct radeon_winsys_cs *cs = ctx->cs; + int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS); + int cp_dwords = block->pm4_ndwords, start_dword = 0; + int new_dwords = 0; + int nbo = block->nbo; + + if (block->nreg_dirty == 0 && optional) { + goto out; + } + + if (nbo) { + ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; + + for (int j = 0; j < block->nreg; j++) { + if (block->pm4_bo_index[j]) { + /* find relocation */ + struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; + block->pm4[reloc->bo_pm4_index] = + r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); + nbo--; + if (nbo == 0) + break; + } + } + ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; + } + + optional &= (block->nreg_dirty != block->nreg); + if (optional) { + new_dwords = block->nreg_dirty; + start_dword = cs->cdw; + cp_dwords = new_dwords + 2; + } + memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4); + cs->cdw += cp_dwords; + + if (optional) { + uint32_t newword; + + newword = cs->buf[start_dword]; + newword &= PKT_COUNT_C; + newword |= PKT_COUNT_S(new_dwords); + cs->buf[start_dword] = newword; + } +out: + block->status ^= R600_BLOCK_STATUS_DIRTY; + block->nreg_dirty = 0; + LIST_DELINIT(&block->list); +} + +void r600_inval_shader_cache(struct r600_context *ctx) +{ + ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_ICACHE_ACTION_ENA(1); + ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_KCACHE_ACTION_ENA(1); + r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); +} + +void r600_inval_texture_cache(struct r600_context *ctx) +{ + ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); + r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); +} + +void r600_inval_vertex_cache(struct r600_context *ctx) +{ + /* Some GPUs don't have the vertex cache and must use the texture cache instead. */ + ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); + r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); +} + +void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now) +{ + if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) + return; + + ctx->atom_surface_sync.flush_flags |= + r600_get_cb_flush_flags(ctx) | + (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0); + + if (flush_now) { + r600_emit_atom(ctx, &ctx->atom_surface_sync.atom); + } else { + r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + } + + ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; +} + +void r600_context_flush(struct r600_context *ctx, unsigned flags) +{ + struct radeon_winsys_cs *cs = ctx->cs; + struct r600_block *enable_block = NULL; + bool queries_suspended = false; + bool streamout_suspended = false; + + if (cs->cdw == ctx->init_dwords) + return; + + /* suspend queries */ + if (ctx->num_cs_dw_queries_suspend) { + r600_context_queries_suspend(ctx); + queries_suspended = true; + } + + if (ctx->num_cs_dw_streamout_end) { + r600_context_streamout_end(ctx); + streamout_suspended = true; + } + + r600_flush_framebuffer(ctx, true); + + /* partial flush is needed to avoid lockups on some chips with user fences */ + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + + /* Flush the CS. */ + ctx->ws->cs_flush(ctx->cs, flags); + + ctx->pm4_dirty_cdwords = 0; + ctx->flags = 0; + + r600_init_cs(ctx); + + if (streamout_suspended) { + ctx->streamout_start = TRUE; + ctx->streamout_append_bitmask = ~0; + } + + /* resume queries */ + if (queries_suspended) { + r600_context_queries_resume(ctx); + } + + /* set all valid group as dirty so they get reemited on + * next draw command + */ + LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) { + if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) { + LIST_ADDTAIL(&enable_block->list,&ctx->dirty); + enable_block->status |= R600_BLOCK_STATUS_DIRTY; + } + ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords; + enable_block->nreg_dirty = enable_block->nreg; + } +} + +void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + r600_need_cs_space(ctx, 10, FALSE); + + va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); + va = va + (offset << 2); + + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ + /* DATA_SEL | INT_EN | ADDRESS_HI */ + cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = value; /* DATA_LO */ + cs->buf[cs->cdw++] = 0; /* DATA_HI */ + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); +} + +static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index, + bool test_status_bit) +{ + uint32_t *current_result = (uint32_t*)map; + uint64_t start, end; + + start = (uint64_t)current_result[start_index] | + (uint64_t)current_result[start_index+1] << 32; + end = (uint64_t)current_result[end_index] | + (uint64_t)current_result[end_index+1] << 32; + + if (!test_status_bit || + ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) { + return end - start; + } + return 0; +} + +static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait) +{ + unsigned results_base = query->results_start; + char *map; + + map = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, + PIPE_TRANSFER_READ | + (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); + if (!map) + return FALSE; + + /* count all results across all data blocks */ + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + while (results_base != query->results_end) { + query->result.u64 += + r600_query_read_result(map + results_base, 0, 2, true); + results_base = (results_base + 16) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_OCCLUSION_PREDICATE: + while (results_base != query->results_end) { + query->result.b = query->result.b || + r600_query_read_result(map + results_base, 0, 2, true) != 0; + results_base = (results_base + 16) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_TIME_ELAPSED: + while (results_base != query->results_end) { + query->result.u64 += + r600_query_read_result(map + results_base, 0, 2, false); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + /* SAMPLE_STREAMOUTSTATS stores this structure: + * { + * u64 NumPrimitivesWritten; + * u64 PrimitiveStorageNeeded; + * } + * We only need NumPrimitivesWritten here. */ + while (results_base != query->results_end) { + query->result.u64 += + r600_query_read_result(map + results_base, 2, 6, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_PRIMITIVES_GENERATED: + /* Here we read PrimitiveStorageNeeded. */ + while (results_base != query->results_end) { + query->result.u64 += + r600_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_SO_STATISTICS: + while (results_base != query->results_end) { + query->result.so.num_primitives_written += + r600_query_read_result(map + results_base, 2, 6, true); + query->result.so.primitives_storage_needed += + r600_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + } + break; + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + while (results_base != query->results_end) { + query->result.b = query->result.b || + r600_query_read_result(map + results_base, 2, 6, true) != + r600_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + } + break; + default: + assert(0); + } + + query->results_start = query->results_end; + ctx->ws->buffer_unmap(query->buffer->buf); + return TRUE; +} + +void r600_query_begin(struct r600_context *ctx, struct r600_query *query) +{ + struct radeon_winsys_cs *cs = ctx->cs; + unsigned new_results_end, i; + uint32_t *results; + uint64_t va; + + r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE); + + new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; + + /* collect current results if query buffer is full */ + if (new_results_end == query->results_start) { + r600_query_result(ctx, query, TRUE); + } + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); + if (results) { + results = (uint32_t*)((char*)results + query->results_end); + memset(results, 0, query->result_size); + + /* Set top bits for unused backends */ + for (i = 0; i < ctx->max_db; i++) { + if (!(ctx->backend_mask & (1<<i))) { + results[(i * 4)+1] = 0x80000000; + results[(i * 4)+3] = 0x80000000; + } + } + ctx->ws->buffer_unmap(query->buffer->buf); + } + break; + case PIPE_QUERY_TIME_ELAPSED: + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); + results = (uint32_t*)((char*)results + query->results_end); + memset(results, 0, query->result_size); + ctx->ws->buffer_unmap(query->buffer->buf); + break; + default: + assert(0); + } + + /* emit begin query */ + va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + va += query->results_end; + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); + cs->buf[cs->cdw++] = query->results_end; + cs->buf[cs->cdw++] = 0; + break; + case PIPE_QUERY_TIME_ELAPSED: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = 0; + break; + default: + assert(0); + } + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + + ctx->num_cs_dw_queries_suspend += query->num_cs_dw; +} + +void r600_query_end(struct r600_context *ctx, struct r600_query *query) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + /* emit end query */ + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + va += query->results_end + 8; + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); + cs->buf[cs->cdw++] = query->results_end + query->result_size/2; + cs->buf[cs->cdw++] = 0; + break; + case PIPE_QUERY_TIME_ELAPSED: + va += query->results_end + query->result_size/2; + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = 0; + break; + default: + assert(0); + } + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + + query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; + ctx->num_cs_dw_queries_suspend -= query->num_cs_dw; +} + +void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, + int flag_wait) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + if (operation == PREDICATION_OP_CLEAR) { + r600_need_cs_space(ctx, 3, FALSE); + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = PRED_OP(PREDICATION_OP_CLEAR); + } else { + unsigned results_base = query->results_start; + unsigned count; + uint32_t op; + + /* find count of the query data blocks */ + count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0; + count /= query->result_size; + + r600_need_cs_space(ctx, 5 * count, TRUE); + + op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | + (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); + va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + + /* emit predicate packets for all data blocks */ + while (results_base != query->results_end) { + cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); + cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL; + cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, + RADEON_USAGE_READ); + results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; + + /* set CONTINUE bit for all packets except the first */ + op |= PREDICATION_CONTINUE; + } + } +} + +struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) +{ + struct r600_query *query; + unsigned buffer_size = 4096; + + query = CALLOC_STRUCT(r600_query); + if (query == NULL) + return NULL; + + query->type = query_type; + + switch (query_type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + query->result_size = 16 * ctx->max_db; + query->num_cs_dw = 6; + break; + case PIPE_QUERY_TIME_ELAPSED: + query->result_size = 16; + query->num_cs_dw = 8; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + /* NumPrimitivesWritten, PrimitiveStorageNeeded. */ + query->result_size = 32; + query->num_cs_dw = 6; + break; + default: + assert(0); + FREE(query); + return NULL; + } + + /* adjust buffer size to simplify offsets wrapping math */ + buffer_size -= buffer_size % query->result_size; + + /* Queries are normally read by the CPU after + * being written by the gpu, hence staging is probably a good + * usage pattern. + */ + query->buffer = (struct r600_resource*) + pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size); + if (!query->buffer) { + FREE(query); + return NULL; + } + return query; +} + +void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) +{ + pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL); + free(query); +} + +boolean r600_context_query_result(struct r600_context *ctx, + struct r600_query *query, + boolean wait, void *vresult) +{ + boolean *result_b = (boolean*)vresult; + uint64_t *result_u64 = (uint64_t*)vresult; + struct pipe_query_data_so_statistics *result_so = + (struct pipe_query_data_so_statistics*)vresult; + + if (!r600_query_result(ctx, query, wait)) + return FALSE; + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + *result_u64 = query->result.u64; + break; + case PIPE_QUERY_OCCLUSION_PREDICATE: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + *result_b = query->result.b; + break; + case PIPE_QUERY_TIME_ELAPSED: + *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; + break; + case PIPE_QUERY_SO_STATISTICS: + *result_so = query->result.so; + break; + default: + assert(0); + } + return TRUE; +} + +void r600_context_queries_suspend(struct r600_context *ctx) +{ + struct r600_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { + r600_query_end(ctx, query); + } + assert(ctx->num_cs_dw_queries_suspend == 0); +} + +void r600_context_queries_resume(struct r600_context *ctx) +{ + struct r600_query *query; + + assert(ctx->num_cs_dw_queries_suspend == 0); + + LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { + r600_query_begin(ctx, query); + } +} + +void r600_context_streamout_begin(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + struct r600_so_target **t = ctx->so_targets; + unsigned *strides = ctx->vs_shader_so_strides; + unsigned buffer_en, i; + + buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) | + (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) | + (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) | + (ctx->num_so_targets >= 4 && t[3] ? 8 : 0); + + ctx->num_cs_dw_streamout_end = + 12 + /* flush_vgt_streamout */ + util_bitcount(buffer_en) * 8 + + 3; + + r600_need_cs_space(ctx, + 12 + /* flush_vgt_streamout */ + 6 + /* enables */ + util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + + util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + + ctx->num_cs_dw_streamout_end, TRUE); + + if (ctx->chip_class >= CAYMAN) { + evergreen_flush_vgt_streamout(ctx); + evergreen_set_streamout_enable(ctx, buffer_en); + } + + for (i = 0; i < ctx->num_so_targets; i++) { +#if 0 + if (t[i]) { + t[i]->stride = strides[i]; + t[i]->so_index = i; + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0); + cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + + 16*i - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = (t[i]->b.buffer_offset + + t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */ + cs->buf[cs->cdw++] = strides[i] >> 2; /* VTX_STRIDE (in DW) */ + cs->buf[cs->cdw++] = 0; /* BUFFER_BASE */ + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = + r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer), + RADEON_USAGE_WRITE); + + if (ctx->streamout_append_bitmask & (1 << i)) { + /* Append. */ + cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); + cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | + STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = 0; /* src address lo */ + cs->buf[cs->cdw++] = 0; /* src address hi */ + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = + r600_context_bo_reloc(ctx, t[i]->filled_size, + RADEON_USAGE_READ); + } else { + /* Start from the beginning. */ + cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); + cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | + STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */ + cs->buf[cs->cdw++] = 0; /* unused */ + } + } +#endif + } +} + +void r600_context_streamout_end(struct r600_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + struct r600_so_target **t = ctx->so_targets; + unsigned i, flush_flags = 0; + + evergreen_flush_vgt_streamout(ctx); + + for (i = 0; i < ctx->num_so_targets; i++) { +#if 0 + if (t[i]) { + cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); + cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | + STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) | + STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */ + cs->buf[cs->cdw++] = 0; /* dst address lo */ + cs->buf[cs->cdw++] = 0; /* dst address hi */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = 0; /* unused */ + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = + r600_context_bo_reloc(ctx, t[i]->filled_size, + RADEON_USAGE_WRITE); + + flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i; + } +#endif + } + + evergreen_set_streamout_enable(ctx, 0); + + ctx->atom_surface_sync.flush_flags |= flush_flags; + r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + + ctx->num_cs_dw_streamout_end = 0; + + /* XXX print some debug info */ + for (i = 0; i < ctx->num_so_targets; i++) { + if (!t[i]) + continue; + + uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ); + printf("FILLED_SIZE%i: %u\n", i, *ptr); + ctx->ws->buffer_unmap(t[i]->filled_size->buf); + } +} + +void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) +{ + struct radeon_winsys_cs *cs = ctx->cs; + r600_need_cs_space(ctx, 14 + 21, TRUE); + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = 0; + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = t->stride >> 2; + +#if 0 + cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); + cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; + cs->buf[cs->cdw++] = 0; /* src address lo */ + cs->buf[cs->cdw++] = 0; /* src address hi */ + cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ + cs->buf[cs->cdw++] = 0; /* unused */ +#endif + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); + +#if 0 /* I have not found this useful yet. */ + cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); + cs->buf[cs->cdw++] = COPY_DW_SRC_IS_REG | COPY_DW_DST_IS_REG; + cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* src register */ + cs->buf[cs->cdw++] = 0; /* unused */ + cs->buf[cs->cdw++] = R_0085F4_CP_COHER_SIZE >> 2; /* dst register */ + cs->buf[cs->cdw++] = 0; /* unused */ + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); + cs->buf[cs->cdw++] = (R_0085F0_CP_COHER_CNTL - SI_CONFIG_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = S_0085F0_SO0_DEST_BASE_ENA(1) << t->so_index; + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); + cs->buf[cs->cdw++] = (R_0085F8_CP_COHER_BASE - SI_CONFIG_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = t->b.buffer_offset >> 2; + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, (struct r600_resource*)t->b.buffer, + RADEON_USAGE_WRITE); + + cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); + cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ + cs->buf[cs->cdw++] = R_0085FC_CP_COHER_STATUS >> 2; /* register */ + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = 0; /* reference value */ + cs->buf[cs->cdw++] = 0xffffffff; /* mask */ + cs->buf[cs->cdw++] = 4; /* poll interval */ +#endif +} diff --git a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h new file mode 100644 index 00000000000..7d5394e9f58 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h @@ -0,0 +1,76 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600_PRIV_H +#define R600_PRIV_H + +#include "radeonsi_pipe.h" +#include "util/u_hash_table.h" +#include "os/os_thread.h" + +#define R600_MAX_DRAW_CS_DWORDS 17 + +#define PKT_COUNT_C 0xC000FFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) + +/* these flags are used in register flags and added into block flags */ +#define REG_FLAG_NEED_BO 1 +#define REG_FLAG_DIRTY_ALWAYS 2 +#define REG_FLAG_RV6XX_SBU 4 +#define REG_FLAG_NOT_R600 8 +#define REG_FLAG_ENABLE_ALWAYS 16 +#define REG_FLAG_FLUSH_CHANGE 64 + +struct r600_reg { + unsigned offset; + unsigned flags; +}; + +/* + * r600_hw_context.c + */ +struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base); +void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block, + int dirty, int index); +int r600_setup_block_table(struct r600_context *ctx); +void r600_init_cs(struct r600_context *ctx); + +/* + * evergreen_hw_context.c + */ +void evergreen_flush_vgt_streamout(struct r600_context *ctx); +void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit); + + +static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, + enum radeon_bo_usage usage) +{ + assert(usage); + return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; +} + +#endif diff --git a/src/gallium/drivers/radeonsi/r600_query.c b/src/gallium/drivers/radeonsi/r600_query.c new file mode 100644 index 00000000000..bbf7c046f57 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_query.c @@ -0,0 +1,130 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include "radeonsi_pipe.h" +#include "sid.h" + +static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + return (struct pipe_query*)r600_context_query_create(rctx, query_type); +} + +static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + r600_context_query_destroy(rctx, (struct r600_query *)query); +} + +static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_query *rquery = (struct r600_query *)query; + + memset(&rquery->result, 0, sizeof(rquery->result)); + rquery->results_start = rquery->results_end; + r600_query_begin(rctx, (struct r600_query *)query); + LIST_ADDTAIL(&rquery->list, &rctx->active_query_list); +} + +static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_query *rquery = (struct r600_query *)query; + + r600_query_end(rctx, rquery); + LIST_DELINIT(&rquery->list); +} + +static boolean r600_get_query_result(struct pipe_context *ctx, + struct pipe_query *query, + boolean wait, union pipe_query_result *vresult) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_query *rquery = (struct r600_query *)query; + + return r600_context_query_result(rctx, rquery, wait, vresult); +} + +static void r600_render_condition(struct pipe_context *ctx, + struct pipe_query *query, + uint mode) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_query *rquery = (struct r600_query *)query; + int wait_flag = 0; + + /* If we already have nonzero result, render unconditionally */ + if (query != NULL && rquery->result.u64 != 0) { + if (rctx->current_render_cond) { + r600_render_condition(ctx, NULL, 0); + } + return; + } + + rctx->current_render_cond = query; + rctx->current_render_cond_mode = mode; + + if (query == NULL) { + if (rctx->predicate_drawing) { + rctx->predicate_drawing = false; + r600_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, 1); + } + return; + } + + if (mode == PIPE_RENDER_COND_WAIT || + mode == PIPE_RENDER_COND_BY_REGION_WAIT) { + wait_flag = 1; + } + + rctx->predicate_drawing = true; + + switch (rquery->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + r600_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag); + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + r600_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag); + break; + default: + assert(0); + } +} + +void r600_init_query_functions(struct r600_context *rctx) +{ + rctx->context.create_query = r600_create_query; + rctx->context.destroy_query = r600_destroy_query; + rctx->context.begin_query = r600_begin_query; + rctx->context.end_query = r600_end_query; + rctx->context.get_query_result = r600_get_query_result; + + if (rctx->screen->info.r600_num_backends > 0) + rctx->context.render_condition = r600_render_condition; +} diff --git a/src/gallium/drivers/radeonsi/r600_resource.c b/src/gallium/drivers/radeonsi/r600_resource.c new file mode 100644 index 00000000000..7bdf6d6bd5f --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_resource.c @@ -0,0 +1,64 @@ +/* + * Copyright 2010 Marek Olšák <maraeo@gmail.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "radeonsi_pipe.h" + +static struct pipe_resource *r600_resource_create(struct pipe_screen *screen, + const struct pipe_resource *templ) +{ + if (templ->target == PIPE_BUFFER) { + return r600_buffer_create(screen, templ); + } else { + return r600_texture_create(screen, templ); + } +} + +static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * screen, + const struct pipe_resource *templ, + struct winsys_handle *whandle) +{ + if (templ->target == PIPE_BUFFER) { + return NULL; + } else { + return r600_texture_from_handle(screen, templ, whandle); + } +} + +void r600_init_screen_resource_functions(struct pipe_screen *screen) +{ + screen->resource_create = r600_resource_create; + screen->resource_from_handle = r600_resource_from_handle; + screen->resource_get_handle = u_resource_get_handle_vtbl; + screen->resource_destroy = u_resource_destroy_vtbl; + screen->user_buffer_create = r600_user_buffer_create; +} + +void r600_init_context_resource_functions(struct r600_context *r600) +{ + r600->context.get_transfer = u_get_transfer_vtbl; + r600->context.transfer_map = u_transfer_map_vtbl; + r600->context.transfer_flush_region = u_transfer_flush_region_vtbl; + r600->context.transfer_unmap = u_transfer_unmap_vtbl; + r600->context.transfer_destroy = u_transfer_destroy_vtbl; + r600->context.transfer_inline_write = u_transfer_inline_write_vtbl; +} diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h new file mode 100644 index 00000000000..d6f97b0d5a5 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_resource.h @@ -0,0 +1,105 @@ +/* + * Copyright 2010 Marek Olšák <maraeo@gmail.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_RESOURCE_H +#define R600_RESOURCE_H + +#include "util/u_transfer.h" +#include "util/u_vbuf.h" + +/* flag to indicate a resource is to be used as a transfer so should not be tiled */ +#define R600_RESOURCE_FLAG_TRANSFER PIPE_RESOURCE_FLAG_DRV_PRIV + +/* Texture transfer. */ +struct r600_transfer { + /* Base class. */ + struct pipe_transfer transfer; + /* Buffer transfer. */ + struct pipe_transfer *buffer_transfer; + unsigned offset; + struct pipe_resource *staging_texture; +}; + +struct r600_resource_texture { + struct r600_resource resource; + + /* If this resource is a depth-stencil buffer on evergreen, this contains + * the depth part of the format. There is a separate stencil resource + * for the stencil buffer below. */ + enum pipe_format real_format; + + unsigned offset[PIPE_MAX_TEXTURE_LEVELS]; + unsigned pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS]; /* transfer */ + unsigned pitch_in_blocks[PIPE_MAX_TEXTURE_LEVELS]; /* texture resource */ + unsigned layer_size[PIPE_MAX_TEXTURE_LEVELS]; + unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS]; + unsigned pitch_override; + unsigned size; + unsigned tile_type; + unsigned depth; + unsigned dirty_db; + struct r600_resource_texture *stencil; /* Stencil is in a separate buffer on Evergreen. */ + struct r600_resource_texture *flushed_depth_texture; + boolean is_flushing_texture; +}; + +#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED) + +struct r600_surface { + struct pipe_surface base; + unsigned aligned_height; +}; + +void r600_init_screen_resource_functions(struct pipe_screen *screen); + +/* r600_texture */ +struct pipe_resource *r600_texture_create(struct pipe_screen *screen, + const struct pipe_resource *templ); +struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, + const struct pipe_resource *base, + struct winsys_handle *whandle); + +static INLINE struct r600_resource *r600_resource(struct pipe_resource *r) +{ + return (struct r600_resource*)r; +} + +int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create); + +/* r600_texture.c texture transfer functions. */ +struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, + struct pipe_resource *texture, + unsigned level, + unsigned usage, + const struct pipe_box *box); +void r600_texture_transfer_destroy(struct pipe_context *ctx, + struct pipe_transfer *trans); +void* r600_texture_transfer_map(struct pipe_context *ctx, + struct pipe_transfer* transfer); +void r600_texture_transfer_unmap(struct pipe_context *ctx, + struct pipe_transfer* transfer); + +struct r600_context; + +void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer, uint32_t *offset); + +#endif diff --git a/src/gallium/drivers/radeonsi/r600_state_common.c b/src/gallium/drivers/radeonsi/r600_state_common.c new file mode 100644 index 00000000000..4ba83dec903 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_state_common.c @@ -0,0 +1,899 @@ +/* + * Copyright 2010 Red Hat Inc. + * 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie <airlied@redhat.com> + * Jerome Glisse <jglisse@redhat.com> + */ +#include "util/u_blitter.h" +#include "util/u_memory.h" +#include "util/u_format.h" +#include "pipebuffer/pb_buffer.h" +#include "pipe/p_shader_tokens.h" +#include "tgsi/tgsi_parse.h" +#include "r600_hw_context_priv.h" +#include "radeonsi_pipe.h" +#include "sid.h" + +static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = rctx->cs; + struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom; + + cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); + cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */ + cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */ + cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */ + cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */ + + a->flush_flags = 0; +} + +static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = rctx->cs; + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); +} + +static void r600_init_atom(struct r600_atom *atom, + void (*emit)(struct r600_context *ctx, struct r600_atom *state), + unsigned num_dw, + enum r600_atom_flags flags) +{ + atom->emit = emit; + atom->num_dw = num_dw; + atom->flags = flags; +} + +void r600_init_common_atoms(struct r600_context *rctx) +{ + r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY); + r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); +} + +unsigned r600_get_cb_flush_flags(struct r600_context *rctx) +{ + unsigned flags = 0; + + if (rctx->framebuffer.nr_cbufs) { + flags |= S_0085F0_CB_ACTION_ENA(1) | + (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT); + } + + return flags; +} + +void r600_texture_barrier(struct pipe_context *ctx) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); + r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom); +} + +static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) +{ + static const int prim_conv[] = { + V_008958_DI_PT_POINTLIST, + V_008958_DI_PT_LINELIST, + V_008958_DI_PT_LINELOOP, + V_008958_DI_PT_LINESTRIP, + V_008958_DI_PT_TRILIST, + V_008958_DI_PT_TRISTRIP, + V_008958_DI_PT_TRIFAN, + V_008958_DI_PT_QUADLIST, + V_008958_DI_PT_QUADSTRIP, + V_008958_DI_PT_POLYGON, + -1, + -1, + -1, + -1 + }; + + *prim = prim_conv[pprim]; + if (*prim == -1) { + fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); + return false; + } + return true; +} + +/* common state between evergreen and r600 */ +void r600_bind_blend_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state; + struct r600_pipe_state *rstate; + + if (state == NULL) + return; + rstate = &blend->rstate; + rctx->states[rstate->id] = rstate; + rctx->cb_target_mask = blend->cb_target_mask; + rctx->cb_color_control = blend->cb_color_control; + + r600_context_pipe_state_set(rctx, rstate); +} + +static void r600_set_stencil_ref(struct pipe_context *ctx, + const struct r600_stencil_ref *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); + + if (rstate == NULL) + return; + + rstate->id = R600_PIPE_STATE_STENCIL_REF; + r600_pipe_state_add_reg(rstate, + R_028430_DB_STENCILREFMASK, + S_028430_STENCILTESTVAL(state->ref_value[0]) | + S_028430_STENCILMASK(state->valuemask[0]) | + S_028430_STENCILWRITEMASK(state->writemask[0]), + NULL, 0); + r600_pipe_state_add_reg(rstate, + R_028434_DB_STENCILREFMASK_BF, + S_028434_STENCILTESTVAL_BF(state->ref_value[1]) | + S_028434_STENCILMASK_BF(state->valuemask[1]) | + S_028434_STENCILWRITEMASK_BF(state->writemask[1]), + NULL, 0); + + free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); + rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; + r600_context_pipe_state_set(rctx, rstate); +} + +void r600_set_pipe_stencil_ref(struct pipe_context *ctx, + const struct pipe_stencil_ref *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; + struct r600_stencil_ref ref; + + rctx->stencil_ref = *state; + + if (!dsa) + return; + + ref.ref_value[0] = state->ref_value[0]; + ref.ref_value[1] = state->ref_value[1]; + ref.valuemask[0] = dsa->valuemask[0]; + ref.valuemask[1] = dsa->valuemask[1]; + ref.writemask[0] = dsa->writemask[0]; + ref.writemask[1] = dsa->writemask[1]; + + r600_set_stencil_ref(ctx, &ref); +} + +void r600_bind_dsa_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_dsa *dsa = state; + struct r600_pipe_state *rstate; + struct r600_stencil_ref ref; + + if (state == NULL) + return; + rstate = &dsa->rstate; + rctx->states[rstate->id] = rstate; + rctx->alpha_ref = dsa->alpha_ref; + rctx->alpha_ref_dirty = true; + r600_context_pipe_state_set(rctx, rstate); + + ref.ref_value[0] = rctx->stencil_ref.ref_value[0]; + ref.ref_value[1] = rctx->stencil_ref.ref_value[1]; + ref.valuemask[0] = dsa->valuemask[0]; + ref.valuemask[1] = dsa->valuemask[1]; + ref.writemask[0] = dsa->writemask[0]; + ref.writemask[1] = dsa->writemask[1]; + + r600_set_stencil_ref(ctx, &ref); +} + +void r600_bind_rs_state(struct pipe_context *ctx, void *state) +{ + struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; + struct r600_context *rctx = (struct r600_context *)ctx; + + if (state == NULL) + return; + + rctx->sprite_coord_enable = rs->sprite_coord_enable; + rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; + rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; + rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; + rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; + + rctx->rasterizer = rs; + + rctx->states[rs->rstate.id] = &rs->rstate; + r600_context_pipe_state_set(rctx, &rs->rstate); + + if (rctx->chip_class >= CAYMAN) { + cayman_polygon_offset_update(rctx); + } +} + +void r600_delete_rs_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; + + if (rctx->rasterizer == rs) { + rctx->rasterizer = NULL; + } + if (rctx->states[rs->rstate.id] == &rs->rstate) { + rctx->states[rs->rstate.id] = NULL; + } + free(rs); +} + +void r600_sampler_view_destroy(struct pipe_context *ctx, + struct pipe_sampler_view *state) +{ + struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; + + pipe_resource_reference(&state->texture, NULL); + FREE(resource); +} + +void r600_delete_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; + + if (rctx->states[rstate->id] == rstate) { + rctx->states[rstate->id] = NULL; + } + for (int i = 0; i < rstate->nregs; i++) { + pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); + } + free(rstate); +} + +void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_vertex_element *v = (struct r600_vertex_element*)state; + + rctx->vertex_elements = v; + if (v) { + r600_inval_shader_cache(rctx); + u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state, + v->vmgr_elements); + + rctx->states[v->rstate.id] = &v->rstate; + r600_context_pipe_state_set(rctx, &v->rstate); + } +} + +void r600_delete_vertex_element(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_vertex_element *v = (struct r600_vertex_element*)state; + + if (rctx->states[v->rstate.id] == &v->rstate) { + rctx->states[v->rstate.id] = NULL; + } + if (rctx->vertex_elements == state) + rctx->vertex_elements = NULL; + + u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements); + FREE(state); +} + + +void r600_set_index_buffer(struct pipe_context *ctx, + const struct pipe_index_buffer *ib) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib); +} + +void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, + const struct pipe_vertex_buffer *buffers) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers); +} + +void *si_create_vertex_elements(struct pipe_context *ctx, + unsigned count, + const struct pipe_vertex_element *elements) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); + + assert(count < 32); + if (!v) + return NULL; + + v->count = count; + v->vmgr_elements = + u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count, + elements, v->elements); + + return v; +} + +void *si_create_shader_state(struct pipe_context *ctx, + const struct pipe_shader_state *state) +{ + struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader); + + shader->tokens = tgsi_dup_tokens(state->tokens); + shader->so = state->stream_output; + + return shader; +} + +void r600_bind_ps_shader(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + if (rctx->ps_shader != state) + rctx->shader_dirty = true; + + /* TODO delete old shader */ + rctx->ps_shader = (struct si_pipe_shader *)state; + if (state) { + r600_inval_shader_cache(rctx); + r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate); + } +} + +void r600_bind_vs_shader(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + if (rctx->vs_shader != state) + rctx->shader_dirty = true; + + /* TODO delete old shader */ + rctx->vs_shader = (struct si_pipe_shader *)state; + if (state) { + r600_inval_shader_cache(rctx); + r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate); + } +} + +void r600_delete_ps_shader(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct si_pipe_shader *shader = (struct si_pipe_shader *)state; + + if (rctx->ps_shader == shader) { + rctx->ps_shader = NULL; + } + + free(shader->tokens); + si_pipe_shader_destroy(ctx, shader); + free(shader); +} + +void r600_delete_vs_shader(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct si_pipe_shader *shader = (struct si_pipe_shader *)state; + + if (rctx->vs_shader == shader) { + rctx->vs_shader = NULL; + } + + free(shader->tokens); + si_pipe_shader_destroy(ctx, shader); + free(shader); +} + +static void r600_update_alpha_ref(struct r600_context *rctx) +{ +#if 0 + unsigned alpha_ref; + struct r600_pipe_state rstate; + + alpha_ref = rctx->alpha_ref; + rstate.nregs = 0; + if (rctx->export_16bpc) + alpha_ref &= ~0x1FFF; + r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0); + + r600_context_pipe_state_set(rctx, &rstate); + rctx->alpha_ref_dirty = false; +#endif +} + +void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, + struct pipe_resource *buffer) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_resource *rbuffer = r600_resource(buffer); + struct r600_pipe_state *rstate; + uint64_t va_offset; + uint32_t offset; + + /* Note that the state tracker can unbind constant buffers by + * passing NULL here. + */ + if (buffer == NULL) { + return; + } + + r600_inval_shader_cache(rctx); + + r600_upload_const_buffer(rctx, &rbuffer, &offset); + va_offset = r600_resource_va(ctx->screen, (void*)rbuffer); + va_offset += offset; + //va_offset >>= 8; + + switch (shader) { + case PIPE_SHADER_VERTEX: + rstate = &rctx->vs_const_buffer; + rstate->nregs = 0; + r600_pipe_state_add_reg(rstate, + R_00B138_SPI_SHADER_USER_DATA_VS_2, + va_offset, rbuffer, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, + R_00B13C_SPI_SHADER_USER_DATA_VS_3, + va_offset >> 32, NULL, 0); + break; + case PIPE_SHADER_FRAGMENT: + rstate = &rctx->ps_const_buffer; + rstate->nregs = 0; + r600_pipe_state_add_reg(rstate, + R_00B030_SPI_SHADER_USER_DATA_PS_0, + va_offset, rbuffer, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, + R_00B034_SPI_SHADER_USER_DATA_PS_1, + va_offset >> 32, NULL, 0); + break; + default: + R600_ERR("unsupported %d\n", shader); + return; + } + + r600_context_pipe_state_set(rctx, rstate); + + if (buffer != &rbuffer->b.b.b) + pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL); +} + +struct pipe_stream_output_target * +r600_create_so_target(struct pipe_context *ctx, + struct pipe_resource *buffer, + unsigned buffer_offset, + unsigned buffer_size) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_so_target *t; + void *ptr; + + t = CALLOC_STRUCT(r600_so_target); + if (!t) { + return NULL; + } + + t->b.reference.count = 1; + t->b.context = ctx; + pipe_resource_reference(&t->b.buffer, buffer); + t->b.buffer_offset = buffer_offset; + t->b.buffer_size = buffer_size; + + t->filled_size = (struct r600_resource*) + pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4); + ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE); + memset(ptr, 0, t->filled_size->buf->size); + rctx->ws->buffer_unmap(t->filled_size->buf); + + return &t->b; +} + +void r600_so_target_destroy(struct pipe_context *ctx, + struct pipe_stream_output_target *target) +{ + struct r600_so_target *t = (struct r600_so_target*)target; + pipe_resource_reference(&t->b.buffer, NULL); + pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL); + FREE(t); +} + +void r600_set_so_targets(struct pipe_context *ctx, + unsigned num_targets, + struct pipe_stream_output_target **targets, + unsigned append_bitmask) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + unsigned i; + + /* Stop streamout. */ + if (rctx->num_so_targets) { + r600_context_streamout_end(rctx); + } + + /* Set the new targets. */ + for (i = 0; i < num_targets; i++) { + pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]); + } + for (; i < rctx->num_so_targets; i++) { + pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL); + } + + rctx->num_so_targets = num_targets; + rctx->streamout_start = num_targets != 0; + rctx->streamout_append_bitmask = append_bitmask; +} + +static void r600_vertex_buffer_update(struct r600_context *rctx) +{ + struct pipe_context *ctx = &rctx->context; + struct r600_pipe_state *rstate = &rctx->vs_user_data; + struct r600_resource *rbuffer, *t_list_buffer; + struct pipe_vertex_buffer *vertex_buffer; + unsigned i, count, offset; + uint32_t *ptr; + uint64_t va; + + r600_inval_vertex_cache(rctx); + + if (rctx->vertex_elements->vbuffer_need_offset) { + /* one resource per vertex elements */ + count = rctx->vertex_elements->count; + } else { + /* bind vertex buffer once */ + count = rctx->vbuf_mgr->nr_real_vertex_buffers; + } + assert(count <= 256 / 4); + + t_list_buffer = (struct r600_resource*) + pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, + PIPE_USAGE_IMMUTABLE, 4 * 4 * count); + if (t_list_buffer == NULL) + return; + + ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->buf, + rctx->cs, + PIPE_TRANSFER_WRITE); + + for (i = 0 ; i < count; i++, ptr += 4) { + struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[i]; + const struct util_format_description *desc; + unsigned data_format, num_format; + int first_non_void; + + if (rctx->vertex_elements->vbuffer_need_offset) { + /* one resource per vertex elements */ + unsigned vbuffer_index; + vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index; + vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index]; + rbuffer = (struct r600_resource*)vertex_buffer->buffer; + offset = rctx->vertex_elements->vbuffer_offset[i]; + } else { + /* bind vertex buffer once */ + vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i]; + rbuffer = (struct r600_resource*)vertex_buffer->buffer; + offset = 0; + } + if (vertex_buffer == NULL || rbuffer == NULL) + continue; + offset += vertex_buffer->buffer_offset; + + va = r600_resource_va(ctx->screen, (void*)rbuffer); + va += offset; + + desc = util_format_description(velem->src_format); + first_non_void = util_format_get_first_non_void_channel(velem->src_format); + data_format = si_translate_vertexformat(ctx->screen, + velem->src_format, + desc, first_non_void); + + switch (desc->channel[first_non_void].type) { + case UTIL_FORMAT_TYPE_FIXED: + num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */ + break; + case UTIL_FORMAT_TYPE_SIGNED: + num_format = V_008F0C_BUF_NUM_FORMAT_SNORM; + break; + case UTIL_FORMAT_TYPE_UNSIGNED: + num_format = V_008F0C_BUF_NUM_FORMAT_UNORM; + break; + case UTIL_FORMAT_TYPE_FLOAT: + default: + num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; + } + + /* Fill in T# buffer resource description */ + ptr[0] = va & 0xFFFFFFFF; + ptr[1] = ((va >> 32) & 0xFFFF) | + (vertex_buffer->stride & 0x3FFF) << 16; + ptr[2] = (vertex_buffer->buffer->width0 - offset) / vertex_buffer->stride; + /* XXX: Hardcoding RGBA */ + ptr[3] = 4 | 5 << 3 | 6 << 6 | 7 << 9 | + num_format << 12 | data_format << 15; + + r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ); + } + + rstate->nregs = 0; + + va = r600_resource_va(ctx->screen, (void*)t_list_buffer); + r600_pipe_state_add_reg(rstate, + R_00B130_SPI_SHADER_USER_DATA_VS_0, + va, t_list_buffer, RADEON_USAGE_READ); + r600_pipe_state_add_reg(rstate, + R_00B134_SPI_SHADER_USER_DATA_VS_1, + va >> 32, + NULL, 0); + + r600_context_pipe_state_set(rctx, rstate); +} + +static void si_update_derived_state(struct r600_context *rctx) +{ + struct pipe_context * ctx = (struct pipe_context*)rctx; + + if (!rctx->blitter->running) { + if (rctx->have_depth_fb || rctx->have_depth_texture) + r600_flush_depth_textures(rctx); + } + + if (rctx->shader_dirty) { + si_pipe_shader_destroy(&rctx->context, rctx->vs_shader); + } + + if (rctx->shader_dirty || + (rctx->ps_shader->shader.fs_write_all && + (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)) || + (rctx->sprite_coord_enable && + (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) { + si_pipe_shader_destroy(&rctx->context, rctx->ps_shader); + } + + if (rctx->alpha_ref_dirty) { + r600_update_alpha_ref(rctx); + } + + if (!rctx->vs_shader->bo) { + si_pipe_shader_vs(ctx, rctx->vs_shader); + + r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate); + } + + if (!rctx->ps_shader->bo) { + si_pipe_shader_ps(ctx, rctx->ps_shader); + + r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate); + } + + if (rctx->shader_dirty) { + si_update_spi_map(rctx); + rctx->shader_dirty = false; + } +} + +void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; + struct pipe_draw_info info = *dinfo; + struct r600_draw rdraw = {}; + struct pipe_index_buffer ib = {}; + unsigned prim, mask, ls_mask = 0; + struct r600_block *dirty_block = NULL, *next_block = NULL; + struct r600_atom *state = NULL, *next_state = NULL; + int i; + + if ((!info.count && (info.indexed || !info.count_from_stream_output)) || + (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) || + !r600_conv_pipe_prim(info.mode, &prim)) { + return; + } + + if (!rctx->ps_shader || !rctx->vs_shader) + return; + + si_update_derived_state(rctx); + + u_vbuf_draw_begin(rctx->vbuf_mgr, &info); + r600_vertex_buffer_update(rctx); + + rdraw.vgt_num_indices = info.count; + rdraw.vgt_num_instances = info.instance_count; + + if (info.indexed) { + /* Initialize the index buffer struct. */ + pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer); + ib.index_size = rctx->vbuf_mgr->index_buffer.index_size; + ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size; + + /* Translate or upload, if needed. */ + r600_translate_index_buffer(rctx, &ib, info.count); + + if (u_vbuf_resource(ib.buffer)->user_ptr) { + r600_upload_index_buffer(rctx, &ib, info.count); + } + + /* Initialize the r600_draw struct with index buffer info. */ + if (ib.index_size == 4) { + rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 | + (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0); + } else { + rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 | + (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0); + } + rdraw.indices = (struct r600_resource*)ib.buffer; + rdraw.indices_bo_offset = ib.offset; + rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA; + } else { + info.index_bias = info.start; + rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX; + if (info.count_from_stream_output) { + rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1); + + r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output); + } + } + + rctx->vs_shader_so_strides = rctx->vs_shader->so_strides; + + mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; + + if (rctx->vgt.id != R600_PIPE_STATE_VGT) { + rctx->vgt.id = R600_PIPE_STATE_VGT; + rctx->vgt.nregs = 0; + r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0); +#if 0 + r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0); +#endif + r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0); + } + + rctx->vgt.nregs = 0; + r600_pipe_state_mod_reg(&rctx->vgt, prim); + r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask); + r600_pipe_state_mod_reg(&rctx->vgt, ~0); + r600_pipe_state_mod_reg(&rctx->vgt, 0); + r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); + r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); + r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); +#if 0 + r600_pipe_state_mod_reg(&rctx->vgt, 0); + r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); +#endif + + if (prim == V_008958_DI_PT_LINELIST) + ls_mask = 1; + else if (prim == V_008958_DI_PT_LINESTRIP) + ls_mask = 2; + r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple); + + if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) { + r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl); + } else { + r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl); + } + r600_pipe_state_mod_reg(&rctx->vgt, + rctx->pa_cl_vs_out_cntl /*| + (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write)*/); + r600_pipe_state_mod_reg(&rctx->vgt, + rctx->pa_cl_clip_cntl /*| + (rctx->vs_shader->shader.clip_dist_write || + rctx->vs_shader->shader.vs_prohibit_ucps ? + 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/); + + r600_context_pipe_state_set(rctx, &rctx->vgt); + + rdraw.db_render_override = dsa->db_render_override; + rdraw.db_render_control = dsa->db_render_control; + + /* Emit states. */ + r600_need_cs_space(rctx, 0, TRUE); + + LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { + r600_emit_atom(rctx, state); + } + LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) { + r600_context_block_emit_dirty(rctx, dirty_block); + } + rctx->pm4_dirty_cdwords = 0; + + /* Enable stream out if needed. */ + if (rctx->streamout_start) { + r600_context_streamout_begin(rctx); + rctx->streamout_start = FALSE; + } + + for (i = 0; i < NUM_TEX_UNITS; i++) { + if (rctx->ps_samplers.views[i]) + r600_context_bo_reloc(rctx, + (struct r600_resource*)rctx->ps_samplers.views[i]->base.texture, + RADEON_USAGE_READ); + } + + if (rctx->chip_class >= CAYMAN) { + evergreen_context_draw(rctx, &rdraw); + } + + rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING; + + if (rctx->framebuffer.zsbuf) + { + struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture; + ((struct r600_resource_texture *)tex)->dirty_db = TRUE; + } + + pipe_resource_reference(&ib.buffer, NULL); + u_vbuf_draw_end(rctx->vbuf_mgr); +} + +void _r600_pipe_state_add_reg(struct r600_context *ctx, + struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + uint32_t range_id, uint32_t block_id, + struct r600_resource *bo, + enum radeon_bo_usage usage) +{ + struct r600_range *range; + struct r600_block *block; + + if (bo) assert(usage); + + range = &ctx->range[range_id]; + block = range->blocks[block_id]; + state->regs[state->nregs].block = block; + state->regs[state->nregs].id = (offset - block->start_offset) >> 2; + + state->regs[state->nregs].value = value; + state->regs[state->nregs].bo = bo; + state->regs[state->nregs].bo_usage = usage; + + state->nregs++; + assert(state->nregs < R600_BLOCK_MAX_REG); +} + +void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + struct r600_resource *bo, + enum radeon_bo_usage usage) +{ + if (bo) assert(usage); + + state->regs[state->nregs].id = offset; + state->regs[state->nregs].block = NULL; + state->regs[state->nregs].value = value; + state->regs[state->nregs].bo = bo; + state->regs[state->nregs].bo_usage = usage; + + state->nregs++; + assert(state->nregs < R600_BLOCK_MAX_REG); +} diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c new file mode 100644 index 00000000000..c9e1b832113 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -0,0 +1,825 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <errno.h> +#include "pipe/p_screen.h" +#include "util/u_format.h" +#include "util/u_format_s3tc.h" +#include "util/u_math.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include "pipebuffer/pb_buffer.h" +#include "radeonsi_pipe.h" +#include "r600_resource.h" +#include "sid.h" + +/* Copy from a full GPU texture to a transfer's staging one. */ +static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) +{ + struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; + struct pipe_resource *texture = transfer->resource; + + ctx->resource_copy_region(ctx, rtransfer->staging_texture, + 0, 0, 0, 0, texture, transfer->level, + &transfer->box); +} + + +/* Copy from a transfer's staging texture to a full GPU one. */ +static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) +{ + struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; + struct pipe_resource *texture = transfer->resource; + struct pipe_box sbox; + + sbox.x = sbox.y = sbox.z = 0; + sbox.width = transfer->box.width; + sbox.height = transfer->box.height; + /* XXX that might be wrong */ + sbox.depth = 1; + ctx->resource_copy_region(ctx, texture, transfer->level, + transfer->box.x, transfer->box.y, transfer->box.z, + rtransfer->staging_texture, + 0, &sbox); +} + +unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, + unsigned level, unsigned layer) +{ + unsigned offset = rtex->offset[level]; + + switch (rtex->resource.b.b.b.target) { + case PIPE_TEXTURE_3D: + case PIPE_TEXTURE_CUBE: + default: + return offset + layer * rtex->layer_size[level]; + } +} + +static unsigned r600_get_block_alignment(struct pipe_screen *screen, + enum pipe_format format, + unsigned array_mode) +{ + struct r600_screen* rscreen = (struct r600_screen *)screen; + unsigned pixsize = util_format_get_blocksize(format); + int p_align; + + switch(array_mode) { +#if 0 + case V_038000_ARRAY_1D_TILED_THIN1: + p_align = MAX2(8, + ((rscreen->tiling_info.group_bytes / 8 / pixsize))); + break; + case V_038000_ARRAY_2D_TILED_THIN1: + p_align = MAX2(rscreen->tiling_info.num_banks, + (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * + rscreen->tiling_info.num_banks)) * 8; + break; + case V_038000_ARRAY_LINEAR_ALIGNED: + p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); + break; + case V_038000_ARRAY_LINEAR_GENERAL: +#endif + default: + p_align = rscreen->tiling_info.group_bytes / pixsize; + break; + } + return p_align; +} + +static unsigned r600_get_height_alignment(struct pipe_screen *screen, + unsigned array_mode) +{ + struct r600_screen* rscreen = (struct r600_screen *)screen; + int h_align; + + switch (array_mode) { +#if 0 + case V_038000_ARRAY_2D_TILED_THIN1: + h_align = rscreen->tiling_info.num_channels * 8; + break; + case V_038000_ARRAY_1D_TILED_THIN1: + case V_038000_ARRAY_LINEAR_ALIGNED: + h_align = 8; + break; + case V_038000_ARRAY_LINEAR_GENERAL: +#endif + default: + h_align = 1; + break; + } + return h_align; +} + +static unsigned r600_get_base_alignment(struct pipe_screen *screen, + enum pipe_format format, + unsigned array_mode) +{ + struct r600_screen* rscreen = (struct r600_screen *)screen; + unsigned pixsize = util_format_get_blocksize(format); + int p_align = r600_get_block_alignment(screen, format, array_mode); + int h_align = r600_get_height_alignment(screen, array_mode); + int b_align; + + switch (array_mode) { +#if 0 + case V_038000_ARRAY_2D_TILED_THIN1: + b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, + p_align * pixsize * h_align); + break; + case V_038000_ARRAY_1D_TILED_THIN1: + case V_038000_ARRAY_LINEAR_ALIGNED: + case V_038000_ARRAY_LINEAR_GENERAL: +#endif + default: + b_align = rscreen->tiling_info.group_bytes; + break; + } + return b_align; +} + +static unsigned mip_minify(unsigned size, unsigned level) +{ + unsigned val; + val = u_minify(size, level); + if (level > 0) + val = util_next_power_of_two(val); + return val; +} + +static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, + struct r600_resource_texture *rtex, + unsigned level) +{ + struct pipe_resource *ptex = &rtex->resource.b.b.b; + unsigned nblocksx, block_align, width; + unsigned blocksize = util_format_get_blocksize(rtex->real_format); + + if (rtex->pitch_override) + return rtex->pitch_override / blocksize; + + width = mip_minify(ptex->width0, level); + nblocksx = util_format_get_nblocksx(rtex->real_format, width); + + block_align = r600_get_block_alignment(screen, rtex->real_format, + rtex->array_mode[level]); + nblocksx = align(nblocksx, block_align); + return nblocksx; +} + +static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, + struct r600_resource_texture *rtex, + unsigned level) +{ + struct pipe_resource *ptex = &rtex->resource.b.b.b; + unsigned height, tile_height; + + height = mip_minify(ptex->height0, level); + height = util_format_get_nblocksy(rtex->real_format, height); + tile_height = r600_get_height_alignment(screen, + rtex->array_mode[level]); + + /* XXX Hack around an alignment issue. Less tests fail with this. + * + * The thing is depth-stencil buffers should be tiled, i.e. + * the alignment should be >=8. If I make them tiled, stencil starts + * working because it no longer overlaps with the depth buffer + * in memory, but texturing like drawpix-stencil breaks. */ + if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) + tile_height = 8; + + height = align(height, tile_height); + return height; +} + +static void r600_texture_set_array_mode(struct pipe_screen *screen, + struct r600_resource_texture *rtex, + unsigned level, unsigned array_mode) +{ + struct pipe_resource *ptex = &rtex->resource.b.b.b; + + switch (array_mode) { +#if 0 + case V_0280A0_ARRAY_LINEAR_GENERAL: + case V_0280A0_ARRAY_LINEAR_ALIGNED: + case V_0280A0_ARRAY_1D_TILED_THIN1: +#endif + default: + rtex->array_mode[level] = array_mode; + break; +#if 0 + case V_0280A0_ARRAY_2D_TILED_THIN1: + { + unsigned w, h, tile_height, tile_width; + + tile_height = r600_get_height_alignment(screen, array_mode); + tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); + + w = mip_minify(ptex->width0, level); + h = mip_minify(ptex->height0, level); + if (w <= tile_width || h <= tile_height) + rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; + else + rtex->array_mode[level] = array_mode; + } + break; +#endif + } +} + +static void r600_setup_miptree(struct pipe_screen *screen, + struct r600_resource_texture *rtex, + unsigned array_mode) +{ + struct pipe_resource *ptex = &rtex->resource.b.b.b; + enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; + unsigned size, layer_size, i, offset; + unsigned nblocksx, nblocksy; + + for (i = 0, offset = 0; i <= ptex->last_level; i++) { + unsigned blocksize = util_format_get_blocksize(rtex->real_format); + unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); + + r600_texture_set_array_mode(screen, rtex, i, array_mode); + + nblocksx = r600_texture_get_nblocksx(screen, rtex, i); + nblocksy = r600_texture_get_nblocksy(screen, rtex, i); + + if (chipc >= CAYMAN /*&& array_mode == V_038000_ARRAY_LINEAR_GENERAL*/) + layer_size = align(nblocksx, 64) * nblocksy * blocksize; + else + layer_size = nblocksx * nblocksy * blocksize; + + if (ptex->target == PIPE_TEXTURE_CUBE) { + if (chipc >= CAYMAN) + size = layer_size * 8; + } + else if (ptex->target == PIPE_TEXTURE_3D) + size = layer_size * u_minify(ptex->depth0, i); + else + size = layer_size * ptex->array_size; + + /* align base image and start of miptree */ + if ((i == 0) || (i == 1)) + offset = align(offset, base_align); + rtex->offset[i] = offset; + rtex->layer_size[i] = layer_size; + rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ + rtex->pitch_in_bytes[i] = nblocksx * blocksize; + + offset += size; + } + rtex->size = offset; +} + +/* Figure out whether u_blitter will fallback to a transfer operation. + * If so, don't use a staging resource. + */ +static boolean permit_hardware_blit(struct pipe_screen *screen, + const struct pipe_resource *res) +{ + unsigned bind; + + if (util_format_is_depth_or_stencil(res->format)) + bind = PIPE_BIND_DEPTH_STENCIL; + else + bind = PIPE_BIND_RENDER_TARGET; + + /* hackaround for S3TC */ + if (util_format_is_compressed(res->format)) + return TRUE; + + if (!screen->is_format_supported(screen, + res->format, + res->target, + res->nr_samples, + bind)) + return FALSE; + + if (!screen->is_format_supported(screen, + res->format, + res->target, + res->nr_samples, + PIPE_BIND_SAMPLER_VIEW)) + return FALSE; + + switch (res->usage) { + case PIPE_USAGE_STREAM: + case PIPE_USAGE_STAGING: + return FALSE; + + default: + return TRUE; + } +} + +static boolean r600_texture_get_handle(struct pipe_screen* screen, + struct pipe_resource *ptex, + struct winsys_handle *whandle) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; + struct r600_resource *resource = &rtex->resource; + struct r600_screen *rscreen = (struct r600_screen*)screen; + + return rscreen->ws->buffer_get_handle(resource->buf, + rtex->pitch_in_bytes[0], whandle); +} + +static void r600_texture_destroy(struct pipe_screen *screen, + struct pipe_resource *ptex) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; + struct r600_resource *resource = &rtex->resource; + + if (rtex->flushed_depth_texture) + pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); + + if (rtex->stencil) + pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); + + pb_reference(&resource->buf, NULL); + FREE(rtex); +} + +static const struct u_resource_vtbl r600_texture_vtbl = +{ + r600_texture_get_handle, /* get_handle */ + r600_texture_destroy, /* resource_destroy */ + r600_texture_get_transfer, /* get_transfer */ + r600_texture_transfer_destroy, /* transfer_destroy */ + r600_texture_transfer_map, /* transfer_map */ + u_default_transfer_flush_region,/* transfer_flush_region */ + r600_texture_transfer_unmap, /* transfer_unmap */ + u_default_transfer_inline_write /* transfer_inline_write */ +}; + +static struct r600_resource_texture * +r600_texture_create_object(struct pipe_screen *screen, + const struct pipe_resource *base, + unsigned array_mode, + unsigned pitch_in_bytes_override, + unsigned max_buffer_size, + struct pb_buffer *buf, + boolean alloc_bo) +{ + struct r600_resource_texture *rtex; + struct r600_resource *resource; + struct r600_screen *rscreen = (struct r600_screen*)screen; + + rtex = CALLOC_STRUCT(r600_resource_texture); + if (rtex == NULL) + return NULL; + + resource = &rtex->resource; + resource->b.b.b = *base; + resource->b.b.vtbl = &r600_texture_vtbl; + pipe_reference_init(&resource->b.b.b.reference, 1); + resource->b.b.b.screen = screen; + rtex->pitch_override = pitch_in_bytes_override; + rtex->real_format = base->format; + + /* We must split depth and stencil into two separate buffers on Evergreen. */ + if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && + ((struct r600_screen*)screen)->chip_class >= CAYMAN && + util_format_is_depth_and_stencil(base->format)) { + struct pipe_resource stencil; + unsigned stencil_pitch_override = 0; + + switch (base->format) { + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; + break; + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; + break; + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + rtex->real_format = PIPE_FORMAT_Z32_FLOAT; + break; + default: + assert(0); + FREE(rtex); + return NULL; + } + + /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ + if (pitch_in_bytes_override) { + assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || + base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); + stencil_pitch_override = pitch_in_bytes_override / 4; + } + + /* Allocate the stencil buffer. */ + stencil = *base; + stencil.format = PIPE_FORMAT_S8_UINT; + rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, + stencil_pitch_override, + max_buffer_size, NULL, FALSE); + if (!rtex->stencil) { + FREE(rtex); + return NULL; + } + /* Proceed in creating the depth buffer. */ + } + + /* only mark depth textures the HW can hit as depth textures */ + if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) + rtex->depth = 1; + + r600_setup_miptree(screen, rtex, array_mode); + + /* If we initialized separate stencil for Evergreen. place it after depth. */ + if (rtex->stencil) { + unsigned stencil_align, stencil_offset; + + stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); + stencil_offset = align(rtex->size, stencil_align); + + for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) + rtex->stencil->offset[i] += stencil_offset; + + rtex->size = stencil_offset + rtex->stencil->size; + } + + /* Now create the backing buffer. */ + if (!buf && alloc_bo) { + struct pipe_resource *ptex = &rtex->resource.b.b.b; + unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); + + if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { + pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); + FREE(rtex); + return NULL; + } + } else if (buf) { + resource->buf = buf; + resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); + resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; + } + + if (rtex->stencil) { + pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); + rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; + rtex->stencil->resource.domains = rtex->resource.domains; + } + return rtex; +} + +DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE); + +struct pipe_resource *r600_texture_create(struct pipe_screen *screen, + const struct pipe_resource *templ) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + unsigned array_mode = 0; + + if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && + !(templ->bind & PIPE_BIND_SCANOUT)) { +#if 0 + if (util_format_is_compressed(templ->format)) { + array_mode = V_038000_ARRAY_1D_TILED_THIN1; + } + else if (debug_get_option_tiling_enabled() && + rscreen->info.drm_minor >= 9 && + permit_hardware_blit(screen, templ)) { + array_mode = V_038000_ARRAY_2D_TILED_THIN1; + } +#endif + } + + return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, + 0, 0, NULL, TRUE); +} + +static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, + struct pipe_resource *texture, + const struct pipe_surface *surf_tmpl) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; + struct r600_surface *surface = CALLOC_STRUCT(r600_surface); + unsigned level = surf_tmpl->u.tex.level; + + assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); + if (surface == NULL) + return NULL; + /* XXX no offset */ +/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ + pipe_reference_init(&surface->base.reference, 1); + pipe_resource_reference(&surface->base.texture, texture); + surface->base.context = pipe; + surface->base.format = surf_tmpl->format; + surface->base.width = mip_minify(texture->width0, level); + surface->base.height = mip_minify(texture->height0, level); + surface->base.usage = surf_tmpl->usage; + surface->base.texture = texture; + surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; + surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; + surface->base.u.tex.level = level; + + surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, + rtex, level); + return &surface->base; +} + +static void r600_surface_destroy(struct pipe_context *pipe, + struct pipe_surface *surface) +{ + pipe_resource_reference(&surface->texture, NULL); + FREE(surface); +} + +struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, + const struct pipe_resource *templ, + struct winsys_handle *whandle) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct pb_buffer *buf = NULL; + unsigned stride = 0; + unsigned array_mode = 0; + enum radeon_bo_layout micro, macro; + + /* Support only 2D textures without mipmaps */ + if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || + templ->depth0 != 1 || templ->last_level != 0) + return NULL; + + buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); + if (!buf) + return NULL; + + rscreen->ws->buffer_get_tiling(buf, µ, ¯o, NULL, NULL, NULL, NULL, NULL); + +#if 0 + if (macro == RADEON_LAYOUT_TILED) + array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; + else if (micro == RADEON_LAYOUT_TILED) + array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; + else +#endif + array_mode = 0; + + return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, + stride, 0, buf, FALSE); +} + +int r600_texture_depth_flush(struct pipe_context *ctx, + struct pipe_resource *texture, boolean just_create) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; + struct pipe_resource resource; + + if (rtex->flushed_depth_texture) + goto out; + + resource.target = texture->target; + resource.format = texture->format; + resource.width0 = texture->width0; + resource.height0 = texture->height0; + resource.depth0 = texture->depth0; + resource.array_size = texture->array_size; + resource.last_level = texture->last_level; + resource.nr_samples = texture->nr_samples; + resource.usage = PIPE_USAGE_DYNAMIC; + resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL; + resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags; + + rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); + if (rtex->flushed_depth_texture == NULL) { + R600_ERR("failed to create temporary texture to hold untiled copy\n"); + return -ENOMEM; + } + + ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; +out: + if (just_create) + return 0; + + /* XXX: only do this if the depth texture has actually changed: + */ + r600_blit_uncompress_depth(ctx, rtex); + return 0; +} + +/* Needs adjustment for pixelformat: + */ +static INLINE unsigned u_box_volume( const struct pipe_box *box ) +{ + return box->width * box->depth * box->height; +}; + +struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, + struct pipe_resource *texture, + unsigned level, + unsigned usage, + const struct pipe_box *box) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; + struct pipe_resource resource; + struct r600_transfer *trans; + int r; + boolean use_staging_texture = FALSE; + +#if 0 + /* We cannot map a tiled texture directly because the data is + * in a different order, therefore we do detiling using a blit. + * + * Also, use a temporary in GTT memory for read transfers, as + * the CPU is much happier reading out of cached system memory + * than uncached VRAM. + */ + if (R600_TEX_IS_TILED(rtex, level)) + use_staging_texture = TRUE; +#endif + + if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) + use_staging_texture = TRUE; + + /* XXX: Use a staging texture for uploads if the underlying BO + * is busy. No interface for checking that currently? so do + * it eagerly whenever the transfer doesn't require a readback + * and might block. + */ + if ((usage & PIPE_TRANSFER_WRITE) && + !(usage & (PIPE_TRANSFER_READ | + PIPE_TRANSFER_DONTBLOCK | + PIPE_TRANSFER_UNSYNCHRONIZED))) + use_staging_texture = TRUE; + + if (!permit_hardware_blit(ctx->screen, texture) || + (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) + use_staging_texture = FALSE; + + if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) + return NULL; + + trans = CALLOC_STRUCT(r600_transfer); + if (trans == NULL) + return NULL; + pipe_resource_reference(&trans->transfer.resource, texture); + trans->transfer.level = level; + trans->transfer.usage = usage; + trans->transfer.box = *box; + if (rtex->depth) { + /* XXX: only readback the rectangle which is being mapped? + */ + /* XXX: when discard is true, no need to read back from depth texture + */ + r = r600_texture_depth_flush(ctx, texture, FALSE); + if (r < 0) { + R600_ERR("failed to create temporary texture to hold untiled copy\n"); + pipe_resource_reference(&trans->transfer.resource, NULL); + FREE(trans); + return NULL; + } + trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; + trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); + return &trans->transfer; + } else if (use_staging_texture) { + resource.target = PIPE_TEXTURE_2D; + resource.format = texture->format; + resource.width0 = box->width; + resource.height0 = box->height; + resource.depth0 = 1; + resource.array_size = 1; + resource.last_level = 0; + resource.nr_samples = 0; + resource.usage = PIPE_USAGE_STAGING; + resource.bind = 0; + resource.flags = R600_RESOURCE_FLAG_TRANSFER; + /* For texture reading, the temporary (detiled) texture is used as + * a render target when blitting from a tiled texture. */ + if (usage & PIPE_TRANSFER_READ) { + resource.bind |= PIPE_BIND_RENDER_TARGET; + } + /* For texture writing, the temporary texture is used as a sampler + * when blitting into a tiled texture. */ + if (usage & PIPE_TRANSFER_WRITE) { + resource.bind |= PIPE_BIND_SAMPLER_VIEW; + } + /* Create the temporary texture. */ + trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); + if (trans->staging_texture == NULL) { + R600_ERR("failed to create temporary texture to hold untiled copy\n"); + pipe_resource_reference(&trans->transfer.resource, NULL); + FREE(trans); + return NULL; + } + + trans->transfer.stride = + ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0]; + if (usage & PIPE_TRANSFER_READ) { + r600_copy_to_staging_texture(ctx, trans); + /* Always referenced in the blit. */ + radeonsi_flush(ctx, NULL, 0); + } + return &trans->transfer; + } + trans->transfer.stride = rtex->pitch_in_bytes[level]; + trans->transfer.layer_stride = rtex->layer_size[level]; + trans->offset = r600_texture_get_offset(rtex, level, box->z); + return &trans->transfer; +} + +void r600_texture_transfer_destroy(struct pipe_context *ctx, + struct pipe_transfer *transfer) +{ + struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; + struct pipe_resource *texture = transfer->resource; + struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; + + if (rtransfer->staging_texture) { + if (transfer->usage & PIPE_TRANSFER_WRITE) { + r600_copy_from_staging_texture(ctx, rtransfer); + } + pipe_resource_reference(&rtransfer->staging_texture, NULL); + } + + if (rtex->depth && !rtex->is_flushing_texture) { + if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) + r600_blit_push_depth(ctx, rtex); + } + + pipe_resource_reference(&transfer->resource, NULL); + FREE(transfer); +} + +void* r600_texture_transfer_map(struct pipe_context *ctx, + struct pipe_transfer* transfer) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; + struct pb_buffer *buf; + enum pipe_format format = transfer->resource->format; + unsigned offset = 0; + char *map; + + if (rtransfer->staging_texture) { + buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; + } else { + struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; + + if (rtex->flushed_depth_texture) + buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; + else + buf = ((struct r600_resource *)transfer->resource)->buf; + + offset = rtransfer->offset + + transfer->box.y / util_format_get_blockheight(format) * transfer->stride + + transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); + } + + if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { + return NULL; + } + + return map + offset; +} + +void r600_texture_transfer_unmap(struct pipe_context *ctx, + struct pipe_transfer* transfer) +{ + struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; + struct r600_context *rctx = (struct r600_context*)ctx; + struct pb_buffer *buf; + + if (rtransfer->staging_texture) { + buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; + } else { + struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; + + if (rtex->flushed_depth_texture) { + buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; + } else { + buf = ((struct r600_resource *)transfer->resource)->buf; + } + } + rctx->ws->buffer_unmap(buf); +} + +void r600_init_surface_functions(struct r600_context *r600) +{ + r600->context.create_surface = r600_create_surface; + r600->context.surface_destroy = r600_surface_destroy; +} diff --git a/src/gallium/drivers/radeonsi/r600_translate.c b/src/gallium/drivers/radeonsi/r600_translate.c new file mode 100644 index 00000000000..6551044b553 --- /dev/null +++ b/src/gallium/drivers/radeonsi/r600_translate.c @@ -0,0 +1,54 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie <airlied@redhat.com> + */ + +#include "util/u_index_modify.h" +#include "util/u_inlines.h" +#include "util/u_upload_mgr.h" +#include "radeonsi_pipe.h" + + +void r600_translate_index_buffer(struct r600_context *r600, + struct pipe_index_buffer *ib, + unsigned count) +{ + struct pipe_resource *out_buffer = NULL; + unsigned out_offset; + void *ptr; + + switch (ib->index_size) { + case 1: + u_upload_alloc(r600->vbuf_mgr->uploader, 0, count * 2, + &out_offset, &out_buffer, &ptr); + + util_shorten_ubyte_elts_to_userptr( + &r600->context, ib->buffer, 0, ib->offset, count, ptr); + + pipe_resource_reference(&ib->buffer, NULL); + ib->buffer = out_buffer; + ib->offset = out_offset; + ib->index_size = 2; + break; + } +} diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c new file mode 100644 index 00000000000..9e849525cc9 --- /dev/null +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -0,0 +1,731 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdio.h> +#include <errno.h> +#include "pipe/p_defines.h" +#include "pipe/p_state.h" +#include "pipe/p_context.h" +#include "tgsi/tgsi_scan.h" +#include "tgsi/tgsi_parse.h" +#include "tgsi/tgsi_util.h" +#include "util/u_blitter.h" +#include "util/u_double_list.h" +#include "util/u_format.h" +#include "util/u_format_s3tc.h" +#include "util/u_transfer.h" +#include "util/u_surface.h" +#include "util/u_pack_color.h" +#include "util/u_memory.h" +#include "util/u_inlines.h" +#include "util/u_upload_mgr.h" +#include "vl/vl_decoder.h" +#include "vl/vl_video_buffer.h" +#include "os/os_time.h" +#include "pipebuffer/pb_buffer.h" +#include "r600.h" +#include "sid.h" +#include "r600_resource.h" +#include "radeonsi_pipe.h" +#include "r600_hw_context_priv.h" + +/* + * pipe_context + */ +static struct r600_fence *r600_create_fence(struct r600_context *rctx) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_fence *fence = NULL; + + pipe_mutex_lock(rscreen->fences.mutex); + + if (!rscreen->fences.bo) { + /* Create the shared buffer object */ + rscreen->fences.bo = (struct r600_resource*) + pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, + PIPE_USAGE_STAGING, 4096); + if (!rscreen->fences.bo) { + R600_ERR("r600: failed to create bo for fence objects\n"); + goto out; + } + rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf, + rctx->cs, + PIPE_TRANSFER_READ_WRITE); + } + + if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { + struct r600_fence *entry; + + /* Try to find a freed fence that has been signalled */ + LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { + if (rscreen->fences.data[entry->index] != 0) { + LIST_DELINIT(&entry->head); + fence = entry; + break; + } + } + } + + if (!fence) { + /* Allocate a new fence */ + struct r600_fence_block *block; + unsigned index; + + if ((rscreen->fences.next_index + 1) >= 1024) { + R600_ERR("r600: too many concurrent fences\n"); + goto out; + } + + index = rscreen->fences.next_index++; + + if (!(index % FENCE_BLOCK_SIZE)) { + /* Allocate a new block */ + block = CALLOC_STRUCT(r600_fence_block); + if (block == NULL) + goto out; + + LIST_ADD(&block->head, &rscreen->fences.blocks); + } else { + block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); + } + + fence = &block->fences[index % FENCE_BLOCK_SIZE]; + fence->index = index; + } + + pipe_reference_init(&fence->reference, 1); + + rscreen->fences.data[fence->index] = 0; + r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); + + /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ + fence->sleep_bo = (struct r600_resource*) + pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, + PIPE_USAGE_STAGING, 1); + /* Add the fence as a dummy relocation. */ + r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); + +out: + pipe_mutex_unlock(rscreen->fences.mutex); + return fence; +} + + +void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, + unsigned flags) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_fence **rfence = (struct r600_fence**)fence; + struct pipe_query *render_cond = NULL; + unsigned render_cond_mode = 0; + + if (rfence) + *rfence = r600_create_fence(rctx); + + /* Disable render condition. */ + if (rctx->current_render_cond) { + render_cond = rctx->current_render_cond; + render_cond_mode = rctx->current_render_cond_mode; + ctx->render_condition(ctx, NULL, 0); + } + + r600_context_flush(rctx, flags); + + /* Re-enable render condition. */ + if (render_cond) { + ctx->render_condition(ctx, render_cond, render_cond_mode); + } +} + +static void r600_flush_from_st(struct pipe_context *ctx, + struct pipe_fence_handle **fence) +{ + radeonsi_flush(ctx, fence, 0); +} + +static void r600_flush_from_winsys(void *ctx, unsigned flags) +{ + radeonsi_flush((struct pipe_context*)ctx, NULL, flags); +} + +static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) +{ + pipe_mutex_lock(rscreen->mutex_num_contexts); + if (diff > 0) { + rscreen->num_contexts++; + + if (rscreen->num_contexts > 1) + util_slab_set_thread_safety(&rscreen->pool_buffers, + UTIL_SLAB_MULTITHREADED); + } else { + rscreen->num_contexts--; + + if (rscreen->num_contexts <= 1) + util_slab_set_thread_safety(&rscreen->pool_buffers, + UTIL_SLAB_SINGLETHREADED); + } + pipe_mutex_unlock(rscreen->mutex_num_contexts); +} + +static void r600_destroy_context(struct pipe_context *context) +{ + struct r600_context *rctx = (struct r600_context *)context; + + rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); + util_unreference_framebuffer_state(&rctx->framebuffer); + + r600_context_fini(rctx); + + util_blitter_destroy(rctx->blitter); + + for (int i = 0; i < R600_PIPE_NSTATES; i++) { + free(rctx->states[i]); + } + + u_vbuf_destroy(rctx->vbuf_mgr); + util_slab_destroy(&rctx->pool_transfers); + + r600_update_num_contexts(rctx->screen, -1); + + FREE(rctx); +} + +static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) +{ + struct r600_context *rctx = CALLOC_STRUCT(r600_context); + struct r600_screen* rscreen = (struct r600_screen *)screen; + + if (rctx == NULL) + return NULL; + + r600_update_num_contexts(rscreen, 1); + + rctx->context.screen = screen; + rctx->context.priv = priv; + rctx->context.destroy = r600_destroy_context; + rctx->context.flush = r600_flush_from_st; + + /* Easy accessing of screen/winsys. */ + rctx->screen = rscreen; + rctx->ws = rscreen->ws; + rctx->family = rscreen->family; + rctx->chip_class = rscreen->chip_class; + + r600_init_blit_functions(rctx); + r600_init_query_functions(rctx); + r600_init_context_resource_functions(rctx); + r600_init_surface_functions(rctx); + rctx->context.draw_vbo = r600_draw_vbo; + + rctx->context.create_video_decoder = vl_create_decoder; + rctx->context.create_video_buffer = vl_video_buffer_create; + + r600_init_common_atoms(rctx); + + switch (rctx->chip_class) { + case TAHITI: + cayman_init_state_functions(rctx); + if (si_context_init(rctx)) { + r600_destroy_context(&rctx->context); + return NULL; + } + si_init_config(rctx); + rctx->custom_dsa_flush = cayman_create_db_flush_dsa(rctx); + break; + default: + R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); + r600_destroy_context(&rctx->context); + return NULL; + } + + rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); + + util_slab_create(&rctx->pool_transfers, + sizeof(struct pipe_transfer), 64, + UTIL_SLAB_SINGLETHREADED); + + rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, + PIPE_BIND_VERTEX_BUFFER | + PIPE_BIND_INDEX_BUFFER | + PIPE_BIND_CONSTANT_BUFFER, + U_VERTEX_FETCH_DWORD_ALIGNED); + if (!rctx->vbuf_mgr) { + r600_destroy_context(&rctx->context); + return NULL; + } + rctx->vbuf_mgr->caps.format_fixed32 = 0; + + rctx->blitter = util_blitter_create(&rctx->context); + if (rctx->blitter == NULL) { + r600_destroy_context(&rctx->context); + return NULL; + } + + LIST_INITHEAD(&rctx->dirty_states); + + r600_get_backend_mask(rctx); /* this emits commands and must be last */ + + return &rctx->context; +} + +/* + * pipe_screen + */ +static const char* r600_get_vendor(struct pipe_screen* pscreen) +{ + return "X.Org"; +} + +static const char *r600_get_family_name(enum radeon_family family) +{ + switch(family) { + case CHIP_CAYMAN: return "AMD CAYMAN"; + default: return "AMD unknown"; + } +} + +static const char* r600_get_name(struct pipe_screen* pscreen) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + + return r600_get_family_name(rscreen->family); +} + +static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + enum radeon_family family = rscreen->family; + + switch (param) { + /* Supported features (boolean caps). */ + case PIPE_CAP_NPOT_TEXTURES: + case PIPE_CAP_TWO_SIDED_STENCIL: + case PIPE_CAP_DUAL_SOURCE_BLEND: + case PIPE_CAP_ANISOTROPIC_FILTER: + case PIPE_CAP_POINT_SPRITE: + case PIPE_CAP_OCCLUSION_QUERY: + case PIPE_CAP_TEXTURE_SHADOW_MAP: + case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + case PIPE_CAP_BLEND_EQUATION_SEPARATE: + case PIPE_CAP_TEXTURE_SWIZZLE: + case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: + case PIPE_CAP_DEPTH_CLIP_DISABLE: + case PIPE_CAP_SHADER_STENCIL_EXPORT: + case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: + case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: + case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: + case PIPE_CAP_SM3: + case PIPE_CAP_SEAMLESS_CUBE_MAP: + case PIPE_CAP_PRIMITIVE_RESTART: + case PIPE_CAP_CONDITIONAL_RENDER: + case PIPE_CAP_TEXTURE_BARRIER: + case PIPE_CAP_INDEP_BLEND_ENABLE: + case PIPE_CAP_INDEP_BLEND_FUNC: + case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: + case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: + return 1; + + case PIPE_CAP_GLSL_FEATURE_LEVEL: + return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120; + + /* Unsupported features. */ + case PIPE_CAP_TGSI_INSTANCEID: + case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: + case PIPE_CAP_SCALED_RESOLVE: + case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: + case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: + case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: + case PIPE_CAP_VERTEX_COLOR_CLAMPED: + case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: + return 0; + + /* Stream output. */ + case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: + return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0; + case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: + return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0; + case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: + case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: + return 16*4; + + /* Texturing. */ + case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: + return 15; + case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: + return rscreen->info.drm_minor >= 9 ? 16384 : 0; + case PIPE_CAP_MAX_COMBINED_SAMPLERS: + return 32; + + /* Render targets. */ + case PIPE_CAP_MAX_RENDER_TARGETS: + /* FIXME some r6xx are buggy and can only do 4 */ + return 8; + + /* Timer queries, present when the clock frequency is non zero. */ + case PIPE_CAP_TIMER_QUERY: + return rscreen->info.r600_clock_crystal_freq != 0; + + case PIPE_CAP_MIN_TEXEL_OFFSET: + return -8; + + case PIPE_CAP_MAX_TEXEL_OFFSET: + return 7; + } + return 0; +} + +static float r600_get_paramf(struct pipe_screen* pscreen, + enum pipe_capf param) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + enum radeon_family family = rscreen->family; + + switch (param) { + case PIPE_CAPF_MAX_LINE_WIDTH: + case PIPE_CAPF_MAX_LINE_WIDTH_AA: + case PIPE_CAPF_MAX_POINT_WIDTH: + case PIPE_CAPF_MAX_POINT_WIDTH_AA: + return 16384.0f; + case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: + return 16.0f; + case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: + return 16.0f; + case PIPE_CAPF_GUARD_BAND_LEFT: + case PIPE_CAPF_GUARD_BAND_TOP: + case PIPE_CAPF_GUARD_BAND_RIGHT: + case PIPE_CAPF_GUARD_BAND_BOTTOM: + return 0.0f; + } + return 0.0f; +} + +static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + switch(shader) + { + case PIPE_SHADER_FRAGMENT: + case PIPE_SHADER_VERTEX: + break; + case PIPE_SHADER_GEOMETRY: + /* TODO: support and enable geometry programs */ + return 0; + default: + /* TODO: support tessellation */ + return 0; + } + + /* TODO: all these should be fixed, since r600 surely supports much more! */ + switch (param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 16384; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return 8; /* FIXME */ + case PIPE_SHADER_CAP_MAX_INPUTS: + if(shader == PIPE_SHADER_FRAGMENT) + return 34; + else + return 32; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 256; /* Max native temporaries. */ + case PIPE_SHADER_CAP_MAX_ADDRS: + /* FIXME Isn't this equal to TEMPS? */ + return 1; /* Max native address registers */ + case PIPE_SHADER_CAP_MAX_CONSTS: + return R600_MAX_CONST_BUFFER_SIZE; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return R600_MAX_CONST_BUFFERS; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* FIXME */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: + case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: + case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: + case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: + case PIPE_SHADER_CAP_INTEGERS: + return 0; + case PIPE_SHADER_CAP_SUBROUTINES: + return 0; + case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: + return 16; + } + return 0; +} + +static int r600_get_video_param(struct pipe_screen *screen, + enum pipe_video_profile profile, + enum pipe_video_cap param) +{ + switch (param) { + case PIPE_VIDEO_CAP_SUPPORTED: + return vl_profile_supported(screen, profile); + case PIPE_VIDEO_CAP_NPOT_TEXTURES: + return 1; + case PIPE_VIDEO_CAP_MAX_WIDTH: + case PIPE_VIDEO_CAP_MAX_HEIGHT: + return vl_video_buffer_max_size(screen); + case PIPE_VIDEO_CAP_PREFERED_FORMAT: + return PIPE_FORMAT_NV12; + default: + return 0; + } +} + +static void r600_destroy_screen(struct pipe_screen* pscreen) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + + if (rscreen == NULL) + return; + + if (rscreen->fences.bo) { + struct r600_fence_block *entry, *tmp; + + LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { + LIST_DEL(&entry->head); + FREE(entry); + } + + rscreen->ws->buffer_unmap(rscreen->fences.bo->buf); + pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); + } + pipe_mutex_destroy(rscreen->fences.mutex); + + rscreen->ws->destroy(rscreen->ws); + + util_slab_destroy(&rscreen->pool_buffers); + pipe_mutex_destroy(rscreen->mutex_num_contexts); + FREE(rscreen); +} + +static void r600_fence_reference(struct pipe_screen *pscreen, + struct pipe_fence_handle **ptr, + struct pipe_fence_handle *fence) +{ + struct r600_fence **oldf = (struct r600_fence**)ptr; + struct r600_fence *newf = (struct r600_fence*)fence; + + if (pipe_reference(&(*oldf)->reference, &newf->reference)) { + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + pipe_mutex_lock(rscreen->fences.mutex); + pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); + LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); + pipe_mutex_unlock(rscreen->fences.mutex); + } + + *ptr = fence; +} + +static boolean r600_fence_signalled(struct pipe_screen *pscreen, + struct pipe_fence_handle *fence) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct r600_fence *rfence = (struct r600_fence*)fence; + + return rscreen->fences.data[rfence->index]; +} + +static boolean r600_fence_finish(struct pipe_screen *pscreen, + struct pipe_fence_handle *fence, + uint64_t timeout) +{ + struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct r600_fence *rfence = (struct r600_fence*)fence; + int64_t start_time = 0; + unsigned spins = 0; + + if (timeout != PIPE_TIMEOUT_INFINITE) { + start_time = os_time_get(); + + /* Convert to microseconds. */ + timeout /= 1000; + } + + while (rscreen->fences.data[rfence->index] == 0) { + /* Special-case infinite timeout - wait for the dummy BO to become idle */ + if (timeout == PIPE_TIMEOUT_INFINITE) { + rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); + break; + } + + /* The dummy BO will be busy until the CS including the fence has completed, or + * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ + if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) + break; + + if (++spins % 256) + continue; +#ifdef PIPE_OS_UNIX + sched_yield(); +#else + os_time_sleep(10); +#endif + if (timeout != PIPE_TIMEOUT_INFINITE && + os_time_get() - start_time >= timeout) { + break; + } + } + + return rscreen->fences.data[rfence->index] != 0; +} + +static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) +{ + switch (tiling_config & 0xf) { + case 0: + rscreen->tiling_info.num_channels = 1; + break; + case 1: + rscreen->tiling_info.num_channels = 2; + break; + case 2: + rscreen->tiling_info.num_channels = 4; + break; + case 3: + rscreen->tiling_info.num_channels = 8; + break; + default: + return -EINVAL; + } + + switch ((tiling_config & 0xf0) >> 4) { + case 0: + rscreen->tiling_info.num_banks = 4; + break; + case 1: + rscreen->tiling_info.num_banks = 8; + break; + case 2: + rscreen->tiling_info.num_banks = 16; + break; + default: + return -EINVAL; + } + + switch ((tiling_config & 0xf00) >> 8) { + case 0: + rscreen->tiling_info.group_bytes = 256; + break; + case 1: + rscreen->tiling_info.group_bytes = 512; + break; + default: + return -EINVAL; + } + return 0; +} + +static int r600_init_tiling(struct r600_screen *rscreen) +{ + uint32_t tiling_config = rscreen->info.r600_tiling_config; + + /* set default group bytes, overridden by tiling info ioctl */ + rscreen->tiling_info.group_bytes = 512; + + if (!tiling_config) + return 0; + + return evergreen_interpret_tiling(rscreen, tiling_config); +} + +static unsigned radeon_family_from_device(unsigned device) +{ + switch (device) { +#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; +#include "pci_ids/radeonsi_pci_ids.h" +#undef CHIPSET + default: + return CHIP_UNKNOWN; + } +} + +struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) +{ + struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); + if (rscreen == NULL) { + return NULL; + } + + rscreen->ws = ws; + ws->query_info(ws, &rscreen->info); + + rscreen->family = radeon_family_from_device(rscreen->info.pci_id); + if (rscreen->family == CHIP_UNKNOWN) { + fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); + FREE(rscreen); + return NULL; + } + + /* setup class */ + if (rscreen->family >= CHIP_TAHITI) { + rscreen->chip_class = TAHITI; + } else { + fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family); + FREE(rscreen); + return NULL; + } + + if (r600_init_tiling(rscreen)) { + FREE(rscreen); + return NULL; + } + + rscreen->screen.destroy = r600_destroy_screen; + rscreen->screen.get_name = r600_get_name; + rscreen->screen.get_vendor = r600_get_vendor; + rscreen->screen.get_param = r600_get_param; + rscreen->screen.get_shader_param = r600_get_shader_param; + rscreen->screen.get_paramf = r600_get_paramf; + rscreen->screen.get_video_param = r600_get_video_param; + rscreen->screen.is_format_supported = si_is_format_supported; + rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; + rscreen->screen.context_create = r600_create_context; + rscreen->screen.fence_reference = r600_fence_reference; + rscreen->screen.fence_signalled = r600_fence_signalled; + rscreen->screen.fence_finish = r600_fence_finish; + r600_init_screen_resource_functions(&rscreen->screen); + + util_format_s3tc_init(); + + util_slab_create(&rscreen->pool_buffers, + sizeof(struct r600_resource), 64, + UTIL_SLAB_SINGLETHREADED); + + pipe_mutex_init(rscreen->mutex_num_contexts); + + rscreen->fences.bo = NULL; + rscreen->fences.data = NULL; + rscreen->fences.next_index = 0; + LIST_INITHEAD(&rscreen->fences.pool); + LIST_INITHEAD(&rscreen->fences.blocks); + pipe_mutex_init(rscreen->fences.mutex); + + return &rscreen->screen; +} diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h new file mode 100644 index 00000000000..f4a1219d860 --- /dev/null +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h @@ -0,0 +1,490 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef RADEONSI_PIPE_H +#define RADEONSI_PIPE_H + +#include "../../winsys/radeon/drm/radeon_winsys.h" + +#include "pipe/p_state.h" +#include "pipe/p_screen.h" +#include "pipe/p_context.h" +#include "util/u_format.h" +#include "util/u_math.h" +#include "util/u_slab.h" +#include "util/u_vbuf.h" +#include "r600.h" +#include "radeonsi_public.h" +#include "r600_resource.h" + +#define R600_MAX_CONST_BUFFERS 1 +#define R600_MAX_CONST_BUFFER_SIZE 4096 + +#ifdef PIPE_ARCH_BIG_ENDIAN +#define R600_BIG_ENDIAN 1 +#else +#define R600_BIG_ENDIAN 0 +#endif + +enum r600_atom_flags { + /* When set, atoms are added at the beginning of the dirty list + * instead of the end. */ + EMIT_EARLY = (1 << 0) +}; + +/* This encapsulates a state or an operation which can emitted into the GPU + * command stream. It's not limited to states only, it can be used for anything + * that wants to write commands into the CS (e.g. cache flushes). */ +struct r600_atom { + void (*emit)(struct r600_context *ctx, struct r600_atom *state); + + unsigned num_dw; + enum r600_atom_flags flags; + bool dirty; + + struct list_head head; +}; + +struct r600_atom_surface_sync { + struct r600_atom atom; + unsigned flush_flags; /* CP_COHER_CNTL */ +}; + +enum r600_pipe_state_id { + R600_PIPE_STATE_BLEND = 0, + R600_PIPE_STATE_BLEND_COLOR, + R600_PIPE_STATE_CONFIG, + R600_PIPE_STATE_SEAMLESS_CUBEMAP, + R600_PIPE_STATE_CLIP, + R600_PIPE_STATE_SCISSOR, + R600_PIPE_STATE_VIEWPORT, + R600_PIPE_STATE_RASTERIZER, + R600_PIPE_STATE_VGT, + R600_PIPE_STATE_FRAMEBUFFER, + R600_PIPE_STATE_DSA, + R600_PIPE_STATE_STENCIL_REF, + R600_PIPE_STATE_PS_SHADER, + R600_PIPE_STATE_VS_SHADER, + R600_PIPE_STATE_CONSTANT, + R600_PIPE_STATE_SAMPLER, + R600_PIPE_STATE_RESOURCE, + R600_PIPE_STATE_POLYGON_OFFSET, + R600_PIPE_NSTATES +}; + +struct r600_pipe_fences { + struct r600_resource *bo; + unsigned *data; + unsigned next_index; + /* linked list of preallocated blocks */ + struct list_head blocks; + /* linked list of freed fences */ + struct list_head pool; + pipe_mutex mutex; +}; + +struct r600_screen { + struct pipe_screen screen; + struct radeon_winsys *ws; + unsigned family; + enum chip_class chip_class; + struct radeon_info info; + struct r600_tiling_info tiling_info; + struct util_slab_mempool pool_buffers; + struct r600_pipe_fences fences; + + unsigned num_contexts; + + /* for thread-safe write accessing to num_contexts */ + pipe_mutex mutex_num_contexts; +}; + +struct si_pipe_sampler_view { + struct pipe_sampler_view base; + uint32_t state[8]; +}; + +struct si_pipe_sampler_state { + uint32_t val[4]; +}; + +struct r600_pipe_rasterizer { + struct r600_pipe_state rstate; + boolean flatshade; + unsigned sprite_coord_enable; + unsigned pa_sc_line_stipple; + unsigned pa_su_sc_mode_cntl; + unsigned pa_cl_clip_cntl; + unsigned pa_cl_vs_out_cntl; + float offset_units; + float offset_scale; +}; + +struct r600_pipe_blend { + struct r600_pipe_state rstate; + unsigned cb_target_mask; + unsigned cb_color_control; +}; + +struct r600_pipe_dsa { + struct r600_pipe_state rstate; + unsigned alpha_ref; + unsigned db_render_override; + unsigned db_render_control; + ubyte valuemask[2]; + ubyte writemask[2]; +}; + +struct r600_vertex_element +{ + unsigned count; + struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; + struct u_vbuf_elements *vmgr_elements; + unsigned fs_size; + struct r600_pipe_state rstate; + /* if offset is to big for fetch instructio we need to alterate + * offset of vertex buffer, record here the offset need to add + */ + unsigned vbuffer_need_offset; + unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; +}; + +struct r600_shader_io { + unsigned name; + unsigned gpr; + unsigned done; + int sid; + unsigned interpolate; + boolean centroid; + unsigned lds_pos; /* for evergreen */ +}; + +struct r600_shader { + unsigned ninput; + unsigned noutput; + struct r600_shader_io input[32]; + struct r600_shader_io output[32]; + boolean uses_kill; + boolean fs_write_all; + unsigned nr_cbufs; +}; + +struct si_pipe_shader { + struct r600_shader shader; + struct r600_pipe_state rstate; + struct r600_resource *bo; + struct r600_vertex_element vertex_elements; + struct tgsi_token *tokens; + unsigned num_sgprs; + unsigned num_vgprs; + unsigned spi_ps_input_ena; + unsigned sprite_coord_enable; + struct pipe_stream_output_info so; + unsigned so_strides[4]; +}; + +/* needed for blitter save */ +#define NUM_TEX_UNITS 16 + +struct r600_textures_info { + struct r600_pipe_state rstate; + struct si_pipe_sampler_view *views[NUM_TEX_UNITS]; + struct si_pipe_sampler_state *samplers[NUM_TEX_UNITS]; + unsigned n_views; + unsigned n_samplers; + bool samplers_dirty; + bool is_array_sampler[NUM_TEX_UNITS]; +}; + +struct r600_fence { + struct pipe_reference reference; + unsigned index; /* in the shared bo */ + struct r600_resource *sleep_bo; + struct list_head head; +}; + +#define FENCE_BLOCK_SIZE 16 + +struct r600_fence_block { + struct r600_fence fences[FENCE_BLOCK_SIZE]; + struct list_head head; +}; + +#define R600_CONSTANT_ARRAY_SIZE 256 +#define R600_RESOURCE_ARRAY_SIZE 160 + +struct r600_stencil_ref +{ + ubyte ref_value[2]; + ubyte valuemask[2]; + ubyte writemask[2]; +}; + +struct r600_context { + struct pipe_context context; + struct blitter_context *blitter; + enum radeon_family family; + enum chip_class chip_class; + void *custom_dsa_flush; + struct r600_screen *screen; + struct radeon_winsys *ws; + struct r600_pipe_state *states[R600_PIPE_NSTATES]; + struct r600_vertex_element *vertex_elements; + struct pipe_framebuffer_state framebuffer; + unsigned cb_target_mask; + unsigned cb_color_control; + unsigned pa_sc_line_stipple; + unsigned pa_su_sc_mode_cntl; + unsigned pa_cl_clip_cntl; + unsigned pa_cl_vs_out_cntl; + /* for saving when using blitter */ + struct pipe_stencil_ref stencil_ref; + struct pipe_viewport_state viewport; + struct pipe_clip_state clip; + struct r600_pipe_state config; + struct si_pipe_shader *ps_shader; + struct si_pipe_shader *vs_shader; + struct r600_pipe_state vs_const_buffer; + struct r600_pipe_state vs_user_data; + struct r600_pipe_state ps_const_buffer; + struct r600_pipe_rasterizer *rasterizer; + struct r600_pipe_state vgt; + struct r600_pipe_state spi; + struct pipe_query *current_render_cond; + unsigned current_render_cond_mode; + struct pipe_query *saved_render_cond; + unsigned saved_render_cond_mode; + /* shader information */ + unsigned sprite_coord_enable; + boolean export_16bpc; + unsigned alpha_ref; + boolean alpha_ref_dirty; + unsigned nr_cbufs; + struct r600_textures_info vs_samplers; + struct r600_textures_info ps_samplers; + boolean shader_dirty; + + struct u_vbuf *vbuf_mgr; + struct util_slab_mempool pool_transfers; + boolean have_depth_texture, have_depth_fb; + + unsigned default_ps_gprs, default_vs_gprs; + + /* States based on r600_state. */ + struct list_head dirty_states; + struct r600_atom_surface_sync atom_surface_sync; + struct r600_atom atom_r6xx_flush_and_inv; + + /* Below are variables from the old r600_context. + */ + struct radeon_winsys_cs *cs; + + struct r600_range *range; + unsigned nblocks; + struct r600_block **blocks; + struct list_head dirty; + struct list_head enable_list; + unsigned pm4_dirty_cdwords; + unsigned ctx_pm4_ndwords; + unsigned init_dwords; + + /* The list of active queries. Only one query of each type can be active. */ + struct list_head active_query_list; + unsigned num_cs_dw_queries_suspend; + unsigned num_cs_dw_streamout_end; + + unsigned backend_mask; + unsigned max_db; /* for OQ */ + unsigned flags; + boolean predicate_drawing; + + unsigned num_so_targets; + struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; + boolean streamout_start; + unsigned streamout_append_bitmask; + unsigned *vs_so_stride_in_dw; + unsigned *vs_shader_so_strides; +}; + +static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) +{ + atom->emit(rctx, atom); + atom->dirty = false; + if (atom->head.next && atom->head.prev) + LIST_DELINIT(&atom->head); +} + +static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) +{ + if (!state->dirty) { + if (state->flags & EMIT_EARLY) { + LIST_ADD(&state->head, &rctx->dirty_states); + } else { + LIST_ADDTAIL(&state->head, &rctx->dirty_states); + } + state->dirty = true; + } +} + +/* evergreen_state.c */ +void cayman_init_state_functions(struct r600_context *rctx); +void si_init_config(struct r600_context *rctx); +void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader); +void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader); +void si_update_spi_map(struct r600_context *rctx); +void *cayman_create_db_flush_dsa(struct r600_context *rctx); +void cayman_polygon_offset_update(struct r600_context *rctx); +uint32_t si_translate_vertexformat(struct pipe_screen *screen, + enum pipe_format format, + const struct util_format_description *desc, + int first_non_void); +boolean si_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned sample_count, + unsigned usage); + +/* r600_blit.c */ +void r600_init_blit_functions(struct r600_context *rctx); +void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); +void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); +void r600_flush_depth_textures(struct r600_context *rctx); + +/* r600_buffer.c */ +bool r600_init_resource(struct r600_screen *rscreen, + struct r600_resource *res, + unsigned size, unsigned alignment, + unsigned bind, unsigned usage); +struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, + const struct pipe_resource *templ); +struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, + void *ptr, unsigned bytes, + unsigned bind); +void r600_upload_index_buffer(struct r600_context *rctx, + struct pipe_index_buffer *ib, unsigned count); + + +/* r600_pipe.c */ +void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, + unsigned flags); + +/* r600_query.c */ +void r600_init_query_functions(struct r600_context *rctx); + +/* r600_resource.c */ +void r600_init_context_resource_functions(struct r600_context *r600); + +/* radeonsi_shader.c */ +int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader); +void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader); + +/* r600_texture.c */ +void r600_init_screen_texture_functions(struct pipe_screen *screen); +void r600_init_surface_functions(struct r600_context *r600); +unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, + unsigned level, unsigned layer); + +/* r600_translate.c */ +void r600_translate_index_buffer(struct r600_context *r600, + struct pipe_index_buffer *ib, + unsigned count); + +/* r600_state_common.c */ +void r600_init_common_atoms(struct r600_context *rctx); +unsigned r600_get_cb_flush_flags(struct r600_context *rctx); +void r600_texture_barrier(struct pipe_context *ctx); +void r600_set_index_buffer(struct pipe_context *ctx, + const struct pipe_index_buffer *ib); +void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, + const struct pipe_vertex_buffer *buffers); +void *si_create_vertex_elements(struct pipe_context *ctx, + unsigned count, + const struct pipe_vertex_element *elements); +void r600_delete_vertex_element(struct pipe_context *ctx, void *state); +void r600_bind_blend_state(struct pipe_context *ctx, void *state); +void r600_bind_dsa_state(struct pipe_context *ctx, void *state); +void r600_bind_rs_state(struct pipe_context *ctx, void *state); +void r600_delete_rs_state(struct pipe_context *ctx, void *state); +void r600_sampler_view_destroy(struct pipe_context *ctx, + struct pipe_sampler_view *state); +void r600_delete_state(struct pipe_context *ctx, void *state); +void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); +void *si_create_shader_state(struct pipe_context *ctx, + const struct pipe_shader_state *state); +void r600_bind_ps_shader(struct pipe_context *ctx, void *state); +void r600_bind_vs_shader(struct pipe_context *ctx, void *state); +void r600_delete_ps_shader(struct pipe_context *ctx, void *state); +void r600_delete_vs_shader(struct pipe_context *ctx, void *state); +void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, + struct pipe_resource *buffer); +struct pipe_stream_output_target * +r600_create_so_target(struct pipe_context *ctx, + struct pipe_resource *buffer, + unsigned buffer_offset, + unsigned buffer_size); +void r600_so_target_destroy(struct pipe_context *ctx, + struct pipe_stream_output_target *target); +void r600_set_so_targets(struct pipe_context *ctx, + unsigned num_targets, + struct pipe_stream_output_target **targets, + unsigned append_bitmask); +void r600_set_pipe_stencil_ref(struct pipe_context *ctx, + const struct pipe_stencil_ref *state); +void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); + +/* + * common helpers + */ +static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) +{ + return value * (1 << frac_bits); +} +#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) + +static inline unsigned r600_tex_aniso_filter(unsigned filter) +{ + if (filter <= 1) return 0; + if (filter <= 2) return 1; + if (filter <= 4) return 2; + if (filter <= 8) return 3; + /* else */ return 4; +} + +/* 12.4 fixed-point */ +static INLINE unsigned r600_pack_float_12p4(float x) +{ + return x <= 0 ? 0 : + x >= 4096 ? 0xffff : x * 16; +} + +static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct r600_resource *rresource = (struct r600_resource*)resource; + + return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); +} + +#endif diff --git a/src/gallium/drivers/radeonsi/radeonsi_public.h b/src/gallium/drivers/radeonsi/radeonsi_public.h new file mode 100644 index 00000000000..5dcec0fc93b --- /dev/null +++ b/src/gallium/drivers/radeonsi/radeonsi_public.h @@ -0,0 +1,30 @@ +/* + * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef RADEONSI_PUBLIC_H +#define RADEONSI_PUBLIC_H + +struct radeon_winsys; + +struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws); + +#endif diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c new file mode 100644 index 00000000000..50f2e39314f --- /dev/null +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -0,0 +1,565 @@ + +#include "gallivm/lp_bld_tgsi_action.h" +#include "gallivm/lp_bld_const.h" +#include "gallivm/lp_bld_intr.h" +#include "gallivm/lp_bld_tgsi.h" +#include "radeon_llvm.h" +#include "tgsi/tgsi_info.h" +#include "tgsi/tgsi_parse.h" +#include "tgsi/tgsi_scan.h" +#include "tgsi/tgsi_dump.h" + +#include "radeonsi_pipe.h" +#include "radeonsi_shader.h" +#include "sid.h" + +#include <assert.h> +#include <errno.h> +#include <stdio.h> + +/* +static ps_remap_inputs( + struct tgsi_llvm_context * tl_ctx, + unsigned tgsi_index, + unsigned tgsi_chan) +{ + : +} + +struct si_input +{ + struct list_head head; + unsigned tgsi_index; + unsigned tgsi_chan; + unsigned order; +}; +*/ + + +struct si_shader_context +{ + struct radeon_llvm_context radeon_bld; + struct r600_context *rctx; + struct tgsi_parse_context parse; + struct tgsi_token * tokens; + struct si_pipe_shader *shader; + unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */ +/* unsigned num_inputs; */ +/* struct list_head inputs; */ +/* unsigned * input_mappings *//* From TGSI to SI hw */ +/* struct tgsi_shader_info info;*/ +}; + +static struct si_shader_context * si_shader_context( + struct lp_build_tgsi_context * bld_base) +{ + return (struct si_shader_context *)bld_base; +} + + +#define PERSPECTIVE_BASE 0 +#define LINEAR_BASE 9 + +#define SAMPLE_OFFSET 0 +#define CENTER_OFFSET 2 +#define CENTROID_OFSET 4 + +#define USE_SGPR_MAX_SUFFIX_LEN 5 + +enum sgpr_type { + SGPR_I32, + SGPR_I64, + SGPR_PTR_V4I32, + SGPR_PTR_V8I32 +}; + +static LLVMValueRef use_sgpr( + struct gallivm_state * gallivm, + enum sgpr_type type, + unsigned sgpr) +{ + LLVMValueRef sgpr_index; + LLVMValueRef sgpr_value; + LLVMTypeRef ret_type; + + sgpr_index = lp_build_const_int32(gallivm, sgpr); + + if (type == SGPR_I32) { + ret_type = LLVMInt32TypeInContext(gallivm->context); + return lp_build_intrinsic_unary(gallivm->builder, + "llvm.SI.use.sgpr.i32", + ret_type, sgpr_index); + } + + ret_type = LLVMInt64TypeInContext(gallivm->context); + sgpr_value = lp_build_intrinsic_unary(gallivm->builder, + "llvm.SI.use.sgpr.i64", + ret_type, sgpr_index); + + switch (type) { + case SGPR_I64: + return sgpr_value; + case SGPR_PTR_V4I32: + ret_type = LLVMInt32TypeInContext(gallivm->context); + ret_type = LLVMVectorType(ret_type, 4); + ret_type = LLVMPointerType(ret_type, + 0 /*XXX: Specify address space*/); + return LLVMBuildIntToPtr(gallivm->builder, sgpr_value, + ret_type, ""); + case SGPR_PTR_V8I32: + ret_type = LLVMInt32TypeInContext(gallivm->context); + ret_type = LLVMVectorType(ret_type, 8); + ret_type = LLVMPointerType(ret_type, + 0 /*XXX: Specify address space*/); + return LLVMBuildIntToPtr(gallivm->builder, sgpr_value, + ret_type, ""); + default: + assert(!"Unsupported SGPR type in use_sgpr()"); + return NULL; + } +} + +static void declare_input_vs( + struct si_shader_context * si_shader_ctx, + unsigned input_index, + const struct tgsi_full_declaration *decl) +{ + LLVMValueRef t_list_ptr; + LLVMValueRef t_offset; + LLVMValueRef attribute_offset; + LLVMValueRef buffer_index_reg; + LLVMValueRef args[4]; + LLVMTypeRef vec4_type; + LLVMValueRef input; + struct lp_build_context * uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base; + struct r600_context *rctx = si_shader_ctx->rctx; + struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index]; + unsigned chan; + + /* XXX: Communicate with the rest of the driver about which SGPR the T# + * list pointer is going to be stored in. Hard code to SGPR[0-1] for + * now */ + t_list_ptr = use_sgpr(base->gallivm, SGPR_I64, 0); + + t_offset = lp_build_const_int32(base->gallivm, + 4 * velem->vertex_buffer_index); + attribute_offset = lp_build_const_int32(base->gallivm, velem->src_offset); + + /* Load the buffer index is always, which is always stored in VGPR0 + * for Vertex Shaders */ + buffer_index_reg = lp_build_intrinsic(base->gallivm->builder, + "llvm.SI.vs.load.buffer.index", uint->elem_type, NULL, 0); + + vec4_type = LLVMVectorType(base->elem_type, 4); + args[0] = t_list_ptr; + args[1] = t_offset; + args[2] = attribute_offset; + args[3] = buffer_index_reg; + input = lp_build_intrinsic(base->gallivm->builder, + "llvm.SI.vs.load.input", vec4_type, args, 4); + + /* Break up the vec4 into individual components */ + for (chan = 0; chan < 4; chan++) { + LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan); + /* XXX: Use a helper function for this. There is one in + * tgsi_llvm.c. */ + si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] = + LLVMBuildExtractElement(base->gallivm->builder, + input, llvm_chan, ""); + } +} + +static void declare_input_fs( + struct si_shader_context * si_shader_ctx, + unsigned input_index, + const struct tgsi_full_declaration *decl) +{ + const char * intr_name; + unsigned chan; + struct lp_build_context * base = + &si_shader_ctx->radeon_bld.soa.bld_base.base; + struct gallivm_state * gallivm = base->gallivm; + + /* This value is: + * [15:0] NewPrimMask (Bit mask for each quad. It is set it the + * quad begins a new primitive. Bit 0 always needs + * to be unset) + * [32:16] ParamOffset + * + */ + LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, 6); + + + /* XXX: Is this the input_index? */ + LLVMValueRef attr_number = lp_build_const_int32(gallivm, input_index); + + /* XXX: Handle all possible interpolation modes */ + switch (decl->Declaration.Interpolate) { + case TGSI_INTERPOLATE_COLOR: + if (si_shader_ctx->rctx->rasterizer->flatshade) + intr_name = "llvm.SI.fs.interp.constant"; + else + intr_name = "llvm.SI.fs.interp.linear.center"; + break; + case TGSI_INTERPOLATE_CONSTANT: + intr_name = "llvm.SI.fs.interp.constant"; + break; + case TGSI_INTERPOLATE_LINEAR: + intr_name = "llvm.SI.fs.interp.linear.center"; + break; + default: + fprintf(stderr, "Warning: Unhandled interpolation mode.\n"); + return; + } + + /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */ + for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { + LLVMValueRef args[3]; + LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan); + unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan); + LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context); + args[0] = llvm_chan; + args[1] = attr_number; + args[2] = params; + si_shader_ctx->radeon_bld.inputs[soa_index] = + lp_build_intrinsic(gallivm->builder, intr_name, + input_type, args, 3); + } +} + +static void declare_input( + struct radeon_llvm_context * radeon_bld, + unsigned input_index, + const struct tgsi_full_declaration *decl) +{ + struct si_shader_context * si_shader_ctx = + si_shader_context(&radeon_bld->soa.bld_base); + if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) { + declare_input_vs(si_shader_ctx, input_index, decl); + } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) { + declare_input_fs(si_shader_ctx, input_index, decl); + } else { + fprintf(stderr, "Warning: Unsupported shader type,\n"); + } +} + +static LLVMValueRef fetch_constant( + struct lp_build_tgsi_context * bld_base, + const struct tgsi_full_src_register *reg, + enum tgsi_opcode_type type, + unsigned swizzle) +{ + struct lp_build_context * base = &bld_base->base; + + LLVMValueRef const_ptr; + LLVMValueRef offset; + + /* XXX: Assume the pointer to the constant buffer is being stored in + * SGPR[2:3] */ + const_ptr = use_sgpr(base->gallivm, SGPR_I64, 1); + + /* XXX: This assumes that the constant buffer is not packed, so + * CONST[0].x will have an offset of 0 and CONST[1].x will have an + * offset of 4. */ + offset = lp_build_const_int32(base->gallivm, + (reg->Register.Index * 4) + swizzle); + + return lp_build_intrinsic_binary(base->gallivm->builder, + "llvm.SI.load.const", base->elem_type, const_ptr, offset); +} + + +/* Declare some intrinsics with the correct attributes */ +static void si_llvm_emit_prologue(struct lp_build_tgsi_context * bld_base) +{ + LLVMValueRef function; + struct gallivm_state * gallivm = bld_base->base.gallivm; + + LLVMTypeRef i64 = LLVMInt64TypeInContext(gallivm->context); + LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); + + /* declare i32 @llvm.SI.use.sgpr.i32(i32) */ + function = lp_declare_intrinsic(gallivm->module, "llvm.SI.use.sgpr.i32", + i32, &i32, 1); + LLVMAddFunctionAttr(function, LLVMReadNoneAttribute); + + /* declare i64 @llvm.SI.use.sgpr.i64(i32) */ + function = lp_declare_intrinsic(gallivm->module, "llvm.SI.use.sgpr.i64", + i64, &i32, 1); + LLVMAddFunctionAttr(function, LLVMReadNoneAttribute); +} + +/* XXX: This is partially implemented for VS only at this point. It is not complete */ +static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base) +{ + struct si_shader_context * si_shader_ctx = si_shader_context(bld_base); + struct r600_shader * shader = &si_shader_ctx->shader->shader; + struct lp_build_context * base = &bld_base->base; + struct lp_build_context * uint = + &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct tgsi_parse_context *parse = &si_shader_ctx->parse; + LLVMValueRef last_args[9] = { 0 }; + + while (!tgsi_parse_end_of_tokens(parse)) { + /* XXX: component_bits controls which components of the output + * registers actually get exported. (e.g bit 0 means export + * X component, bit 1 means export Y component, etc.) I'm + * hard coding this to 0xf for now. In the future, we might + * want to do something else. */ + unsigned component_bits = 0xf; + unsigned chan; + struct tgsi_full_declaration *d = + &parse->FullToken.FullDeclaration; + LLVMValueRef args[9]; + unsigned target; + unsigned index; + unsigned color_count = 0; + unsigned param_count = 0; + int i; + + tgsi_parse_token(parse); + if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION) + continue; + + switch (d->Declaration.File) { + case TGSI_FILE_INPUT: + i = shader->ninput++; + shader->input[i].name = d->Semantic.Name; + shader->input[i].sid = d->Semantic.Index; + shader->input[i].interpolate = d->Declaration.Interpolate; + shader->input[i].centroid = d->Declaration.Centroid; + break; + case TGSI_FILE_OUTPUT: + i = shader->noutput++; + shader->output[i].name = d->Semantic.Name; + shader->output[i].sid = d->Semantic.Index; + shader->output[i].interpolate = d->Declaration.Interpolate; + break; + } + + if (d->Declaration.File != TGSI_FILE_OUTPUT) + continue; + + for (index = d->Range.First; index <= d->Range.Last; index++) { + for (chan = 0; chan < 4; chan++ ) { + LLVMValueRef out_ptr = + si_shader_ctx->radeon_bld.soa.outputs + [index][chan]; + /* +5 because the first output value will be + * the 6th argument to the intrinsic. */ + args[chan + 5]= LLVMBuildLoad( + base->gallivm->builder, out_ptr, ""); + } + + /* XXX: We probably need to keep track of the output + * values, so we know what we are passing to the next + * stage. */ + + /* Select the correct target */ + switch(d->Semantic.Name) { + case TGSI_SEMANTIC_POSITION: + target = V_008DFC_SQ_EXP_POS; + break; + case TGSI_SEMANTIC_COLOR: + if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) { + target = V_008DFC_SQ_EXP_PARAM + param_count; + param_count++; + } else { + target = V_008DFC_SQ_EXP_MRT + color_count; + color_count++; + } + break; + case TGSI_SEMANTIC_GENERIC: + target = V_008DFC_SQ_EXP_PARAM + param_count; + param_count++; + break; + default: + target = 0; + fprintf(stderr, + "Warning: SI unhandled output type:%d\n", + d->Semantic.Name); + } + + /* Specify which components to enable */ + args[0] = lp_build_const_int32(base->gallivm, + component_bits); + + /* Specify whether the EXEC mask represents the valid mask */ + args[1] = lp_build_const_int32(base->gallivm, 0); + + /* Specify whether this is the last export */ + args[2] = lp_build_const_int32(base->gallivm, 0); + + /* Specify the target we are exporting */ + args[3] = lp_build_const_int32(base->gallivm, target); + + /* Set COMPR flag to zero to export data as 32-bit */ + args[4] = uint->zero; + + if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ? + (d->Semantic.Name == TGSI_SEMANTIC_POSITION) : + (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) { + if (last_args[0]) { + lp_build_intrinsic(base->gallivm->builder, + "llvm.SI.export", + LLVMVoidTypeInContext(base->gallivm->context), + last_args, 9); + } + + memcpy(last_args, args, sizeof(args)); + } else { + lp_build_intrinsic(base->gallivm->builder, + "llvm.SI.export", + LLVMVoidTypeInContext(base->gallivm->context), + args, 9); + } + + } + } + + /* Specify whether the EXEC mask represents the valid mask */ + last_args[1] = lp_build_const_int32(base->gallivm, + si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT); + + /* Specify that this is the last export */ + last_args[2] = lp_build_const_int32(base->gallivm, 1); + + lp_build_intrinsic(base->gallivm->builder, + "llvm.SI.export", + LLVMVoidTypeInContext(base->gallivm->context), + last_args, 9); + +/* XXX: Look up what this function does */ +/* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/ +} + +static void tex_fetch_args( + struct lp_build_tgsi_context * bld_base, + struct lp_build_emit_data * emit_data) +{ + /* WriteMask */ + emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, + emit_data->inst->Dst[0].Register.WriteMask); + + /* Coordinates */ + /* XXX: Not all sample instructions need 4 address arguments. */ + emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst, + 0, LP_CHAN_ALL); + + /* Resource */ + emit_data->args[2] = use_sgpr(bld_base->base.gallivm, SGPR_I64, 2); + emit_data->args[3] = lp_build_const_int32(bld_base->base.gallivm, + 32 * emit_data->inst->Src[2].Register.Index); + + /* Sampler */ + emit_data->args[4] = use_sgpr(bld_base->base.gallivm, SGPR_I64, 1); + emit_data->args[5] = lp_build_const_int32(bld_base->base.gallivm, + 16 * emit_data->inst->Src[2].Register.Index); + + /* Dimensions */ + /* XXX: We might want to pass this information to the shader at some. */ +/* emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, + emit_data->inst->Texture.Texture); +*/ + + emit_data->arg_count = 6; + /* XXX: To optimize, we could use a float or v2f32, if the last bits of + * the writemask are clear */ + emit_data->dst_type = LLVMVectorType( + LLVMFloatTypeInContext(bld_base->base.gallivm->context), + 4); +} + +static const struct lp_build_tgsi_action tex_action = { + .fetch_args = tex_fetch_args, + .emit = lp_build_tgsi_intrinsic, + .intr_name = "llvm.SI.sample" +}; + + +int si_pipe_shader_create( + struct pipe_context *ctx, + struct si_pipe_shader *shader) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + struct si_shader_context si_shader_ctx; + struct tgsi_shader_info shader_info; + struct lp_build_tgsi_context * bld_base; + LLVMModuleRef mod; + unsigned char * inst_bytes; + unsigned inst_byte_count; + unsigned i; + + radeon_llvm_context_init(&si_shader_ctx.radeon_bld); + bld_base = &si_shader_ctx.radeon_bld.soa.bld_base; + + tgsi_scan_shader(shader->tokens, &shader_info); + bld_base->info = &shader_info; + bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant; + bld_base->emit_prologue = si_llvm_emit_prologue; + bld_base->emit_epilogue = si_llvm_emit_epilogue; + + bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action; + + si_shader_ctx.radeon_bld.load_input = declare_input; + si_shader_ctx.tokens = shader->tokens; + tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens); + si_shader_ctx.shader = shader; + si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor; + si_shader_ctx.rctx = rctx; + + shader->shader.nr_cbufs = rctx->nr_cbufs; + + lp_build_tgsi_llvm(bld_base, shader->tokens); + + radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld); + + mod = bld_base->base.gallivm->module; + tgsi_dump(shader->tokens, 0); + LLVMDumpModule(mod); + radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", 1 /* dump */); + fprintf(stderr, "SI CODE:\n"); + for (i = 0; i < inst_byte_count; i+=4 ) { + fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3], + inst_bytes[i + 2], inst_bytes[i + 1], + inst_bytes[i]); + } + + shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes); + shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4)); + shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8)); + + tgsi_parse_free(&si_shader_ctx.parse); + + /* copy new shader */ + if (shader->bo == NULL) { + uint32_t *ptr; + + shader->bo = (struct r600_resource*) + pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, inst_byte_count); + if (shader->bo == NULL) { + return -ENOMEM; + } + ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->buf, rctx->cs, PIPE_TRANSFER_WRITE); + if (0 /*R600_BIG_ENDIAN*/) { + for (i = 0; i < (inst_byte_count-12)/4; ++i) { + ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4)); + } + } else { + memcpy(ptr, inst_bytes + 12, inst_byte_count - 12); + } + rctx->ws->buffer_unmap(shader->bo->buf); + } + + free(inst_bytes); + + return 0; +} + +void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader) +{ + pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL); + + memset(&shader->shader,0,sizeof(struct r600_shader)); +} diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h new file mode 100644 index 00000000000..cd742f57da1 --- /dev/null +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h @@ -0,0 +1,4 @@ + +struct tgsi_token; + +void si_test(struct tgsi_token * token, unsigned type); diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h new file mode 100644 index 00000000000..325445c97e0 --- /dev/null +++ b/src/gallium/drivers/radeonsi/sid.h @@ -0,0 +1,7668 @@ +/* + * Southern Islands Register documentation + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SID_H +#define SID_H + +/* si values */ +#define SI_CONFIG_REG_OFFSET 0x00008000 +#define SI_CONFIG_REG_END 0x0000B000 +#define SI_SH_REG_OFFSET 0x0000B000 +#define SI_SH_REG_END 0x0000C000 +#define SI_CONTEXT_REG_OFFSET 0x00028000 +#define SI_CONTEXT_REG_END 0x00029000 + +#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 +#define EVENT_TYPE_ZPASS_DONE 0x15 +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 +#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f +#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + * 5 - TS events + */ + +#define PREDICATION_OP_CLEAR 0x0 +#define PREDICATION_OP_ZPASS 0x1 +#define PREDICATION_OP_PRIMCOUNT 0x2 + +#define PRED_OP(x) ((x) << 16) + +#define PREDICATION_CONTINUE (1 << 31) + +#define PREDICATION_HINT_WAIT (0 << 12) +#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) + +#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) +#define PREDICATION_DRAW_VISIBLE (1 << 8) + +#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 + +#define PKT3_NOP 0x10 +#define PKT3_SET_PREDICATION 0x20 +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define PKT3_INDEX_TYPE 0x2A +#define PKT3_DRAW_INDEX 0x2B +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A +#define PKT3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_EQUAL 3 +#define PKT3_MEM_WRITE 0x3D +#define PKT3_INDIRECT_BUFFER 0x32 +#define PKT3_SURFACE_SYNC 0x43 +#define PKT3_ME_INITIALIZE 0x44 +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_EVENT_WRITE_EOS 0x48 +#define PKT3_ONE_REG_WRITE 0x57 +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_SH_REG 0x76 + +#define PKT_TYPE_S(x) (((x) & 0x3) << 30) +#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) +#define PKT_TYPE_C 0x3FFFFFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) +#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) +#define PKT_COUNT_C 0xC000FFFF +#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) +#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) +#define PKT0_BASE_INDEX_C 0xFFFF0000 +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) +#define PKT3_IT_OPCODE_C 0xFFFF00FF +#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) +#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate)) + +#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC +#define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) +#define R_0085F0_CP_COHER_CNTL 0x0085F0 +#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) +#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) +#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE +#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) +#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) +#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD +#define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 +#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) +#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) +#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF +#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) +#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) +#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F +#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) +#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) +#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF +#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) +#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) +#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF +#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) +#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) +#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF +#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) +#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) +#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF +#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) +#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) +#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF +#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) +#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) +#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF +#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) +#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) +#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF +#define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) +#define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) +#define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF +#define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) +#define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) +#define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF +#define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) +#define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) +#define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF +#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) +#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) +#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF +#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) +#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) +#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF +#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) +#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) +#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF +#define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) +#define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) +#define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF +#define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) +#define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) +#define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF +#define R_0085F4_CP_COHER_SIZE 0x0085F4 +#define R_0085F8_CP_COHER_BASE 0x0085F8 +#define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0 +#define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0) +#define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF) +#define C_0088B0_PRIM_COUNT 0xFFFFFC00 +#define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4 +#define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5) +#define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1) +#define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF +#define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13) +#define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1) +#define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF +#define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16) +#define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F) +#define C_0088C4_ES_LIMIT 0xFFE0FFFF +#define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8 +#define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC +#define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4 +#define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0) +#define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F) +#define C_0088D4_VERT_REUSE 0xFFFFFFE0 +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_008958_PRIM_TYPE 0xFFFFFFC0 +#define V_008958_DI_PT_NONE 0x00 +#define V_008958_DI_PT_POINTLIST 0x01 +#define V_008958_DI_PT_LINELIST 0x02 +#define V_008958_DI_PT_LINESTRIP 0x03 +#define V_008958_DI_PT_TRILIST 0x04 +#define V_008958_DI_PT_TRIFAN 0x05 +#define V_008958_DI_PT_TRISTRIP 0x06 +#define V_008958_DI_PT_UNUSED_0 0x07 +#define V_008958_DI_PT_UNUSED_1 0x08 +#define V_008958_DI_PT_PATCH 0x09 +#define V_008958_DI_PT_LINELIST_ADJ 0x0A +#define V_008958_DI_PT_LINESTRIP_ADJ 0x0B +#define V_008958_DI_PT_TRILIST_ADJ 0x0C +#define V_008958_DI_PT_TRISTRIP_ADJ 0x0D +#define V_008958_DI_PT_UNUSED_3 0x0E +#define V_008958_DI_PT_UNUSED_4 0x0F +#define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10 +#define V_008958_DI_PT_RECTLIST 0x11 +#define V_008958_DI_PT_LINELOOP 0x12 +#define V_008958_DI_PT_QUADLIST 0x13 +#define V_008958_DI_PT_QUADSTRIP 0x14 +#define V_008958_DI_PT_POLYGON 0x15 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19 +#define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A +#define V_008958_DI_PT_2D_LINE_STRIP 0x1B +#define V_008958_DI_PT_2D_TRI_STRIP 0x1C +#define R_00895C_VGT_INDEX_TYPE 0x00895C +#define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0) +#define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03) +#define C_00895C_INDEX_TYPE 0xFFFFFFFC +#define V_00895C_DI_INDEX_SIZE_16_BIT 0x00 +#define V_00895C_DI_INDEX_SIZE_32_BIT 0x01 +#define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 +#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 +#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 +#define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C +#define R_008970_VGT_NUM_INDICES 0x008970 +#define R_008974_VGT_NUM_INSTANCES 0x008974 +#define R_008988_VGT_TF_RING_SIZE 0x008988 +#define S_008988_SIZE(x) (((x) & 0xFFFF) << 0) +#define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF) +#define C_008988_SIZE 0xFFFF0000 +#define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0 +#define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0) +#define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F) +#define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80 +#define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8 +#define R_008A14_PA_CL_ENHANCE 0x008A14 +#define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0) +#define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1) +#define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE +#define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1) +#define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03) +#define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9 +#define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3) +#define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1) +#define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7 +#define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4) +#define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1) +#define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF +#define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60 +#define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) +#define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) +#define C_008A60_LINE_STIPPLE_VALUE 0xFF000000 +#define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10 +#define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0) +#define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F) +#define C_008B10_CURRENT_PTR 0xFFFFFFF0 +#define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8) +#define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) +#define C_008B10_CURRENT_COUNT 0xFFFF00FF +#define R_008BF0_PA_SC_ENHANCE 0x008BF0 +#define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0) +#define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1) +#define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE +#define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1) +#define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1) +#define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD +#define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2) +#define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1) +#define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB +#define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3) +#define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1) +#define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7 +#define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4) +#define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1) +#define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF +#define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5) +#define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1) +#define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF +#define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6) +#define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03) +#define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F +#define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8) +#define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1) +#define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF +#define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9) +#define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1) +#define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF +#define R_008C08_SQC_CACHES 0x008C08 +#define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0) +#define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1) +#define C_008C08_INST_INVALIDATE 0xFFFFFFFE +#define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1) +#define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) +#define C_008C08_DATA_INVALIDATE 0xFFFFFFFD +#define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C +#define S_008C0C_RET(x) (((x) & 0x7F) << 0) +#define G_008C0C_RET(x) (((x) >> 0) & 0x7F) +#define C_008C0C_RET 0xFFFFFF80 +#define S_008C0C_RUI(x) (((x) & 0x07) << 7) +#define G_008C0C_RUI(x) (((x) >> 7) & 0x07) +#define C_008C0C_RUI 0xFFFFFC7F +#define S_008C0C_RNG(x) (((x) & 0x7FF) << 10) +#define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF) +#define C_008C0C_RNG 0xFFE003FF +#if 0 +#define R_008DFC_SQ_INST 0x008DFC +#define R_008DFC_SQ_VOP1 0x008DFC +#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) +#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) +#define C_008DFC_SRC0 0xFFFFFE00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_OP(x) (((x) & 0xFF) << 9) +#define G_008DFC_OP(x) (((x) >> 9) & 0xFF) +#define C_008DFC_OP 0xFFFE01FF +#define V_008DFC_SQ_V_NOP 0x00 +#define V_008DFC_SQ_V_MOV_B32 0x01 +#define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02 +#define V_008DFC_SQ_V_CVT_I32_F64 0x03 +#define V_008DFC_SQ_V_CVT_F64_I32 0x04 +#define V_008DFC_SQ_V_CVT_F32_I32 0x05 +#define V_008DFC_SQ_V_CVT_F32_U32 0x06 +#define V_008DFC_SQ_V_CVT_U32_F32 0x07 +#define V_008DFC_SQ_V_CVT_I32_F32 0x08 +#define V_008DFC_SQ_V_MOV_FED_B32 0x09 +#define V_008DFC_SQ_V_CVT_F16_F32 0x0A +#define V_008DFC_SQ_V_CVT_F32_F16 0x0B +#define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C +#define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D +#define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E +#define V_008DFC_SQ_V_CVT_F32_F64 0x0F +#define V_008DFC_SQ_V_CVT_F64_F32 0x10 +#define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11 +#define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12 +#define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13 +#define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14 +#define V_008DFC_SQ_V_CVT_U32_F64 0x15 +#define V_008DFC_SQ_V_CVT_F64_U32 0x16 +#define V_008DFC_SQ_V_FRACT_F32 0x20 +#define V_008DFC_SQ_V_TRUNC_F32 0x21 +#define V_008DFC_SQ_V_CEIL_F32 0x22 +#define V_008DFC_SQ_V_RNDNE_F32 0x23 +#define V_008DFC_SQ_V_FLOOR_F32 0x24 +#define V_008DFC_SQ_V_EXP_F32 0x25 +#define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26 +#define V_008DFC_SQ_V_LOG_F32 0x27 +#define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28 +#define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29 +#define V_008DFC_SQ_V_RCP_F32 0x2A +#define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B +#define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C +#define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D +#define V_008DFC_SQ_V_RSQ_F32 0x2E +#define V_008DFC_SQ_V_RCP_F64 0x2F +#define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30 +#define V_008DFC_SQ_V_RSQ_F64 0x31 +#define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32 +#define V_008DFC_SQ_V_SQRT_F32 0x33 +#define V_008DFC_SQ_V_SQRT_F64 0x34 +#define V_008DFC_SQ_V_SIN_F32 0x35 +#define V_008DFC_SQ_V_COS_F32 0x36 +#define V_008DFC_SQ_V_NOT_B32 0x37 +#define V_008DFC_SQ_V_BFREV_B32 0x38 +#define V_008DFC_SQ_V_FFBH_U32 0x39 +#define V_008DFC_SQ_V_FFBL_B32 0x3A +#define V_008DFC_SQ_V_FFBH_I32 0x3B +#define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C +#define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D +#define V_008DFC_SQ_V_FRACT_F64 0x3E +#define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F +#define V_008DFC_SQ_V_FREXP_MANT_F32 0x40 +#define V_008DFC_SQ_V_CLREXCP 0x41 +#define V_008DFC_SQ_V_MOVRELD_B32 0x42 +#define V_008DFC_SQ_V_MOVRELS_B32 0x43 +#define V_008DFC_SQ_V_MOVRELSD_B32 0x44 +#define S_008DFC_VDST(x) (((x) & 0xFF) << 17) +#define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) +#define C_008DFC_VDST 0xFE01FFFF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) +#define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) +#define C_008DFC_ENCODING 0x01FFFFFF +#define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F +#define R_008DFC_SQ_MIMG_1 0x008DFC +#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) +#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VADDR 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) +#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) +#define C_008DFC_VDATA 0xFFFF00FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) +#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) +#define C_008DFC_SRSRC 0xFFE0FFFF +#define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21) +#define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F) +#define C_008DFC_SSAMP 0xFC1FFFFF +#define R_008DFC_SQ_VOP3_1 0x008DFC +#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) +#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) +#define C_008DFC_SRC0 0xFFFFFE00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9) +#define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF) +#define C_008DFC_SRC1 0xFFFC01FF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18) +#define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF) +#define C_008DFC_SRC2 0xF803FFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_OMOD(x) (((x) & 0x03) << 27) +#define G_008DFC_OMOD(x) (((x) >> 27) & 0x03) +#define C_008DFC_OMOD 0xE7FFFFFF +#define V_008DFC_SQ_OMOD_OFF 0x00 +#define V_008DFC_SQ_OMOD_M2 0x01 +#define V_008DFC_SQ_OMOD_M4 0x02 +#define V_008DFC_SQ_OMOD_D2 0x03 +#define S_008DFC_NEG(x) (((x) & 0x07) << 29) +#define G_008DFC_NEG(x) (((x) >> 29) & 0x07) +#define C_008DFC_NEG 0x1FFFFFFF +#define R_008DFC_SQ_MUBUF_1 0x008DFC +#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) +#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VADDR 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) +#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) +#define C_008DFC_VDATA 0xFFFF00FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) +#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) +#define C_008DFC_SRSRC 0xFFE0FFFF +#define S_008DFC_SLC(x) (((x) & 0x1) << 22) +#define G_008DFC_SLC(x) (((x) >> 22) & 0x1) +#define C_008DFC_SLC 0xFFBFFFFF +#define S_008DFC_TFE(x) (((x) & 0x1) << 23) +#define G_008DFC_TFE(x) (((x) >> 23) & 0x1) +#define C_008DFC_TFE 0xFF7FFFFF +#define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) +#define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) +#define C_008DFC_SOFFSET 0x00FFFFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define R_008DFC_SQ_DS_0 0x008DFC +#define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0) +#define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF) +#define C_008DFC_OFFSET0 0xFFFFFF00 +#define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8) +#define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF) +#define C_008DFC_OFFSET1 0xFFFF00FF +#define S_008DFC_GDS(x) (((x) & 0x1) << 17) +#define G_008DFC_GDS(x) (((x) >> 17) & 0x1) +#define C_008DFC_GDS 0xFFFDFFFF +#define S_008DFC_OP(x) (((x) & 0xFF) << 18) +#define G_008DFC_OP(x) (((x) >> 18) & 0xFF) +#define C_008DFC_OP 0xFC03FFFF +#define V_008DFC_SQ_DS_ADD_U32 0x00 +#define V_008DFC_SQ_DS_SUB_U32 0x01 +#define V_008DFC_SQ_DS_RSUB_U32 0x02 +#define V_008DFC_SQ_DS_INC_U32 0x03 +#define V_008DFC_SQ_DS_DEC_U32 0x04 +#define V_008DFC_SQ_DS_MIN_I32 0x05 +#define V_008DFC_SQ_DS_MAX_I32 0x06 +#define V_008DFC_SQ_DS_MIN_U32 0x07 +#define V_008DFC_SQ_DS_MAX_U32 0x08 +#define V_008DFC_SQ_DS_AND_B32 0x09 +#define V_008DFC_SQ_DS_OR_B32 0x0A +#define V_008DFC_SQ_DS_XOR_B32 0x0B +#define V_008DFC_SQ_DS_MSKOR_B32 0x0C +#define V_008DFC_SQ_DS_WRITE_B32 0x0D +#define V_008DFC_SQ_DS_WRITE2_B32 0x0E +#define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F +#define V_008DFC_SQ_DS_CMPST_B32 0x10 +#define V_008DFC_SQ_DS_CMPST_F32 0x11 +#define V_008DFC_SQ_DS_MIN_F32 0x12 +#define V_008DFC_SQ_DS_MAX_F32 0x13 +#define V_008DFC_SQ_DS_GWS_INIT 0x19 +#define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A +#define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B +#define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C +#define V_008DFC_SQ_DS_GWS_BARRIER 0x1D +#define V_008DFC_SQ_DS_WRITE_B8 0x1E +#define V_008DFC_SQ_DS_WRITE_B16 0x1F +#define V_008DFC_SQ_DS_ADD_RTN_U32 0x20 +#define V_008DFC_SQ_DS_SUB_RTN_U32 0x21 +#define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22 +#define V_008DFC_SQ_DS_INC_RTN_U32 0x23 +#define V_008DFC_SQ_DS_DEC_RTN_U32 0x24 +#define V_008DFC_SQ_DS_MIN_RTN_I32 0x25 +#define V_008DFC_SQ_DS_MAX_RTN_I32 0x26 +#define V_008DFC_SQ_DS_MIN_RTN_U32 0x27 +#define V_008DFC_SQ_DS_MAX_RTN_U32 0x28 +#define V_008DFC_SQ_DS_AND_RTN_B32 0x29 +#define V_008DFC_SQ_DS_OR_RTN_B32 0x2A +#define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B +#define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C +#define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D +#define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E +#define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F +#define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30 +#define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31 +#define V_008DFC_SQ_DS_MIN_RTN_F32 0x32 +#define V_008DFC_SQ_DS_MAX_RTN_F32 0x33 +#define V_008DFC_SQ_DS_SWIZZLE_B32 0x35 +#define V_008DFC_SQ_DS_READ_B32 0x36 +#define V_008DFC_SQ_DS_READ2_B32 0x37 +#define V_008DFC_SQ_DS_READ2ST64_B32 0x38 +#define V_008DFC_SQ_DS_READ_I8 0x39 +#define V_008DFC_SQ_DS_READ_U8 0x3A +#define V_008DFC_SQ_DS_READ_I16 0x3B +#define V_008DFC_SQ_DS_READ_U16 0x3C +#define V_008DFC_SQ_DS_CONSUME 0x3D +#define V_008DFC_SQ_DS_APPEND 0x3E +#define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F +#define V_008DFC_SQ_DS_ADD_U64 0x40 +#define V_008DFC_SQ_DS_SUB_U64 0x41 +#define V_008DFC_SQ_DS_RSUB_U64 0x42 +#define V_008DFC_SQ_DS_INC_U64 0x43 +#define V_008DFC_SQ_DS_DEC_U64 0x44 +#define V_008DFC_SQ_DS_MIN_I64 0x45 +#define V_008DFC_SQ_DS_MAX_I64 0x46 +#define V_008DFC_SQ_DS_MIN_U64 0x47 +#define V_008DFC_SQ_DS_MAX_U64 0x48 +#define V_008DFC_SQ_DS_AND_B64 0x49 +#define V_008DFC_SQ_DS_OR_B64 0x4A +#define V_008DFC_SQ_DS_XOR_B64 0x4B +#define V_008DFC_SQ_DS_MSKOR_B64 0x4C +#define V_008DFC_SQ_DS_WRITE_B64 0x4D +#define V_008DFC_SQ_DS_WRITE2_B64 0x4E +#define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F +#define V_008DFC_SQ_DS_CMPST_B64 0x50 +#define V_008DFC_SQ_DS_CMPST_F64 0x51 +#define V_008DFC_SQ_DS_MIN_F64 0x52 +#define V_008DFC_SQ_DS_MAX_F64 0x53 +#define V_008DFC_SQ_DS_ADD_RTN_U64 0x60 +#define V_008DFC_SQ_DS_SUB_RTN_U64 0x61 +#define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62 +#define V_008DFC_SQ_DS_INC_RTN_U64 0x63 +#define V_008DFC_SQ_DS_DEC_RTN_U64 0x64 +#define V_008DFC_SQ_DS_MIN_RTN_I64 0x65 +#define V_008DFC_SQ_DS_MAX_RTN_I64 0x66 +#define V_008DFC_SQ_DS_MIN_RTN_U64 0x67 +#define V_008DFC_SQ_DS_MAX_RTN_U64 0x68 +#define V_008DFC_SQ_DS_AND_RTN_B64 0x69 +#define V_008DFC_SQ_DS_OR_RTN_B64 0x6A +#define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B +#define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C +#define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D +#define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E +#define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F +#define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70 +#define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71 +#define V_008DFC_SQ_DS_MIN_RTN_F64 0x72 +#define V_008DFC_SQ_DS_MAX_RTN_F64 0x73 +#define V_008DFC_SQ_DS_READ_B64 0x76 +#define V_008DFC_SQ_DS_READ2_B64 0x77 +#define V_008DFC_SQ_DS_READ2ST64_B64 0x78 +#define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80 +#define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81 +#define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82 +#define V_008DFC_SQ_DS_INC_SRC2_U32 0x83 +#define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84 +#define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85 +#define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86 +#define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87 +#define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88 +#define V_008DFC_SQ_DS_AND_SRC2_B32 0x89 +#define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A +#define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B +#define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D +#define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92 +#define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93 +#define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0 +#define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1 +#define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2 +#define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3 +#define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4 +#define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5 +#define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6 +#define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7 +#define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8 +#define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9 +#define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA +#define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB +#define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD +#define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2 +#define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3 +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_DS_FIELD 0x36 +#define R_008DFC_SQ_SOPC 0x008DFC +#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) +#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) +#define C_008DFC_SSRC0 0xFFFFFF00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) +#define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) +#define C_008DFC_SSRC1 0xFFFF00FF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define S_008DFC_OP(x) (((x) & 0x7F) << 16) +#define G_008DFC_OP(x) (((x) >> 16) & 0x7F) +#define C_008DFC_OP 0xFF80FFFF +#define V_008DFC_SQ_S_CMP_EQ_I32 0x00 +#define V_008DFC_SQ_S_CMP_LG_I32 0x01 +#define V_008DFC_SQ_S_CMP_GT_I32 0x02 +#define V_008DFC_SQ_S_CMP_GE_I32 0x03 +#define V_008DFC_SQ_S_CMP_LT_I32 0x04 +#define V_008DFC_SQ_S_CMP_LE_I32 0x05 +#define V_008DFC_SQ_S_CMP_EQ_U32 0x06 +#define V_008DFC_SQ_S_CMP_LG_U32 0x07 +#define V_008DFC_SQ_S_CMP_GT_U32 0x08 +#define V_008DFC_SQ_S_CMP_GE_U32 0x09 +#define V_008DFC_SQ_S_CMP_LT_U32 0x0A +#define V_008DFC_SQ_S_CMP_LE_U32 0x0B +#define V_008DFC_SQ_S_BITCMP0_B32 0x0C +#define V_008DFC_SQ_S_BITCMP1_B32 0x0D +#define V_008DFC_SQ_S_BITCMP0_B64 0x0E +#define V_008DFC_SQ_S_BITCMP1_B64 0x0F +#define V_008DFC_SQ_S_SETVSKIP 0x10 +#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) +#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) +#define C_008DFC_ENCODING 0x007FFFFF +#define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E +#endif +#define R_008DFC_SQ_EXP_0 0x008DFC +#define S_008DFC_EN(x) (((x) & 0x0F) << 0) +#define G_008DFC_EN(x) (((x) >> 0) & 0x0F) +#define C_008DFC_EN 0xFFFFFFF0 +#define S_008DFC_TGT(x) (((x) & 0x3F) << 4) +#define G_008DFC_TGT(x) (((x) >> 4) & 0x3F) +#define C_008DFC_TGT 0xFFFFFC0F +#define V_008DFC_SQ_EXP_MRT 0x00 +#define V_008DFC_SQ_EXP_MRTZ 0x08 +#define V_008DFC_SQ_EXP_NULL 0x09 +#define V_008DFC_SQ_EXP_POS 0x0C +#define V_008DFC_SQ_EXP_PARAM 0x20 +#define S_008DFC_COMPR(x) (((x) & 0x1) << 10) +#define G_008DFC_COMPR(x) (((x) >> 10) & 0x1) +#define C_008DFC_COMPR 0xFFFFFBFF +#define S_008DFC_DONE(x) (((x) & 0x1) << 11) +#define G_008DFC_DONE(x) (((x) >> 11) & 0x1) +#define C_008DFC_DONE 0xFFFFF7FF +#define S_008DFC_VM(x) (((x) & 0x1) << 12) +#define G_008DFC_VM(x) (((x) >> 12) & 0x1) +#define C_008DFC_VM 0xFFFFEFFF +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_EXP_FIELD 0x3E +#if 0 +#define R_008DFC_SQ_MIMG_0 0x008DFC +#define S_008DFC_DMASK(x) (((x) & 0x0F) << 8) +#define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F) +#define C_008DFC_DMASK 0xFFFFF0FF +#define S_008DFC_UNORM(x) (((x) & 0x1) << 12) +#define G_008DFC_UNORM(x) (((x) >> 12) & 0x1) +#define C_008DFC_UNORM 0xFFFFEFFF +#define S_008DFC_GLC(x) (((x) & 0x1) << 13) +#define G_008DFC_GLC(x) (((x) >> 13) & 0x1) +#define C_008DFC_GLC 0xFFFFDFFF +#define S_008DFC_DA(x) (((x) & 0x1) << 14) +#define G_008DFC_DA(x) (((x) >> 14) & 0x1) +#define C_008DFC_DA 0xFFFFBFFF +#define S_008DFC_R128(x) (((x) & 0x1) << 15) +#define G_008DFC_R128(x) (((x) >> 15) & 0x1) +#define C_008DFC_R128 0xFFFF7FFF +#define S_008DFC_TFE(x) (((x) & 0x1) << 16) +#define G_008DFC_TFE(x) (((x) >> 16) & 0x1) +#define C_008DFC_TFE 0xFFFEFFFF +#define S_008DFC_LWE(x) (((x) & 0x1) << 17) +#define G_008DFC_LWE(x) (((x) >> 17) & 0x1) +#define C_008DFC_LWE 0xFFFDFFFF +#define S_008DFC_OP(x) (((x) & 0x7F) << 18) +#define G_008DFC_OP(x) (((x) >> 18) & 0x7F) +#define C_008DFC_OP 0xFE03FFFF +#define V_008DFC_SQ_IMAGE_LOAD 0x00 +#define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01 +#define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02 +#define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03 +#define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04 +#define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05 +#define V_008DFC_SQ_IMAGE_STORE 0x08 +#define V_008DFC_SQ_IMAGE_STORE_MIP 0x09 +#define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A +#define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B +#define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E +#define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F +#define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10 +#define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11 +#define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12 +#define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 +#define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14 +#define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15 +#define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16 +#define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17 +#define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18 +#define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19 +#define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A +#define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B +#define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C +#define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D +#define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E +#define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F +#define V_008DFC_SQ_IMAGE_SAMPLE 0x20 +#define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21 +#define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22 +#define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23 +#define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24 +#define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25 +#define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26 +#define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27 +#define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A +#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B +#define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C +#define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D +#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E +#define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F +#define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30 +#define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31 +#define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32 +#define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33 +#define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34 +#define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35 +#define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36 +#define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A +#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B +#define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C +#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D +#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E +#define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F +#define V_008DFC_SQ_IMAGE_GATHER4 0x40 +#define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41 +#define V_008DFC_SQ_IMAGE_GATHER4_L 0x44 +#define V_008DFC_SQ_IMAGE_GATHER4_B 0x45 +#define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46 +#define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47 +#define V_008DFC_SQ_IMAGE_GATHER4_C 0x48 +#define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49 +#define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C +#define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D +#define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E +#define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F +#define V_008DFC_SQ_IMAGE_GATHER4_O 0x50 +#define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51 +#define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54 +#define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55 +#define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56 +#define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57 +#define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58 +#define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59 +#define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C +#define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D +#define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E +#define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F +#define V_008DFC_SQ_IMAGE_GET_LOD 0x60 +#define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68 +#define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69 +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B +#define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C +#define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E +#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F +#define V_008DFC_SQ_IMAGE_RSRC256 0x7E +#define V_008DFC_SQ_IMAGE_SAMPLER 0x7F +#define S_008DFC_SLC(x) (((x) & 0x1) << 25) +#define G_008DFC_SLC(x) (((x) >> 25) & 0x1) +#define C_008DFC_SLC 0xFDFFFFFF +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C +#define R_008DFC_SQ_SOPP 0x008DFC +#define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) +#define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) +#define C_008DFC_SIMM16 0xFFFF0000 +#define S_008DFC_OP(x) (((x) & 0x7F) << 16) +#define G_008DFC_OP(x) (((x) >> 16) & 0x7F) +#define C_008DFC_OP 0xFF80FFFF +#define V_008DFC_SQ_S_NOP 0x00 +#define V_008DFC_SQ_S_ENDPGM 0x01 +#define V_008DFC_SQ_S_BRANCH 0x02 +#define V_008DFC_SQ_S_CBRANCH_SCC0 0x04 +#define V_008DFC_SQ_S_CBRANCH_SCC1 0x05 +#define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06 +#define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07 +#define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08 +#define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09 +#define V_008DFC_SQ_S_BARRIER 0x0A +#define V_008DFC_SQ_S_WAITCNT 0x0C +#define V_008DFC_SQ_S_SETHALT 0x0D +#define V_008DFC_SQ_S_SLEEP 0x0E +#define V_008DFC_SQ_S_SETPRIO 0x0F +#define V_008DFC_SQ_S_SENDMSG 0x10 +#define V_008DFC_SQ_S_SENDMSGHALT 0x11 +#define V_008DFC_SQ_S_TRAP 0x12 +#define V_008DFC_SQ_S_ICACHE_INV 0x13 +#define V_008DFC_SQ_S_INCPERFLEVEL 0x14 +#define V_008DFC_SQ_S_DECPERFLEVEL 0x15 +#define V_008DFC_SQ_S_TTRACEDATA 0x16 +#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) +#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) +#define C_008DFC_ENCODING 0x007FFFFF +#define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F +#define R_008DFC_SQ_VINTRP 0x008DFC +#define S_008DFC_VSRC(x) (((x) & 0xFF) << 0) +#define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VSRC 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8) +#define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03) +#define C_008DFC_ATTRCHAN 0xFFFFFCFF +#define V_008DFC_SQ_CHAN_X 0x00 +#define V_008DFC_SQ_CHAN_Y 0x01 +#define V_008DFC_SQ_CHAN_Z 0x02 +#define V_008DFC_SQ_CHAN_W 0x03 +#define S_008DFC_ATTR(x) (((x) & 0x3F) << 10) +#define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F) +#define C_008DFC_ATTR 0xFFFF03FF +#define V_008DFC_SQ_ATTR 0x00 +#define S_008DFC_OP(x) (((x) & 0x03) << 16) +#define G_008DFC_OP(x) (((x) >> 16) & 0x03) +#define C_008DFC_OP 0xFFFCFFFF +#define V_008DFC_SQ_V_INTERP_P1_F32 0x00 +#define V_008DFC_SQ_V_INTERP_P2_F32 0x01 +#define V_008DFC_SQ_V_INTERP_MOV_F32 0x02 +#define S_008DFC_VDST(x) (((x) & 0xFF) << 18) +#define G_008DFC_VDST(x) (((x) >> 18) & 0xFF) +#define C_008DFC_VDST 0xFC03FFFF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32 +#define R_008DFC_SQ_MTBUF_0 0x008DFC +#define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) +#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) +#define C_008DFC_OFFSET 0xFFFFF000 +#define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) +#define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) +#define C_008DFC_OFFEN 0xFFFFEFFF +#define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) +#define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) +#define C_008DFC_IDXEN 0xFFFFDFFF +#define S_008DFC_GLC(x) (((x) & 0x1) << 14) +#define G_008DFC_GLC(x) (((x) >> 14) & 0x1) +#define C_008DFC_GLC 0xFFFFBFFF +#define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) +#define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) +#define C_008DFC_ADDR64 0xFFFF7FFF +#define S_008DFC_OP(x) (((x) & 0x07) << 16) +#define G_008DFC_OP(x) (((x) >> 16) & 0x07) +#define C_008DFC_OP 0xFFF8FFFF +#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00 +#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01 +#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02 +#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03 +#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04 +#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05 +#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06 +#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07 +#define S_008DFC_DFMT(x) (((x) & 0x0F) << 19) +#define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F) +#define C_008DFC_DFMT 0xFF87FFFF +#define S_008DFC_NFMT(x) (((x) & 0x07) << 23) +#define G_008DFC_NFMT(x) (((x) >> 23) & 0x07) +#define C_008DFC_NFMT 0xFC7FFFFF +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A +#define R_008DFC_SQ_SMRD 0x008DFC +#define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0) +#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF) +#define C_008DFC_OFFSET 0xFFFFFF00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define S_008DFC_IMM(x) (((x) & 0x1) << 8) +#define G_008DFC_IMM(x) (((x) >> 8) & 0x1) +#define C_008DFC_IMM 0xFFFFFEFF +#define S_008DFC_SBASE(x) (((x) & 0x3F) << 9) +#define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F) +#define C_008DFC_SBASE 0xFFFF81FF +#define S_008DFC_SDST(x) (((x) & 0x7F) << 15) +#define G_008DFC_SDST(x) (((x) >> 15) & 0x7F) +#define C_008DFC_SDST 0xFFC07FFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define S_008DFC_OP(x) (((x) & 0x1F) << 22) +#define G_008DFC_OP(x) (((x) >> 22) & 0x1F) +#define C_008DFC_OP 0xF83FFFFF +#define V_008DFC_SQ_S_LOAD_DWORD 0x00 +#define V_008DFC_SQ_S_LOAD_DWORDX2 0x01 +#define V_008DFC_SQ_S_LOAD_DWORDX4 0x02 +#define V_008DFC_SQ_S_LOAD_DWORDX8 0x03 +#define V_008DFC_SQ_S_LOAD_DWORDX16 0x04 +#define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08 +#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09 +#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A +#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B +#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C +#define V_008DFC_SQ_S_MEMTIME 0x1E +#define V_008DFC_SQ_S_DCACHE_INV 0x1F +#define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27) +#define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F) +#define C_008DFC_ENCODING 0x07FFFFFF +#define V_008DFC_SQ_ENC_SMRD_FIELD 0x18 +#define R_008DFC_SQ_EXP_1 0x008DFC +#define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0) +#define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VSRC0 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8) +#define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF) +#define C_008DFC_VSRC1 0xFFFF00FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16) +#define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF) +#define C_008DFC_VSRC2 0xFF00FFFF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24) +#define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF) +#define C_008DFC_VSRC3 0x00FFFFFF +#define V_008DFC_SQ_VGPR 0x00 +#define R_008DFC_SQ_DS_1 0x008DFC +#define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) +#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) +#define C_008DFC_ADDR 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_DATA0(x) (((x) & 0xFF) << 8) +#define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF) +#define C_008DFC_DATA0 0xFFFF00FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_DATA1(x) (((x) & 0xFF) << 16) +#define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF) +#define C_008DFC_DATA1 0xFF00FFFF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VDST(x) (((x) & 0xFF) << 24) +#define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) +#define C_008DFC_VDST 0x00FFFFFF +#define V_008DFC_SQ_VGPR 0x00 +#define R_008DFC_SQ_VOPC 0x008DFC +#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) +#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) +#define C_008DFC_SRC0 0xFFFFFE00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) +#define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) +#define C_008DFC_VSRC1 0xFFFE01FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_OP(x) (((x) & 0xFF) << 17) +#define G_008DFC_OP(x) (((x) >> 17) & 0xFF) +#define C_008DFC_OP 0xFE01FFFF +#define V_008DFC_SQ_V_CMP_F_F32 0x00 +#define V_008DFC_SQ_V_CMP_LT_F32 0x01 +#define V_008DFC_SQ_V_CMP_EQ_F32 0x02 +#define V_008DFC_SQ_V_CMP_LE_F32 0x03 +#define V_008DFC_SQ_V_CMP_GT_F32 0x04 +#define V_008DFC_SQ_V_CMP_LG_F32 0x05 +#define V_008DFC_SQ_V_CMP_GE_F32 0x06 +#define V_008DFC_SQ_V_CMP_O_F32 0x07 +#define V_008DFC_SQ_V_CMP_U_F32 0x08 +#define V_008DFC_SQ_V_CMP_NGE_F32 0x09 +#define V_008DFC_SQ_V_CMP_NLG_F32 0x0A +#define V_008DFC_SQ_V_CMP_NGT_F32 0x0B +#define V_008DFC_SQ_V_CMP_NLE_F32 0x0C +#define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D +#define V_008DFC_SQ_V_CMP_NLT_F32 0x0E +#define V_008DFC_SQ_V_CMP_TRU_F32 0x0F +#define V_008DFC_SQ_V_CMPX_F_F32 0x10 +#define V_008DFC_SQ_V_CMPX_LT_F32 0x11 +#define V_008DFC_SQ_V_CMPX_EQ_F32 0x12 +#define V_008DFC_SQ_V_CMPX_LE_F32 0x13 +#define V_008DFC_SQ_V_CMPX_GT_F32 0x14 +#define V_008DFC_SQ_V_CMPX_LG_F32 0x15 +#define V_008DFC_SQ_V_CMPX_GE_F32 0x16 +#define V_008DFC_SQ_V_CMPX_O_F32 0x17 +#define V_008DFC_SQ_V_CMPX_U_F32 0x18 +#define V_008DFC_SQ_V_CMPX_NGE_F32 0x19 +#define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A +#define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B +#define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C +#define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D +#define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E +#define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F +#define V_008DFC_SQ_V_CMP_F_F64 0x20 +#define V_008DFC_SQ_V_CMP_LT_F64 0x21 +#define V_008DFC_SQ_V_CMP_EQ_F64 0x22 +#define V_008DFC_SQ_V_CMP_LE_F64 0x23 +#define V_008DFC_SQ_V_CMP_GT_F64 0x24 +#define V_008DFC_SQ_V_CMP_LG_F64 0x25 +#define V_008DFC_SQ_V_CMP_GE_F64 0x26 +#define V_008DFC_SQ_V_CMP_O_F64 0x27 +#define V_008DFC_SQ_V_CMP_U_F64 0x28 +#define V_008DFC_SQ_V_CMP_NGE_F64 0x29 +#define V_008DFC_SQ_V_CMP_NLG_F64 0x2A +#define V_008DFC_SQ_V_CMP_NGT_F64 0x2B +#define V_008DFC_SQ_V_CMP_NLE_F64 0x2C +#define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D +#define V_008DFC_SQ_V_CMP_NLT_F64 0x2E +#define V_008DFC_SQ_V_CMP_TRU_F64 0x2F +#define V_008DFC_SQ_V_CMPX_F_F64 0x30 +#define V_008DFC_SQ_V_CMPX_LT_F64 0x31 +#define V_008DFC_SQ_V_CMPX_EQ_F64 0x32 +#define V_008DFC_SQ_V_CMPX_LE_F64 0x33 +#define V_008DFC_SQ_V_CMPX_GT_F64 0x34 +#define V_008DFC_SQ_V_CMPX_LG_F64 0x35 +#define V_008DFC_SQ_V_CMPX_GE_F64 0x36 +#define V_008DFC_SQ_V_CMPX_O_F64 0x37 +#define V_008DFC_SQ_V_CMPX_U_F64 0x38 +#define V_008DFC_SQ_V_CMPX_NGE_F64 0x39 +#define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A +#define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B +#define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C +#define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D +#define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E +#define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F +#define V_008DFC_SQ_V_CMPS_F_F32 0x40 +#define V_008DFC_SQ_V_CMPS_LT_F32 0x41 +#define V_008DFC_SQ_V_CMPS_EQ_F32 0x42 +#define V_008DFC_SQ_V_CMPS_LE_F32 0x43 +#define V_008DFC_SQ_V_CMPS_GT_F32 0x44 +#define V_008DFC_SQ_V_CMPS_LG_F32 0x45 +#define V_008DFC_SQ_V_CMPS_GE_F32 0x46 +#define V_008DFC_SQ_V_CMPS_O_F32 0x47 +#define V_008DFC_SQ_V_CMPS_U_F32 0x48 +#define V_008DFC_SQ_V_CMPS_NGE_F32 0x49 +#define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A +#define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B +#define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C +#define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D +#define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E +#define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F +#define V_008DFC_SQ_V_CMPSX_F_F32 0x50 +#define V_008DFC_SQ_V_CMPSX_LT_F32 0x51 +#define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52 +#define V_008DFC_SQ_V_CMPSX_LE_F32 0x53 +#define V_008DFC_SQ_V_CMPSX_GT_F32 0x54 +#define V_008DFC_SQ_V_CMPSX_LG_F32 0x55 +#define V_008DFC_SQ_V_CMPSX_GE_F32 0x56 +#define V_008DFC_SQ_V_CMPSX_O_F32 0x57 +#define V_008DFC_SQ_V_CMPSX_U_F32 0x58 +#define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59 +#define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A +#define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B +#define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C +#define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D +#define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E +#define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F +#define V_008DFC_SQ_V_CMPS_F_F64 0x60 +#define V_008DFC_SQ_V_CMPS_LT_F64 0x61 +#define V_008DFC_SQ_V_CMPS_EQ_F64 0x62 +#define V_008DFC_SQ_V_CMPS_LE_F64 0x63 +#define V_008DFC_SQ_V_CMPS_GT_F64 0x64 +#define V_008DFC_SQ_V_CMPS_LG_F64 0x65 +#define V_008DFC_SQ_V_CMPS_GE_F64 0x66 +#define V_008DFC_SQ_V_CMPS_O_F64 0x67 +#define V_008DFC_SQ_V_CMPS_U_F64 0x68 +#define V_008DFC_SQ_V_CMPS_NGE_F64 0x69 +#define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A +#define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B +#define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C +#define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D +#define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E +#define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F +#define V_008DFC_SQ_V_CMPSX_F_F64 0x70 +#define V_008DFC_SQ_V_CMPSX_LT_F64 0x71 +#define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72 +#define V_008DFC_SQ_V_CMPSX_LE_F64 0x73 +#define V_008DFC_SQ_V_CMPSX_GT_F64 0x74 +#define V_008DFC_SQ_V_CMPSX_LG_F64 0x75 +#define V_008DFC_SQ_V_CMPSX_GE_F64 0x76 +#define V_008DFC_SQ_V_CMPSX_O_F64 0x77 +#define V_008DFC_SQ_V_CMPSX_U_F64 0x78 +#define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79 +#define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A +#define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B +#define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C +#define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D +#define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E +#define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F +#define V_008DFC_SQ_V_CMP_F_I32 0x80 +#define V_008DFC_SQ_V_CMP_LT_I32 0x81 +#define V_008DFC_SQ_V_CMP_EQ_I32 0x82 +#define V_008DFC_SQ_V_CMP_LE_I32 0x83 +#define V_008DFC_SQ_V_CMP_GT_I32 0x84 +#define V_008DFC_SQ_V_CMP_NE_I32 0x85 +#define V_008DFC_SQ_V_CMP_GE_I32 0x86 +#define V_008DFC_SQ_V_CMP_T_I32 0x87 +#define V_008DFC_SQ_V_CMP_CLASS_F32 0x88 +#define V_008DFC_SQ_V_CMPX_F_I32 0x90 +#define V_008DFC_SQ_V_CMPX_LT_I32 0x91 +#define V_008DFC_SQ_V_CMPX_EQ_I32 0x92 +#define V_008DFC_SQ_V_CMPX_LE_I32 0x93 +#define V_008DFC_SQ_V_CMPX_GT_I32 0x94 +#define V_008DFC_SQ_V_CMPX_NE_I32 0x95 +#define V_008DFC_SQ_V_CMPX_GE_I32 0x96 +#define V_008DFC_SQ_V_CMPX_T_I32 0x97 +#define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98 +#define V_008DFC_SQ_V_CMP_F_I64 0xA0 +#define V_008DFC_SQ_V_CMP_LT_I64 0xA1 +#define V_008DFC_SQ_V_CMP_EQ_I64 0xA2 +#define V_008DFC_SQ_V_CMP_LE_I64 0xA3 +#define V_008DFC_SQ_V_CMP_GT_I64 0xA4 +#define V_008DFC_SQ_V_CMP_NE_I64 0xA5 +#define V_008DFC_SQ_V_CMP_GE_I64 0xA6 +#define V_008DFC_SQ_V_CMP_T_I64 0xA7 +#define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8 +#define V_008DFC_SQ_V_CMPX_F_I64 0xB0 +#define V_008DFC_SQ_V_CMPX_LT_I64 0xB1 +#define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2 +#define V_008DFC_SQ_V_CMPX_LE_I64 0xB3 +#define V_008DFC_SQ_V_CMPX_GT_I64 0xB4 +#define V_008DFC_SQ_V_CMPX_NE_I64 0xB5 +#define V_008DFC_SQ_V_CMPX_GE_I64 0xB6 +#define V_008DFC_SQ_V_CMPX_T_I64 0xB7 +#define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8 +#define V_008DFC_SQ_V_CMP_F_U32 0xC0 +#define V_008DFC_SQ_V_CMP_LT_U32 0xC1 +#define V_008DFC_SQ_V_CMP_EQ_U32 0xC2 +#define V_008DFC_SQ_V_CMP_LE_U32 0xC3 +#define V_008DFC_SQ_V_CMP_GT_U32 0xC4 +#define V_008DFC_SQ_V_CMP_NE_U32 0xC5 +#define V_008DFC_SQ_V_CMP_GE_U32 0xC6 +#define V_008DFC_SQ_V_CMP_T_U32 0xC7 +#define V_008DFC_SQ_V_CMPX_F_U32 0xD0 +#define V_008DFC_SQ_V_CMPX_LT_U32 0xD1 +#define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2 +#define V_008DFC_SQ_V_CMPX_LE_U32 0xD3 +#define V_008DFC_SQ_V_CMPX_GT_U32 0xD4 +#define V_008DFC_SQ_V_CMPX_NE_U32 0xD5 +#define V_008DFC_SQ_V_CMPX_GE_U32 0xD6 +#define V_008DFC_SQ_V_CMPX_T_U32 0xD7 +#define V_008DFC_SQ_V_CMP_F_U64 0xE0 +#define V_008DFC_SQ_V_CMP_LT_U64 0xE1 +#define V_008DFC_SQ_V_CMP_EQ_U64 0xE2 +#define V_008DFC_SQ_V_CMP_LE_U64 0xE3 +#define V_008DFC_SQ_V_CMP_GT_U64 0xE4 +#define V_008DFC_SQ_V_CMP_NE_U64 0xE5 +#define V_008DFC_SQ_V_CMP_GE_U64 0xE6 +#define V_008DFC_SQ_V_CMP_T_U64 0xE7 +#define V_008DFC_SQ_V_CMPX_F_U64 0xF0 +#define V_008DFC_SQ_V_CMPX_LT_U64 0xF1 +#define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2 +#define V_008DFC_SQ_V_CMPX_LE_U64 0xF3 +#define V_008DFC_SQ_V_CMPX_GT_U64 0xF4 +#define V_008DFC_SQ_V_CMPX_NE_U64 0xF5 +#define V_008DFC_SQ_V_CMPX_GE_U64 0xF6 +#define V_008DFC_SQ_V_CMPX_T_U64 0xF7 +#define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) +#define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) +#define C_008DFC_ENCODING 0x01FFFFFF +#define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E +#define R_008DFC_SQ_SOP1 0x008DFC +#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) +#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) +#define C_008DFC_SSRC0 0xFFFFFF00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define S_008DFC_OP(x) (((x) & 0xFF) << 8) +#define G_008DFC_OP(x) (((x) >> 8) & 0xFF) +#define C_008DFC_OP 0xFFFF00FF +#define V_008DFC_SQ_S_MOV_B32 0x03 +#define V_008DFC_SQ_S_MOV_B64 0x04 +#define V_008DFC_SQ_S_CMOV_B32 0x05 +#define V_008DFC_SQ_S_CMOV_B64 0x06 +#define V_008DFC_SQ_S_NOT_B32 0x07 +#define V_008DFC_SQ_S_NOT_B64 0x08 +#define V_008DFC_SQ_S_WQM_B32 0x09 +#define V_008DFC_SQ_S_WQM_B64 0x0A +#define V_008DFC_SQ_S_BREV_B32 0x0B +#define V_008DFC_SQ_S_BREV_B64 0x0C +#define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D +#define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E +#define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F +#define V_008DFC_SQ_S_BCNT1_I32_B64 0x10 +#define V_008DFC_SQ_S_FF0_I32_B32 0x11 +#define V_008DFC_SQ_S_FF0_I32_B64 0x12 +#define V_008DFC_SQ_S_FF1_I32_B32 0x13 +#define V_008DFC_SQ_S_FF1_I32_B64 0x14 +#define V_008DFC_SQ_S_FLBIT_I32_B32 0x15 +#define V_008DFC_SQ_S_FLBIT_I32_B64 0x16 +#define V_008DFC_SQ_S_FLBIT_I32 0x17 +#define V_008DFC_SQ_S_FLBIT_I32_I64 0x18 +#define V_008DFC_SQ_S_SEXT_I32_I8 0x19 +#define V_008DFC_SQ_S_SEXT_I32_I16 0x1A +#define V_008DFC_SQ_S_BITSET0_B32 0x1B +#define V_008DFC_SQ_S_BITSET0_B64 0x1C +#define V_008DFC_SQ_S_BITSET1_B32 0x1D +#define V_008DFC_SQ_S_BITSET1_B64 0x1E +#define V_008DFC_SQ_S_GETPC_B64 0x1F +#define V_008DFC_SQ_S_SETPC_B64 0x20 +#define V_008DFC_SQ_S_SWAPPC_B64 0x21 +#define V_008DFC_SQ_S_RFE_B64 0x22 +#define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24 +#define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25 +#define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26 +#define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27 +#define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28 +#define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29 +#define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A +#define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B +#define V_008DFC_SQ_S_QUADMASK_B32 0x2C +#define V_008DFC_SQ_S_QUADMASK_B64 0x2D +#define V_008DFC_SQ_S_MOVRELS_B32 0x2E +#define V_008DFC_SQ_S_MOVRELS_B64 0x2F +#define V_008DFC_SQ_S_MOVRELD_B32 0x30 +#define V_008DFC_SQ_S_MOVRELD_B64 0x31 +#define V_008DFC_SQ_S_CBRANCH_JOIN 0x32 +#define V_008DFC_SQ_S_MOV_REGRD_B32 0x33 +#define V_008DFC_SQ_S_ABS_I32 0x34 +#define V_008DFC_SQ_S_MOV_FED_B32 0x35 +#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) +#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) +#define C_008DFC_SDST 0xFF80FFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) +#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) +#define C_008DFC_ENCODING 0x007FFFFF +#define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D +#define R_008DFC_SQ_MTBUF_1 0x008DFC +#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) +#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VADDR 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) +#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) +#define C_008DFC_VDATA 0xFFFF00FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) +#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) +#define C_008DFC_SRSRC 0xFFE0FFFF +#define S_008DFC_SLC(x) (((x) & 0x1) << 22) +#define G_008DFC_SLC(x) (((x) >> 22) & 0x1) +#define C_008DFC_SLC 0xFFBFFFFF +#define S_008DFC_TFE(x) (((x) & 0x1) << 23) +#define G_008DFC_TFE(x) (((x) >> 23) & 0x1) +#define C_008DFC_TFE 0xFF7FFFFF +#define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) +#define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) +#define C_008DFC_SOFFSET 0x00FFFFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define R_008DFC_SQ_SOP2 0x008DFC +#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) +#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) +#define C_008DFC_SSRC0 0xFFFFFF00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) +#define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) +#define C_008DFC_SSRC1 0xFFFF00FF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) +#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) +#define C_008DFC_SDST 0xFF80FFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define S_008DFC_OP(x) (((x) & 0x7F) << 23) +#define G_008DFC_OP(x) (((x) >> 23) & 0x7F) +#define C_008DFC_OP 0xC07FFFFF +#define V_008DFC_SQ_S_ADD_U32 0x00 +#define V_008DFC_SQ_S_SUB_U32 0x01 +#define V_008DFC_SQ_S_ADD_I32 0x02 +#define V_008DFC_SQ_S_SUB_I32 0x03 +#define V_008DFC_SQ_S_ADDC_U32 0x04 +#define V_008DFC_SQ_S_SUBB_U32 0x05 +#define V_008DFC_SQ_S_MIN_I32 0x06 +#define V_008DFC_SQ_S_MIN_U32 0x07 +#define V_008DFC_SQ_S_MAX_I32 0x08 +#define V_008DFC_SQ_S_MAX_U32 0x09 +#define V_008DFC_SQ_S_CSELECT_B32 0x0A +#define V_008DFC_SQ_S_CSELECT_B64 0x0B +#define V_008DFC_SQ_S_AND_B32 0x0E +#define V_008DFC_SQ_S_AND_B64 0x0F +#define V_008DFC_SQ_S_OR_B32 0x10 +#define V_008DFC_SQ_S_OR_B64 0x11 +#define V_008DFC_SQ_S_XOR_B32 0x12 +#define V_008DFC_SQ_S_XOR_B64 0x13 +#define V_008DFC_SQ_S_ANDN2_B32 0x14 +#define V_008DFC_SQ_S_ANDN2_B64 0x15 +#define V_008DFC_SQ_S_ORN2_B32 0x16 +#define V_008DFC_SQ_S_ORN2_B64 0x17 +#define V_008DFC_SQ_S_NAND_B32 0x18 +#define V_008DFC_SQ_S_NAND_B64 0x19 +#define V_008DFC_SQ_S_NOR_B32 0x1A +#define V_008DFC_SQ_S_NOR_B64 0x1B +#define V_008DFC_SQ_S_XNOR_B32 0x1C +#define V_008DFC_SQ_S_XNOR_B64 0x1D +#define V_008DFC_SQ_S_LSHL_B32 0x1E +#define V_008DFC_SQ_S_LSHL_B64 0x1F +#define V_008DFC_SQ_S_LSHR_B32 0x20 +#define V_008DFC_SQ_S_LSHR_B64 0x21 +#define V_008DFC_SQ_S_ASHR_I32 0x22 +#define V_008DFC_SQ_S_ASHR_I64 0x23 +#define V_008DFC_SQ_S_BFM_B32 0x24 +#define V_008DFC_SQ_S_BFM_B64 0x25 +#define V_008DFC_SQ_S_MUL_I32 0x26 +#define V_008DFC_SQ_S_BFE_U32 0x27 +#define V_008DFC_SQ_S_BFE_I32 0x28 +#define V_008DFC_SQ_S_BFE_U64 0x29 +#define V_008DFC_SQ_S_BFE_I64 0x2A +#define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B +#define V_008DFC_SQ_S_ABSDIFF_I32 0x2C +#define S_008DFC_ENCODING(x) (((x) & 0x03) << 30) +#define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03) +#define C_008DFC_ENCODING 0x3FFFFFFF +#define V_008DFC_SQ_ENC_SOP2_FIELD 0x02 +#define R_008DFC_SQ_SOPK 0x008DFC +#define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) +#define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) +#define C_008DFC_SIMM16 0xFFFF0000 +#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) +#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) +#define C_008DFC_SDST 0xFF80FFFF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define S_008DFC_OP(x) (((x) & 0x1F) << 23) +#define G_008DFC_OP(x) (((x) >> 23) & 0x1F) +#define C_008DFC_OP 0xF07FFFFF +#define V_008DFC_SQ_S_MOVK_I32 0x00 +#define V_008DFC_SQ_S_CMOVK_I32 0x02 +#define V_008DFC_SQ_S_CMPK_EQ_I32 0x03 +#define V_008DFC_SQ_S_CMPK_LG_I32 0x04 +#define V_008DFC_SQ_S_CMPK_GT_I32 0x05 +#define V_008DFC_SQ_S_CMPK_GE_I32 0x06 +#define V_008DFC_SQ_S_CMPK_LT_I32 0x07 +#define V_008DFC_SQ_S_CMPK_LE_I32 0x08 +#define V_008DFC_SQ_S_CMPK_EQ_U32 0x09 +#define V_008DFC_SQ_S_CMPK_LG_U32 0x0A +#define V_008DFC_SQ_S_CMPK_GT_U32 0x0B +#define V_008DFC_SQ_S_CMPK_GE_U32 0x0C +#define V_008DFC_SQ_S_CMPK_LT_U32 0x0D +#define V_008DFC_SQ_S_CMPK_LE_U32 0x0E +#define V_008DFC_SQ_S_ADDK_I32 0x0F +#define V_008DFC_SQ_S_MULK_I32 0x10 +#define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11 +#define V_008DFC_SQ_S_GETREG_B32 0x12 +#define V_008DFC_SQ_S_SETREG_B32 0x13 +#define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14 +#define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15 +#define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28) +#define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F) +#define C_008DFC_ENCODING 0x0FFFFFFF +#define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B +#define R_008DFC_SQ_VOP3_0 0x008DFC +#define S_008DFC_VDST(x) (((x) & 0xFF) << 0) +#define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VDST 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_ABS(x) (((x) & 0x07) << 8) +#define G_008DFC_ABS(x) (((x) >> 8) & 0x07) +#define C_008DFC_ABS 0xFFFFF8FF +#define S_008DFC_CLAMP(x) (((x) & 0x1) << 11) +#define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1) +#define C_008DFC_CLAMP 0xFFFFF7FF +#define S_008DFC_OP(x) (((x) & 0x1FF) << 17) +#define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) +#define C_008DFC_OP 0xFC01FFFF +#define V_008DFC_SQ_V_OPC_OFFSET 0x00 +#define V_008DFC_SQ_V_OP2_OFFSET 0x100 +#define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 +#define V_008DFC_SQ_V_MAD_F32 0x141 +#define V_008DFC_SQ_V_MAD_I32_I24 0x142 +#define V_008DFC_SQ_V_MAD_U32_U24 0x143 +#define V_008DFC_SQ_V_CUBEID_F32 0x144 +#define V_008DFC_SQ_V_CUBESC_F32 0x145 +#define V_008DFC_SQ_V_CUBETC_F32 0x146 +#define V_008DFC_SQ_V_CUBEMA_F32 0x147 +#define V_008DFC_SQ_V_BFE_U32 0x148 +#define V_008DFC_SQ_V_BFE_I32 0x149 +#define V_008DFC_SQ_V_BFI_B32 0x14A +#define V_008DFC_SQ_V_FMA_F32 0x14B +#define V_008DFC_SQ_V_FMA_F64 0x14C +#define V_008DFC_SQ_V_LERP_U8 0x14D +#define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E +#define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F +#define V_008DFC_SQ_V_MULLIT_F32 0x150 +#define V_008DFC_SQ_V_MIN3_F32 0x151 +#define V_008DFC_SQ_V_MIN3_I32 0x152 +#define V_008DFC_SQ_V_MIN3_U32 0x153 +#define V_008DFC_SQ_V_MAX3_F32 0x154 +#define V_008DFC_SQ_V_MAX3_I32 0x155 +#define V_008DFC_SQ_V_MAX3_U32 0x156 +#define V_008DFC_SQ_V_MED3_F32 0x157 +#define V_008DFC_SQ_V_MED3_I32 0x158 +#define V_008DFC_SQ_V_MED3_U32 0x159 +#define V_008DFC_SQ_V_SAD_U8 0x15A +#define V_008DFC_SQ_V_SAD_HI_U8 0x15B +#define V_008DFC_SQ_V_SAD_U16 0x15C +#define V_008DFC_SQ_V_SAD_U32 0x15D +#define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E +#define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F +#define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 +#define V_008DFC_SQ_V_LSHL_B64 0x161 +#define V_008DFC_SQ_V_LSHR_B64 0x162 +#define V_008DFC_SQ_V_ASHR_I64 0x163 +#define V_008DFC_SQ_V_ADD_F64 0x164 +#define V_008DFC_SQ_V_MUL_F64 0x165 +#define V_008DFC_SQ_V_MIN_F64 0x166 +#define V_008DFC_SQ_V_MAX_F64 0x167 +#define V_008DFC_SQ_V_LDEXP_F64 0x168 +#define V_008DFC_SQ_V_MUL_LO_U32 0x169 +#define V_008DFC_SQ_V_MUL_HI_U32 0x16A +#define V_008DFC_SQ_V_MUL_LO_I32 0x16B +#define V_008DFC_SQ_V_MUL_HI_I32 0x16C +#define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D +#define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E +#define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F +#define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 +#define V_008DFC_SQ_V_MSAD_U8 0x171 +#define V_008DFC_SQ_V_QSAD_U8 0x172 +#define V_008DFC_SQ_V_MQSAD_U8 0x173 +#define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 +#define V_008DFC_SQ_V_OP1_OFFSET 0x180 +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 +#define R_008DFC_SQ_VOP2 0x008DFC +#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) +#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) +#define C_008DFC_SRC0 0xFFFFFE00 +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define V_008DFC_SQ_M0 0x7C +#define V_008DFC_SQ_EXEC_LO 0x7E +#define V_008DFC_SQ_EXEC_HI 0x7F +#define V_008DFC_SQ_SRC_0 0x80 +#define V_008DFC_SQ_SRC_1_INT 0x81 +#define V_008DFC_SQ_SRC_2_INT 0x82 +#define V_008DFC_SQ_SRC_3_INT 0x83 +#define V_008DFC_SQ_SRC_4_INT 0x84 +#define V_008DFC_SQ_SRC_5_INT 0x85 +#define V_008DFC_SQ_SRC_6_INT 0x86 +#define V_008DFC_SQ_SRC_7_INT 0x87 +#define V_008DFC_SQ_SRC_8_INT 0x88 +#define V_008DFC_SQ_SRC_9_INT 0x89 +#define V_008DFC_SQ_SRC_10_INT 0x8A +#define V_008DFC_SQ_SRC_11_INT 0x8B +#define V_008DFC_SQ_SRC_12_INT 0x8C +#define V_008DFC_SQ_SRC_13_INT 0x8D +#define V_008DFC_SQ_SRC_14_INT 0x8E +#define V_008DFC_SQ_SRC_15_INT 0x8F +#define V_008DFC_SQ_SRC_16_INT 0x90 +#define V_008DFC_SQ_SRC_17_INT 0x91 +#define V_008DFC_SQ_SRC_18_INT 0x92 +#define V_008DFC_SQ_SRC_19_INT 0x93 +#define V_008DFC_SQ_SRC_20_INT 0x94 +#define V_008DFC_SQ_SRC_21_INT 0x95 +#define V_008DFC_SQ_SRC_22_INT 0x96 +#define V_008DFC_SQ_SRC_23_INT 0x97 +#define V_008DFC_SQ_SRC_24_INT 0x98 +#define V_008DFC_SQ_SRC_25_INT 0x99 +#define V_008DFC_SQ_SRC_26_INT 0x9A +#define V_008DFC_SQ_SRC_27_INT 0x9B +#define V_008DFC_SQ_SRC_28_INT 0x9C +#define V_008DFC_SQ_SRC_29_INT 0x9D +#define V_008DFC_SQ_SRC_30_INT 0x9E +#define V_008DFC_SQ_SRC_31_INT 0x9F +#define V_008DFC_SQ_SRC_32_INT 0xA0 +#define V_008DFC_SQ_SRC_33_INT 0xA1 +#define V_008DFC_SQ_SRC_34_INT 0xA2 +#define V_008DFC_SQ_SRC_35_INT 0xA3 +#define V_008DFC_SQ_SRC_36_INT 0xA4 +#define V_008DFC_SQ_SRC_37_INT 0xA5 +#define V_008DFC_SQ_SRC_38_INT 0xA6 +#define V_008DFC_SQ_SRC_39_INT 0xA7 +#define V_008DFC_SQ_SRC_40_INT 0xA8 +#define V_008DFC_SQ_SRC_41_INT 0xA9 +#define V_008DFC_SQ_SRC_42_INT 0xAA +#define V_008DFC_SQ_SRC_43_INT 0xAB +#define V_008DFC_SQ_SRC_44_INT 0xAC +#define V_008DFC_SQ_SRC_45_INT 0xAD +#define V_008DFC_SQ_SRC_46_INT 0xAE +#define V_008DFC_SQ_SRC_47_INT 0xAF +#define V_008DFC_SQ_SRC_48_INT 0xB0 +#define V_008DFC_SQ_SRC_49_INT 0xB1 +#define V_008DFC_SQ_SRC_50_INT 0xB2 +#define V_008DFC_SQ_SRC_51_INT 0xB3 +#define V_008DFC_SQ_SRC_52_INT 0xB4 +#define V_008DFC_SQ_SRC_53_INT 0xB5 +#define V_008DFC_SQ_SRC_54_INT 0xB6 +#define V_008DFC_SQ_SRC_55_INT 0xB7 +#define V_008DFC_SQ_SRC_56_INT 0xB8 +#define V_008DFC_SQ_SRC_57_INT 0xB9 +#define V_008DFC_SQ_SRC_58_INT 0xBA +#define V_008DFC_SQ_SRC_59_INT 0xBB +#define V_008DFC_SQ_SRC_60_INT 0xBC +#define V_008DFC_SQ_SRC_61_INT 0xBD +#define V_008DFC_SQ_SRC_62_INT 0xBE +#define V_008DFC_SQ_SRC_63_INT 0xBF +#define V_008DFC_SQ_SRC_64_INT 0xC0 +#define V_008DFC_SQ_SRC_M_1_INT 0xC1 +#define V_008DFC_SQ_SRC_M_2_INT 0xC2 +#define V_008DFC_SQ_SRC_M_3_INT 0xC3 +#define V_008DFC_SQ_SRC_M_4_INT 0xC4 +#define V_008DFC_SQ_SRC_M_5_INT 0xC5 +#define V_008DFC_SQ_SRC_M_6_INT 0xC6 +#define V_008DFC_SQ_SRC_M_7_INT 0xC7 +#define V_008DFC_SQ_SRC_M_8_INT 0xC8 +#define V_008DFC_SQ_SRC_M_9_INT 0xC9 +#define V_008DFC_SQ_SRC_M_10_INT 0xCA +#define V_008DFC_SQ_SRC_M_11_INT 0xCB +#define V_008DFC_SQ_SRC_M_12_INT 0xCC +#define V_008DFC_SQ_SRC_M_13_INT 0xCD +#define V_008DFC_SQ_SRC_M_14_INT 0xCE +#define V_008DFC_SQ_SRC_M_15_INT 0xCF +#define V_008DFC_SQ_SRC_M_16_INT 0xD0 +#define V_008DFC_SQ_SRC_0_5 0xF0 +#define V_008DFC_SQ_SRC_M_0_5 0xF1 +#define V_008DFC_SQ_SRC_1 0xF2 +#define V_008DFC_SQ_SRC_M_1 0xF3 +#define V_008DFC_SQ_SRC_2 0xF4 +#define V_008DFC_SQ_SRC_M_2 0xF5 +#define V_008DFC_SQ_SRC_4 0xF6 +#define V_008DFC_SQ_SRC_M_4 0xF7 +#define V_008DFC_SQ_SRC_VCCZ 0xFB +#define V_008DFC_SQ_SRC_EXECZ 0xFC +#define V_008DFC_SQ_SRC_SCC 0xFD +#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE +#define V_008DFC_SQ_SRC_VGPR 0x100 +#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) +#define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) +#define C_008DFC_VSRC1 0xFFFE01FF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_VDST(x) (((x) & 0xFF) << 17) +#define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) +#define C_008DFC_VDST 0xFE01FFFF +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_OP(x) (((x) & 0x3F) << 25) +#define G_008DFC_OP(x) (((x) >> 25) & 0x3F) +#define C_008DFC_OP 0x81FFFFFF +#define V_008DFC_SQ_V_CNDMASK_B32 0x00 +#define V_008DFC_SQ_V_READLANE_B32 0x01 +#define V_008DFC_SQ_V_WRITELANE_B32 0x02 +#define V_008DFC_SQ_V_ADD_F32 0x03 +#define V_008DFC_SQ_V_SUB_F32 0x04 +#define V_008DFC_SQ_V_SUBREV_F32 0x05 +#define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06 +#define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07 +#define V_008DFC_SQ_V_MUL_F32 0x08 +#define V_008DFC_SQ_V_MUL_I32_I24 0x09 +#define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A +#define V_008DFC_SQ_V_MUL_U32_U24 0x0B +#define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C +#define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D +#define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E +#define V_008DFC_SQ_V_MIN_F32 0x0F +#define V_008DFC_SQ_V_MAX_F32 0x10 +#define V_008DFC_SQ_V_MIN_I32 0x11 +#define V_008DFC_SQ_V_MAX_I32 0x12 +#define V_008DFC_SQ_V_MIN_U32 0x13 +#define V_008DFC_SQ_V_MAX_U32 0x14 +#define V_008DFC_SQ_V_LSHR_B32 0x15 +#define V_008DFC_SQ_V_LSHRREV_B32 0x16 +#define V_008DFC_SQ_V_ASHR_I32 0x17 +#define V_008DFC_SQ_V_ASHRREV_I32 0x18 +#define V_008DFC_SQ_V_LSHL_B32 0x19 +#define V_008DFC_SQ_V_LSHLREV_B32 0x1A +#define V_008DFC_SQ_V_AND_B32 0x1B +#define V_008DFC_SQ_V_OR_B32 0x1C +#define V_008DFC_SQ_V_XOR_B32 0x1D +#define V_008DFC_SQ_V_BFM_B32 0x1E +#define V_008DFC_SQ_V_MAC_F32 0x1F +#define V_008DFC_SQ_V_MADMK_F32 0x20 +#define V_008DFC_SQ_V_MADAK_F32 0x21 +#define V_008DFC_SQ_V_BCNT_U32_B32 0x22 +#define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23 +#define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24 +#define V_008DFC_SQ_V_ADD_I32 0x25 +#define V_008DFC_SQ_V_SUB_I32 0x26 +#define V_008DFC_SQ_V_SUBREV_I32 0x27 +#define V_008DFC_SQ_V_ADDC_U32 0x28 +#define V_008DFC_SQ_V_SUBB_U32 0x29 +#define V_008DFC_SQ_V_SUBBREV_U32 0x2A +#define V_008DFC_SQ_V_LDEXP_F32 0x2B +#define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C +#define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D +#define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E +#define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F +#define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30 +#define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31 +#define S_008DFC_ENCODING(x) (((x) & 0x1) << 31) +#define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1) +#define C_008DFC_ENCODING 0x7FFFFFFF +#define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC +#define S_008DFC_VDST(x) (((x) & 0xFF) << 0) +#define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) +#define C_008DFC_VDST 0xFFFFFF00 +#define V_008DFC_SQ_VGPR 0x00 +#define S_008DFC_SDST(x) (((x) & 0x7F) << 8) +#define G_008DFC_SDST(x) (((x) >> 8) & 0x7F) +#define C_008DFC_SDST 0xFFFF80FF +#define V_008DFC_SQ_SGPR 0x00 +#define V_008DFC_SQ_VCC_LO 0x6A +#define V_008DFC_SQ_VCC_HI 0x6B +#define V_008DFC_SQ_TBA_LO 0x6C +#define V_008DFC_SQ_TBA_HI 0x6D +#define V_008DFC_SQ_TMA_LO 0x6E +#define V_008DFC_SQ_TMA_HI 0x6F +#define V_008DFC_SQ_TTMP0 0x70 +#define V_008DFC_SQ_TTMP1 0x71 +#define V_008DFC_SQ_TTMP2 0x72 +#define V_008DFC_SQ_TTMP3 0x73 +#define V_008DFC_SQ_TTMP4 0x74 +#define V_008DFC_SQ_TTMP5 0x75 +#define V_008DFC_SQ_TTMP6 0x76 +#define V_008DFC_SQ_TTMP7 0x77 +#define V_008DFC_SQ_TTMP8 0x78 +#define V_008DFC_SQ_TTMP9 0x79 +#define V_008DFC_SQ_TTMP10 0x7A +#define V_008DFC_SQ_TTMP11 0x7B +#define S_008DFC_OP(x) (((x) & 0x1FF) << 17) +#define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) +#define C_008DFC_OP 0xFC01FFFF +#define V_008DFC_SQ_V_OPC_OFFSET 0x00 +#define V_008DFC_SQ_V_OP2_OFFSET 0x100 +#define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 +#define V_008DFC_SQ_V_MAD_F32 0x141 +#define V_008DFC_SQ_V_MAD_I32_I24 0x142 +#define V_008DFC_SQ_V_MAD_U32_U24 0x143 +#define V_008DFC_SQ_V_CUBEID_F32 0x144 +#define V_008DFC_SQ_V_CUBESC_F32 0x145 +#define V_008DFC_SQ_V_CUBETC_F32 0x146 +#define V_008DFC_SQ_V_CUBEMA_F32 0x147 +#define V_008DFC_SQ_V_BFE_U32 0x148 +#define V_008DFC_SQ_V_BFE_I32 0x149 +#define V_008DFC_SQ_V_BFI_B32 0x14A +#define V_008DFC_SQ_V_FMA_F32 0x14B +#define V_008DFC_SQ_V_FMA_F64 0x14C +#define V_008DFC_SQ_V_LERP_U8 0x14D +#define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E +#define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F +#define V_008DFC_SQ_V_MULLIT_F32 0x150 +#define V_008DFC_SQ_V_MIN3_F32 0x151 +#define V_008DFC_SQ_V_MIN3_I32 0x152 +#define V_008DFC_SQ_V_MIN3_U32 0x153 +#define V_008DFC_SQ_V_MAX3_F32 0x154 +#define V_008DFC_SQ_V_MAX3_I32 0x155 +#define V_008DFC_SQ_V_MAX3_U32 0x156 +#define V_008DFC_SQ_V_MED3_F32 0x157 +#define V_008DFC_SQ_V_MED3_I32 0x158 +#define V_008DFC_SQ_V_MED3_U32 0x159 +#define V_008DFC_SQ_V_SAD_U8 0x15A +#define V_008DFC_SQ_V_SAD_HI_U8 0x15B +#define V_008DFC_SQ_V_SAD_U16 0x15C +#define V_008DFC_SQ_V_SAD_U32 0x15D +#define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E +#define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F +#define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 +#define V_008DFC_SQ_V_LSHL_B64 0x161 +#define V_008DFC_SQ_V_LSHR_B64 0x162 +#define V_008DFC_SQ_V_ASHR_I64 0x163 +#define V_008DFC_SQ_V_ADD_F64 0x164 +#define V_008DFC_SQ_V_MUL_F64 0x165 +#define V_008DFC_SQ_V_MIN_F64 0x166 +#define V_008DFC_SQ_V_MAX_F64 0x167 +#define V_008DFC_SQ_V_LDEXP_F64 0x168 +#define V_008DFC_SQ_V_MUL_LO_U32 0x169 +#define V_008DFC_SQ_V_MUL_HI_U32 0x16A +#define V_008DFC_SQ_V_MUL_LO_I32 0x16B +#define V_008DFC_SQ_V_MUL_HI_I32 0x16C +#define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D +#define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E +#define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F +#define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 +#define V_008DFC_SQ_V_MSAD_U8 0x171 +#define V_008DFC_SQ_V_QSAD_U8 0x172 +#define V_008DFC_SQ_V_MQSAD_U8 0x173 +#define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 +#define V_008DFC_SQ_V_OP1_OFFSET 0x180 +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 +#define R_008DFC_SQ_MUBUF_0 0x008DFC +#define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) +#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) +#define C_008DFC_OFFSET 0xFFFFF000 +#define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) +#define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) +#define C_008DFC_OFFEN 0xFFFFEFFF +#define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) +#define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) +#define C_008DFC_IDXEN 0xFFFFDFFF +#define S_008DFC_GLC(x) (((x) & 0x1) << 14) +#define G_008DFC_GLC(x) (((x) >> 14) & 0x1) +#define C_008DFC_GLC 0xFFFFBFFF +#define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) +#define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) +#define C_008DFC_ADDR64 0xFFFF7FFF +#define S_008DFC_LDS(x) (((x) & 0x1) << 16) +#define G_008DFC_LDS(x) (((x) >> 16) & 0x1) +#define C_008DFC_LDS 0xFFFEFFFF +#define S_008DFC_OP(x) (((x) & 0x7F) << 18) +#define G_008DFC_OP(x) (((x) >> 18) & 0x7F) +#define C_008DFC_OP 0xFE03FFFF +#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00 +#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01 +#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02 +#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03 +#define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04 +#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05 +#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06 +#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07 +#define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08 +#define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09 +#define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A +#define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B +#define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C +#define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D +#define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E +#define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18 +#define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A +#define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C +#define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D +#define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E +#define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30 +#define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31 +#define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32 +#define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33 +#define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 +#define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35 +#define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36 +#define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37 +#define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38 +#define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39 +#define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A +#define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B +#define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C +#define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D +#define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E +#define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F +#define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40 +#define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50 +#define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 +#define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52 +#define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53 +#define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 +#define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55 +#define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56 +#define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57 +#define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58 +#define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59 +#define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A +#define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B +#define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C +#define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D +#define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E +#define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F +#define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60 +#define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70 +#define V_008DFC_SQ_BUFFER_WBINVL1 0x71 +#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) +#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) +#define C_008DFC_ENCODING 0x03FFFFFF +#define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38 +#endif +#define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00 +#define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04 +#define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0) +#define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF) +#define C_008F04_BASE_ADDRESS_HI 0xFFFF0000 +#define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16) +#define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF) +#define C_008F04_STRIDE 0xC000FFFF +#define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30) +#define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1) +#define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF +#define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31) +#define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1) +#define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF +#define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08 +#define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C +#define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0) +#define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07) +#define C_008F0C_DST_SEL_X 0xFFFFFFF8 +#define V_008F0C_SQ_SEL_0 0x00 +#define V_008F0C_SQ_SEL_1 0x01 +#define V_008F0C_SQ_SEL_RESERVED_0 0x02 +#define V_008F0C_SQ_SEL_RESERVED_1 0x03 +#define V_008F0C_SQ_SEL_X 0x04 +#define V_008F0C_SQ_SEL_Y 0x05 +#define V_008F0C_SQ_SEL_Z 0x06 +#define V_008F0C_SQ_SEL_W 0x07 +#define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3) +#define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07) +#define C_008F0C_DST_SEL_Y 0xFFFFFFC7 +#define V_008F0C_SQ_SEL_0 0x00 +#define V_008F0C_SQ_SEL_1 0x01 +#define V_008F0C_SQ_SEL_RESERVED_0 0x02 +#define V_008F0C_SQ_SEL_RESERVED_1 0x03 +#define V_008F0C_SQ_SEL_X 0x04 +#define V_008F0C_SQ_SEL_Y 0x05 +#define V_008F0C_SQ_SEL_Z 0x06 +#define V_008F0C_SQ_SEL_W 0x07 +#define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6) +#define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07) +#define C_008F0C_DST_SEL_Z 0xFFFFFE3F +#define V_008F0C_SQ_SEL_0 0x00 +#define V_008F0C_SQ_SEL_1 0x01 +#define V_008F0C_SQ_SEL_RESERVED_0 0x02 +#define V_008F0C_SQ_SEL_RESERVED_1 0x03 +#define V_008F0C_SQ_SEL_X 0x04 +#define V_008F0C_SQ_SEL_Y 0x05 +#define V_008F0C_SQ_SEL_Z 0x06 +#define V_008F0C_SQ_SEL_W 0x07 +#define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9) +#define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07) +#define C_008F0C_DST_SEL_W 0xFFFFF1FF +#define V_008F0C_SQ_SEL_0 0x00 +#define V_008F0C_SQ_SEL_1 0x01 +#define V_008F0C_SQ_SEL_RESERVED_0 0x02 +#define V_008F0C_SQ_SEL_RESERVED_1 0x03 +#define V_008F0C_SQ_SEL_X 0x04 +#define V_008F0C_SQ_SEL_Y 0x05 +#define V_008F0C_SQ_SEL_Z 0x06 +#define V_008F0C_SQ_SEL_W 0x07 +#define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12) +#define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07) +#define C_008F0C_NUM_FORMAT 0xFFFF8FFF +#define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00 +#define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01 +#define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02 +#define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03 +#define V_008F0C_BUF_NUM_FORMAT_UINT 0x04 +#define V_008F0C_BUF_NUM_FORMAT_SINT 0x05 +#define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06 +#define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07 +#define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15) +#define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F) +#define C_008F0C_DATA_FORMAT 0xFFF87FFF +#define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00 +#define V_008F0C_BUF_DATA_FORMAT_8 0x01 +#define V_008F0C_BUF_DATA_FORMAT_16 0x02 +#define V_008F0C_BUF_DATA_FORMAT_8_8 0x03 +#define V_008F0C_BUF_DATA_FORMAT_32 0x04 +#define V_008F0C_BUF_DATA_FORMAT_16_16 0x05 +#define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06 +#define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07 +#define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08 +#define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09 +#define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A +#define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B +#define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C +#define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D +#define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E +#define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F +#define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19) +#define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03) +#define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF +#define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21) +#define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03) +#define C_008F0C_INDEX_STRIDE 0xFF9FFFFF +#define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23) +#define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1) +#define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF +#define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25) +#define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1) +#define C_008F0C_HASH_ENABLE 0xFDFFFFFF +#define S_008F0C_HEAP(x) (((x) & 0x1) << 26) +#define G_008F0C_HEAP(x) (((x) >> 26) & 0x1) +#define C_008F0C_HEAP 0xFBFFFFFF +#define S_008F0C_TYPE(x) (((x) & 0x03) << 30) +#define G_008F0C_TYPE(x) (((x) >> 30) & 0x03) +#define C_008F0C_TYPE 0x3FFFFFFF +#define V_008F0C_SQ_RSRC_BUF 0x00 +#define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01 +#define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02 +#define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03 +#define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10 +#define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14 +#define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) +#define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) +#define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00 +#define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8) +#define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF) +#define C_008F14_MIN_LOD 0xFFF000FF +#define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20) +#define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F) +#define C_008F14_DATA_FORMAT 0xFC0FFFFF +#define V_008F14_IMG_DATA_FORMAT_INVALID 0x00 +#define V_008F14_IMG_DATA_FORMAT_8 0x01 +#define V_008F14_IMG_DATA_FORMAT_16 0x02 +#define V_008F14_IMG_DATA_FORMAT_8_8 0x03 +#define V_008F14_IMG_DATA_FORMAT_32 0x04 +#define V_008F14_IMG_DATA_FORMAT_16_16 0x05 +#define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06 +#define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07 +#define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08 +#define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09 +#define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A +#define V_008F14_IMG_DATA_FORMAT_32_32 0x0B +#define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C +#define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D +#define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E +#define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F +#define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10 +#define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11 +#define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12 +#define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13 +#define V_008F14_IMG_DATA_FORMAT_8_24 0x14 +#define V_008F14_IMG_DATA_FORMAT_24_8 0x15 +#define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16 +#define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17 +#define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18 +#define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19 +#define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A +#define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B +#define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C +#define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D +#define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E +#define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F +#define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20 +#define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21 +#define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22 +#define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A +#define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30 +#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31 +#define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32 +#define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33 +#define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34 +#define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35 +#define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36 +#define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37 +#define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38 +#define V_008F14_IMG_DATA_FORMAT_4_4 0x39 +#define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A +#define V_008F14_IMG_DATA_FORMAT_1 0x3B +#define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C +#define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D +#define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E +#define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F +#define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26) +#define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F) +#define C_008F14_NUM_FORMAT 0xC3FFFFFF +#define V_008F14_IMG_NUM_FORMAT_UNORM 0x00 +#define V_008F14_IMG_NUM_FORMAT_SNORM 0x01 +#define V_008F14_IMG_NUM_FORMAT_USCALED 0x02 +#define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03 +#define V_008F14_IMG_NUM_FORMAT_UINT 0x04 +#define V_008F14_IMG_NUM_FORMAT_SINT 0x05 +#define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06 +#define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07 +#define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08 +#define V_008F14_IMG_NUM_FORMAT_SRGB 0x09 +#define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A +#define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B +#define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C +#define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D +#define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E +#define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F +#define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18 +#define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0) +#define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF) +#define C_008F18_WIDTH 0xFFFFC000 +#define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14) +#define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF) +#define C_008F18_HEIGHT 0xF0003FFF +#define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28) +#define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07) +#define C_008F18_PERF_MOD 0x8FFFFFFF +#define S_008F18_INTERLACED(x) (((x) & 0x1) << 31) +#define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1) +#define C_008F18_INTERLACED 0x7FFFFFFF +#define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C +#define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0) +#define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07) +#define C_008F1C_DST_SEL_X 0xFFFFFFF8 +#define V_008F1C_SQ_SEL_0 0x00 +#define V_008F1C_SQ_SEL_1 0x01 +#define V_008F1C_SQ_SEL_RESERVED_0 0x02 +#define V_008F1C_SQ_SEL_RESERVED_1 0x03 +#define V_008F1C_SQ_SEL_X 0x04 +#define V_008F1C_SQ_SEL_Y 0x05 +#define V_008F1C_SQ_SEL_Z 0x06 +#define V_008F1C_SQ_SEL_W 0x07 +#define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3) +#define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07) +#define C_008F1C_DST_SEL_Y 0xFFFFFFC7 +#define V_008F1C_SQ_SEL_0 0x00 +#define V_008F1C_SQ_SEL_1 0x01 +#define V_008F1C_SQ_SEL_RESERVED_0 0x02 +#define V_008F1C_SQ_SEL_RESERVED_1 0x03 +#define V_008F1C_SQ_SEL_X 0x04 +#define V_008F1C_SQ_SEL_Y 0x05 +#define V_008F1C_SQ_SEL_Z 0x06 +#define V_008F1C_SQ_SEL_W 0x07 +#define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6) +#define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07) +#define C_008F1C_DST_SEL_Z 0xFFFFFE3F +#define V_008F1C_SQ_SEL_0 0x00 +#define V_008F1C_SQ_SEL_1 0x01 +#define V_008F1C_SQ_SEL_RESERVED_0 0x02 +#define V_008F1C_SQ_SEL_RESERVED_1 0x03 +#define V_008F1C_SQ_SEL_X 0x04 +#define V_008F1C_SQ_SEL_Y 0x05 +#define V_008F1C_SQ_SEL_Z 0x06 +#define V_008F1C_SQ_SEL_W 0x07 +#define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9) +#define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07) +#define C_008F1C_DST_SEL_W 0xFFFFF1FF +#define V_008F1C_SQ_SEL_0 0x00 +#define V_008F1C_SQ_SEL_1 0x01 +#define V_008F1C_SQ_SEL_RESERVED_0 0x02 +#define V_008F1C_SQ_SEL_RESERVED_1 0x03 +#define V_008F1C_SQ_SEL_X 0x04 +#define V_008F1C_SQ_SEL_Y 0x05 +#define V_008F1C_SQ_SEL_Z 0x06 +#define V_008F1C_SQ_SEL_W 0x07 +#define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12) +#define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F) +#define C_008F1C_BASE_LEVEL 0xFFFF0FFF +#define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16) +#define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F) +#define C_008F1C_LAST_LEVEL 0xFFF0FFFF +#define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20) +#define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F) +#define C_008F1C_TILING_INDEX 0xFE0FFFFF +#define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25) +#define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1) +#define C_008F1C_POW2_PAD 0xFDFFFFFF +#define S_008F1C_TYPE(x) (((x) & 0x0F) << 28) +#define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F) +#define C_008F1C_TYPE 0x0FFFFFFF +#define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00 +#define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01 +#define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02 +#define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03 +#define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04 +#define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05 +#define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06 +#define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07 +#define V_008F1C_SQ_RSRC_IMG_1D 0x08 +#define V_008F1C_SQ_RSRC_IMG_2D 0x09 +#define V_008F1C_SQ_RSRC_IMG_3D 0x0A +#define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B +#define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C +#define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D +#define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E +#define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F +#define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20 +#define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0) +#define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) +#define C_008F20_DEPTH 0xFFFFE000 +#define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13) +#define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF) +#define C_008F20_PITCH 0xF8001FFF +#define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24 +#define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0) +#define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF) +#define C_008F24_BASE_ARRAY 0xFFFFE000 +#define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13) +#define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF) +#define C_008F24_LAST_ARRAY 0xFC001FFF +#define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28 +#define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0) +#define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF) +#define C_008F28_MIN_LOD_WARN 0xFFFFF000 +#define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C +#define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30 +#define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0) +#define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07) +#define C_008F30_CLAMP_X 0xFFFFFFF8 +#define V_008F30_SQ_TEX_WRAP 0x00 +#define V_008F30_SQ_TEX_MIRROR 0x01 +#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 +#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 +#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 +#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 +#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 +#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 +#define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3) +#define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07) +#define C_008F30_CLAMP_Y 0xFFFFFFC7 +#define V_008F30_SQ_TEX_WRAP 0x00 +#define V_008F30_SQ_TEX_MIRROR 0x01 +#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 +#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 +#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 +#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 +#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 +#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 +#define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6) +#define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07) +#define C_008F30_CLAMP_Z 0xFFFFFE3F +#define V_008F30_SQ_TEX_WRAP 0x00 +#define V_008F30_SQ_TEX_MIRROR 0x01 +#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 +#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 +#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 +#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 +#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 +#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 +#define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12) +#define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07) +#define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF +#define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06 +#define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07 +#define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15) +#define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1) +#define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF +#define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19) +#define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1) +#define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF +#define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20) +#define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1) +#define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF +#define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27) +#define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1) +#define C_008F30_TRUNC_COORD 0xF7FFFFFF +#define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28) +#define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1) +#define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF +#define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29) +#define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03) +#define C_008F30_FILTER_MODE 0x9FFFFFFF +#define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34 +#define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0) +#define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF) +#define C_008F34_MIN_LOD 0xFFFFF000 +#define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12) +#define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF) +#define C_008F34_MAX_LOD 0xFF000FFF +#define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24) +#define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F) +#define C_008F34_PERF_MIP 0xF0FFFFFF +#define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28) +#define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F) +#define C_008F34_PERF_Z 0x0FFFFFFF +#define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38 +#define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0) +#define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF) +#define C_008F38_LOD_BIAS 0xFFFFC000 +#define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14) +#define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F) +#define C_008F38_LOD_BIAS_SEC 0xFFF03FFF +#define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20) +#define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03) +#define C_008F38_XY_MAG_FILTER 0xFFCFFFFF +#define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 +#define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 +#define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22) +#define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03) +#define C_008F38_XY_MIN_FILTER 0xFF3FFFFF +#define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 +#define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 +#define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24) +#define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03) +#define C_008F38_Z_FILTER 0xFCFFFFFF +#define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 +#define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 +#define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 +#define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26) +#define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03) +#define C_008F38_MIP_FILTER 0xF3FFFFFF +#define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 +#define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 +#define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 +#define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28) +#define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1) +#define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF +#define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29) +#define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1) +#define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF +#define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30) +#define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1) +#define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF +#define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C +#define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0) +#define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF) +#define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000 +#define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30) +#define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03) +#define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF +#define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00 +#define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01 +#define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02 +#define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03 +#define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC +#define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0) +#define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F) +#define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0 +#define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4) +#define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F) +#define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F +#define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8) +#define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F) +#define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF +#define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12) +#define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F) +#define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF +#define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16) +#define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F) +#define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF +#define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 +#define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0) +#define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF) +#define C_0090E0_PS_CU_EN 0xFFFF0000 +#define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16) +#define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF) +#define C_0090E0_VS_CU_EN 0x0000FFFF +#define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 +#define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0) +#define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF) +#define C_0090E4_GS_CU_EN 0xFFFF0000 +#define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16) +#define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF) +#define C_0090E4_ES_CU_EN 0x0000FFFF +#define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 +#define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0) +#define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF) +#define C_0090E8_LSHS_CU_EN 0xFFFF0000 +#define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC +#define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) +#define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) +#define C_0090EC_MAX_WAVE_ID 0xFFFFF000 +#define R_0090F0_SPI_ARB_PRIORITY 0x0090F0 +#define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0) +#define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07) +#define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8 +#define V_0090F0_X_R0 0x00 +#define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3) +#define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07) +#define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7 +#define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6) +#define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07) +#define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F +#define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 +#define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0) +#define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF) +#define C_0090F4_TS0_DURATION 0xFFFF0000 +#define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16) +#define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF) +#define C_0090F4_TS1_DURATION 0x0000FFFF +#define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 +#define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0) +#define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF) +#define C_0090F8_TS2_DURATION 0xFFFF0000 +#define R_009100_SPI_CONFIG_CNTL 0x009100 +#define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0) +#define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF) +#define C_009100_GPR_WRITE_PRIORITY 0xFFE00000 +#define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21) +#define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07) +#define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF +#define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24) +#define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1) +#define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF +#define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25) +#define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1) +#define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF +#define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26) +#define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1) +#define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF +#define R_00913C_SPI_CONFIG_CNTL_1 0x00913C +#define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0) +#define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F) +#define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0 +#define V_00913C_X_DELAY_14_CLKS 0x00 +#define V_00913C_X_DELAY_16_CLKS 0x01 +#define V_00913C_X_DELAY_18_CLKS 0x02 +#define V_00913C_X_DELAY_20_CLKS 0x03 +#define V_00913C_X_DELAY_22_CLKS 0x04 +#define V_00913C_X_DELAY_24_CLKS 0x05 +#define V_00913C_X_DELAY_26_CLKS 0x06 +#define V_00913C_X_DELAY_28_CLKS 0x07 +#define V_00913C_X_DELAY_30_CLKS 0x08 +#define V_00913C_X_DELAY_32_CLKS 0x09 +#define V_00913C_X_DELAY_34_CLKS 0x0A +#define V_00913C_X_DELAY_4_CLKS 0x0B +#define V_00913C_X_DELAY_6_CLKS 0x0C +#define V_00913C_X_DELAY_8_CLKS 0x0D +#define V_00913C_X_DELAY_10_CLKS 0x0E +#define V_00913C_X_DELAY_12_CLKS 0x0F +#define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4) +#define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1) +#define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF +#define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6) +#define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1) +#define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF +#define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7) +#define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1) +#define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F +#define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16) +#define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF) +#define C_00913C_PC_LIMIT_SIZE 0x0000FFFF +#define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C +#define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0) +#define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F) +#define C_00936C_TYPE_A 0xFFFFFFF0 +#define S_00936C_VGPR_A(x) (((x) & 0x07) << 4) +#define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07) +#define C_00936C_VGPR_A 0xFFFFFF8F +#define S_00936C_SGPR_A(x) (((x) & 0x07) << 7) +#define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07) +#define C_00936C_SGPR_A 0xFFFFFC7F +#define S_00936C_LDS_A(x) (((x) & 0x07) << 10) +#define G_00936C_LDS_A(x) (((x) >> 10) & 0x07) +#define C_00936C_LDS_A 0xFFFFE3FF +#define S_00936C_WAVES_A(x) (((x) & 0x03) << 13) +#define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03) +#define C_00936C_WAVES_A 0xFFFF9FFF +#define S_00936C_EN_A(x) (((x) & 0x1) << 15) +#define G_00936C_EN_A(x) (((x) >> 15) & 0x1) +#define C_00936C_EN_A 0xFFFF7FFF +#define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16) +#define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F) +#define C_00936C_TYPE_B 0xFFF0FFFF +#define S_00936C_VGPR_B(x) (((x) & 0x07) << 20) +#define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07) +#define C_00936C_VGPR_B 0xFF8FFFFF +#define S_00936C_SGPR_B(x) (((x) & 0x07) << 23) +#define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07) +#define C_00936C_SGPR_B 0xFC7FFFFF +#define S_00936C_LDS_B(x) (((x) & 0x07) << 26) +#define G_00936C_LDS_B(x) (((x) >> 26) & 0x07) +#define C_00936C_LDS_B 0xE3FFFFFF +#define S_00936C_WAVES_B(x) (((x) & 0x03) << 29) +#define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03) +#define C_00936C_WAVES_B 0x9FFFFFFF +#define S_00936C_EN_B(x) (((x) & 0x1) << 31) +#define G_00936C_EN_B(x) (((x) >> 31) & 0x1) +#define C_00936C_EN_B 0x7FFFFFFF +#define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C +#define R_009858_DB_SUBTILE_CONTROL 0x009858 +#define S_009858_MSAA1_X(x) (((x) & 0x03) << 0) +#define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03) +#define C_009858_MSAA1_X 0xFFFFFFFC +#define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2) +#define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03) +#define C_009858_MSAA1_Y 0xFFFFFFF3 +#define S_009858_MSAA2_X(x) (((x) & 0x03) << 4) +#define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03) +#define C_009858_MSAA2_X 0xFFFFFFCF +#define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6) +#define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03) +#define C_009858_MSAA2_Y 0xFFFFFF3F +#define S_009858_MSAA4_X(x) (((x) & 0x03) << 8) +#define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03) +#define C_009858_MSAA4_X 0xFFFFFCFF +#define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10) +#define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03) +#define C_009858_MSAA4_Y 0xFFFFF3FF +#define S_009858_MSAA8_X(x) (((x) & 0x03) << 12) +#define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03) +#define C_009858_MSAA8_X 0xFFFFCFFF +#define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14) +#define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03) +#define C_009858_MSAA8_Y 0xFFFF3FFF +#define S_009858_MSAA16_X(x) (((x) & 0x03) << 16) +#define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03) +#define C_009858_MSAA16_X 0xFFFCFFFF +#define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18) +#define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03) +#define C_009858_MSAA16_Y 0xFFF3FFFF +#define R_009910_GB_TILE_MODE0 0x009910 +#define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0) +#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03) +#define C_009910_MICRO_TILE_MODE 0xFFFFFFFC +#define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00 +#define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01 +#define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02 +#define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03 +#define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2) +#define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F) +#define C_009910_ARRAY_MODE 0xFFFFFFC3 +#define V_009910_ARRAY_LINEAR_GENERAL 0x00 +#define V_009910_ARRAY_LINEAR_ALIGNED 0x01 +#define V_009910_ARRAY_1D_TILED_THIN1 0x02 +#define V_009910_ARRAY_1D_TILED_THICK 0x03 +#define V_009910_ARRAY_2D_TILED_THIN1 0x04 +#define V_009910_ARRAY_2D_TILED_THICK 0x07 +#define V_009910_ARRAY_2D_TILED_XTHICK 0x08 +#define V_009910_ARRAY_3D_TILED_THIN1 0x0C +#define V_009910_ARRAY_3D_TILED_THICK 0x0D +#define V_009910_ARRAY_3D_TILED_XTHICK 0x0E +#define V_009910_ARRAY_POWER_SAVE 0x0F +#define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6) +#define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F) +#define C_009910_PIPE_CONFIG 0xFFFFF83F +#define V_009910_ADDR_SURF_P2 0x00 +#define V_009910_ADDR_SURF_P2_RESERVED0 0x01 +#define V_009910_ADDR_SURF_P2_RESERVED1 0x02 +#define V_009910_ADDR_SURF_P2_RESERVED2 0x03 +#define V_009910_X_ADDR_SURF_P4_8X16 0x04 +#define V_009910_X_ADDR_SURF_P4_16X16 0x05 +#define V_009910_X_ADDR_SURF_P4_16X32 0x06 +#define V_009910_X_ADDR_SURF_P4_32X32 0x07 +#define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08 +#define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09 +#define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A +#define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B +#define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C +#define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D +#define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E +#define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11) +#define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07) +#define C_009910_TILE_SPLIT 0xFFFFC7FF +#define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00 +#define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01 +#define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02 +#define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03 +#define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04 +#define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05 +#define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06 +#define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14) +#define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03) +#define C_009910_BANK_WIDTH 0xFFFF3FFF +#define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00 +#define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01 +#define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02 +#define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03 +#define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16) +#define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03) +#define C_009910_BANK_HEIGHT 0xFFFCFFFF +#define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00 +#define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01 +#define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02 +#define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03 +#define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18) +#define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03) +#define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF +#define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00 +#define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01 +#define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02 +#define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03 +#define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20) +#define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03) +#define C_009910_NUM_BANKS 0xFFCFFFFF +#define V_009910_ADDR_SURF_2_BANK 0x00 +#define V_009910_ADDR_SURF_4_BANK 0x01 +#define V_009910_ADDR_SURF_8_BANK 0x02 +#define V_009910_ADDR_SURF_16_BANK 0x03 +#define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020 +#define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024 +#define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B024_MEM_BASE 0xFFFFFF00 +#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 +#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B028_VGPRS 0xFFFFFFC0 +#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B028_SGPRS 0xFFFFFC3F +#define S_00B028_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B028_PRIORITY 0xFFFFF3FF +#define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B028_FLOAT_MODE 0xFFF00FFF +#define S_00B028_PRIV(x) (((x) & 0x1) << 20) +#define G_00B028_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B028_PRIV 0xFFEFFFFF +#define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B028_DX10_CLAMP 0xFFDFFFFF +#define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B028_DEBUG_MODE 0xFFBFFFFF +#define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B028_IEEE_MODE 0xFF7FFFFF +#define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24) +#define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1) +#define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF +#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C +#define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B02C_SCRATCH_EN 0xFFFFFFFE +#define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B02C_USER_SGPR 0xFFFFFFC1 +#define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7) +#define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1) +#define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F +#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) +#define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF) +#define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF +#define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) +#define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) +#define C_00B02C_EXCP_EN 0xFF80FFFF +#define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030 +#define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034 +#define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038 +#define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C +#define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040 +#define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044 +#define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048 +#define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C +#define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050 +#define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054 +#define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058 +#define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C +#define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060 +#define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064 +#define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068 +#define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C +#define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120 +#define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124 +#define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B124_MEM_BASE 0xFFFFFF00 +#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 +#define S_00B128_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B128_VGPRS 0xFFFFFFC0 +#define S_00B128_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B128_SGPRS 0xFFFFFC3F +#define S_00B128_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B128_PRIORITY 0xFFFFF3FF +#define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B128_FLOAT_MODE 0xFFF00FFF +#define S_00B128_PRIV(x) (((x) & 0x1) << 20) +#define G_00B128_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B128_PRIV 0xFFEFFFFF +#define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B128_DX10_CLAMP 0xFFDFFFFF +#define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B128_DEBUG_MODE 0xFFBFFFFF +#define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B128_IEEE_MODE 0xFF7FFFFF +#define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) +#define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) +#define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF +#define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) +#define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) +#define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF +#define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C +#define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B12C_SCRATCH_EN 0xFFFFFFFE +#define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B12C_USER_SGPR 0xFFFFFFC1 +#define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7) +#define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1) +#define C_00B12C_OC_LDS_EN 0xFFFFFF7F +#define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8) +#define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1) +#define C_00B12C_SO_BASE0_EN 0xFFFFFEFF +#define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9) +#define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1) +#define C_00B12C_SO_BASE1_EN 0xFFFFFDFF +#define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10) +#define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1) +#define C_00B12C_SO_BASE2_EN 0xFFFFFBFF +#define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11) +#define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1) +#define C_00B12C_SO_BASE3_EN 0xFFFFF7FF +#define S_00B12C_SO_EN(x) (((x) & 0x1) << 12) +#define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1) +#define C_00B12C_SO_EN 0xFFFFEFFF +#define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) +#define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) +#define C_00B12C_EXCP_EN 0xFFF01FFF +#define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130 +#define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134 +#define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138 +#define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C +#define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140 +#define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144 +#define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148 +#define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C +#define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150 +#define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154 +#define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158 +#define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C +#define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160 +#define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164 +#define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168 +#define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C +#define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220 +#define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224 +#define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B224_MEM_BASE 0xFFFFFF00 +#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 +#define S_00B228_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B228_VGPRS 0xFFFFFFC0 +#define S_00B228_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B228_SGPRS 0xFFFFFC3F +#define S_00B228_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B228_PRIORITY 0xFFFFF3FF +#define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B228_FLOAT_MODE 0xFFF00FFF +#define S_00B228_PRIV(x) (((x) & 0x1) << 20) +#define G_00B228_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B228_PRIV 0xFFEFFFFF +#define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B228_DX10_CLAMP 0xFFDFFFFF +#define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B228_DEBUG_MODE 0xFFBFFFFF +#define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B228_IEEE_MODE 0xFF7FFFFF +#define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24) +#define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1) +#define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF +#define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C +#define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B22C_SCRATCH_EN 0xFFFFFFFE +#define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B22C_USER_SGPR 0xFFFFFFC1 +#define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) +#define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) +#define C_00B22C_EXCP_EN 0xFFFFC07F +#define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230 +#define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320 +#define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324 +#define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B324_MEM_BASE 0xFFFFFF00 +#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 +#define S_00B328_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B328_VGPRS 0xFFFFFFC0 +#define S_00B328_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B328_SGPRS 0xFFFFFC3F +#define S_00B328_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B328_PRIORITY 0xFFFFF3FF +#define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B328_FLOAT_MODE 0xFFF00FFF +#define S_00B328_PRIV(x) (((x) & 0x1) << 20) +#define G_00B328_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B328_PRIV 0xFFEFFFFF +#define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B328_DX10_CLAMP 0xFFDFFFFF +#define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B328_DEBUG_MODE 0xFFBFFFFF +#define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B328_IEEE_MODE 0xFF7FFFFF +#define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) +#define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) +#define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF +#define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) +#define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) +#define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF +#define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C +#define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B32C_SCRATCH_EN 0xFFFFFFFE +#define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B32C_USER_SGPR 0xFFFFFFC1 +#define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7) +#define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1) +#define C_00B32C_OC_LDS_EN 0xFFFFFF7F +#define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) +#define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) +#define C_00B32C_EXCP_EN 0xFFFF80FF +#define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330 +#define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420 +#define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424 +#define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B424_MEM_BASE 0xFFFFFF00 +#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 +#define S_00B428_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B428_VGPRS 0xFFFFFFC0 +#define S_00B428_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B428_SGPRS 0xFFFFFC3F +#define S_00B428_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B428_PRIORITY 0xFFFFF3FF +#define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B428_FLOAT_MODE 0xFFF00FFF +#define S_00B428_PRIV(x) (((x) & 0x1) << 20) +#define G_00B428_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B428_PRIV 0xFFEFFFFF +#define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B428_DX10_CLAMP 0xFFDFFFFF +#define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B428_DEBUG_MODE 0xFFBFFFFF +#define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B428_IEEE_MODE 0xFF7FFFFF +#define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C +#define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B42C_SCRATCH_EN 0xFFFFFFFE +#define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B42C_USER_SGPR 0xFFFFFFC1 +#define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7) +#define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1) +#define C_00B42C_OC_LDS_EN 0xFFFFFF7F +#define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8) +#define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1) +#define C_00B42C_TG_SIZE_EN 0xFFFFFEFF +#define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) +#define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) +#define C_00B42C_EXCP_EN 0xFFFF01FF +#define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430 +#define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520 +#define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524 +#define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0) +#define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF) +#define C_00B524_MEM_BASE 0xFFFFFF00 +#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 +#define S_00B528_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B528_VGPRS 0xFFFFFFC0 +#define S_00B528_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B528_SGPRS 0xFFFFFC3F +#define S_00B528_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B528_PRIORITY 0xFFFFF3FF +#define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B528_FLOAT_MODE 0xFFF00FFF +#define S_00B528_PRIV(x) (((x) & 0x1) << 20) +#define G_00B528_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B528_PRIV 0xFFEFFFFF +#define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B528_DX10_CLAMP 0xFFDFFFFF +#define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B528_DEBUG_MODE 0xFFBFFFFF +#define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B528_IEEE_MODE 0xFF7FFFFF +#define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) +#define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) +#define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF +#define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C +#define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B52C_SCRATCH_EN 0xFFFFFFFE +#define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B52C_USER_SGPR 0xFFFFFFC1 +#define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7) +#define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF) +#define C_00B52C_LDS_SIZE 0xFFFF007F +#define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) +#define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) +#define C_00B52C_EXCP_EN 0xFF80FFFF +#define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530 +#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 +#define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0) +#define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1) +#define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE +#define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1) +#define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1) +#define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD +#define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2) +#define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1) +#define C_00B800_FORCE_START_AT_000 0xFFFFFFFB +#define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3) +#define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1) +#define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7 +#define R_00B804_COMPUTE_DIM_X 0x00B804 +#define R_00B808_COMPUTE_DIM_Y 0x00B808 +#define R_00B80C_COMPUTE_DIM_Z 0x00B80C +#define R_00B810_COMPUTE_START_X 0x00B810 +#define R_00B814_COMPUTE_START_Y 0x00B814 +#define R_00B818_COMPUTE_START_Z 0x00B818 +#define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C +#define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) +#define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) +#define C_00B81C_NUM_THREAD_FULL 0xFFFF0000 +#define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) +#define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) +#define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF +#define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820 +#define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) +#define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) +#define C_00B820_NUM_THREAD_FULL 0xFFFF0000 +#define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) +#define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) +#define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF +#define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824 +#define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) +#define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) +#define C_00B824_NUM_THREAD_FULL 0xFFFF0000 +#define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) +#define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) +#define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF +#define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C +#define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) +#define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) +#define C_00B82C_MAX_WAVE_ID 0xFFFFF000 +#define R_00B830_COMPUTE_PGM_LO 0x00B830 +#define R_00B834_COMPUTE_PGM_HI 0x00B834 +#define S_00B834_DATA(x) (((x) & 0xFF) << 0) +#define G_00B834_DATA(x) (((x) >> 0) & 0xFF) +#define C_00B834_DATA 0xFFFFFF00 +#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 +#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) +#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) +#define C_00B848_VGPRS 0xFFFFFFC0 +#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) +#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) +#define C_00B848_SGPRS 0xFFFFFC3F +#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) +#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) +#define C_00B848_PRIORITY 0xFFFFF3FF +#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) +#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) +#define C_00B848_FLOAT_MODE 0xFFF00FFF +#define S_00B848_PRIV(x) (((x) & 0x1) << 20) +#define G_00B848_PRIV(x) (((x) >> 20) & 0x1) +#define C_00B848_PRIV 0xFFEFFFFF +#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_00B848_DX10_CLAMP 0xFFDFFFFF +#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) +#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) +#define C_00B848_DEBUG_MODE 0xFFBFFFFF +#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) +#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) +#define C_00B848_IEEE_MODE 0xFF7FFFFF +#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C +#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) +#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) +#define C_00B84C_SCRATCH_EN 0xFFFFFFFE +#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) +#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) +#define C_00B84C_USER_SGPR 0xFFFFFFC1 +#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) +#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) +#define C_00B84C_TGID_X_EN 0xFFFFFF7F +#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) +#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) +#define C_00B84C_TGID_Y_EN 0xFFFFFEFF +#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) +#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) +#define C_00B84C_TGID_Z_EN 0xFFFFFDFF +#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) +#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) +#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF +#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) +#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) +#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF +#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) +#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) +#define C_00B84C_LDS_SIZE 0xFF007FFF +#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) +#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) +#define C_00B84C_EXCP_EN 0x80FFFFFF +#define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854 +#define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) +#define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) +#define C_00B854_WAVES_PER_SH 0xFFFFFFC0 +#define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12) +#define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F) +#define C_00B854_TG_PER_CU 0xFFFF0FFF +#define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16) +#define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F) +#define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF +#define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22) +#define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1) +#define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF +#define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858 +#define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) +#define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) +#define C_00B858_SH0_CU_EN 0xFFFF0000 +#define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) +#define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) +#define C_00B858_SH1_CU_EN 0x0000FFFF +#define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C +#define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) +#define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) +#define C_00B85C_SH0_CU_EN 0xFFFF0000 +#define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) +#define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) +#define C_00B85C_SH1_CU_EN 0x0000FFFF +#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 +#define S_00B860_WAVES(x) (((x) & 0xFFF) << 0) +#define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF) +#define C_00B860_WAVES 0xFFFFF000 +#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) +#define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF) +#define C_00B860_WAVESIZE 0xFE000FFF +#define R_00B900_COMPUTE_USER_DATA_0 0x00B900 +#define R_028000_DB_RENDER_CONTROL 0x028000 +#define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) +#define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE +#define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) +#define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD +#define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2) +#define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1) +#define C_028000_DEPTH_COPY 0xFFFFFFFB +#define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3) +#define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1) +#define C_028000_STENCIL_COPY 0xFFFFFFF7 +#define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) +#define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1) +#define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF +#define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) +#define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1) +#define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF +#define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) +#define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1) +#define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF +#define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7) +#define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1) +#define C_028000_COPY_CENTROID 0xFFFFFF7F +#define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8) +#define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F) +#define C_028000_COPY_SAMPLE 0xFFFFF0FF +#define R_028004_DB_COUNT_CONTROL 0x028004 +#define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0) +#define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1) +#define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE +#define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1) +#define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1) +#define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD +#define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4) +#define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07) +#define C_028004_SAMPLE_RATE 0xFFFFFF8F +#define R_028008_DB_DEPTH_VIEW 0x028008 +#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028008_SLICE_START 0xFFFFF800 +#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028008_SLICE_MAX 0xFF001FFF +#define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24) +#define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1) +#define C_028008_Z_READ_ONLY 0xFEFFFFFF +#define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25) +#define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1) +#define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF +#define R_02800C_DB_RENDER_OVERRIDE 0x02800C +#define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0) +#define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03) +#define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC +#define V_02800C_FORCE_OFF 0x00 +#define V_02800C_FORCE_ENABLE 0x01 +#define V_02800C_FORCE_DISABLE 0x02 +#define V_02800C_FORCE_RESERVED 0x03 +#define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2) +#define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03) +#define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3 +#define V_02800C_FORCE_OFF 0x00 +#define V_02800C_FORCE_ENABLE 0x01 +#define V_02800C_FORCE_DISABLE 0x02 +#define V_02800C_FORCE_RESERVED 0x03 +#define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4) +#define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03) +#define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF +#define V_02800C_FORCE_OFF 0x00 +#define V_02800C_FORCE_ENABLE 0x01 +#define V_02800C_FORCE_DISABLE 0x02 +#define V_02800C_FORCE_RESERVED 0x03 +#define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) +#define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) +#define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF +#define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) +#define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) +#define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F +#define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) +#define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) +#define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF +#define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) +#define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) +#define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF +#define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) +#define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) +#define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF +#define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11) +#define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1) +#define C_02800C_FORCE_Z_READ 0xFFFFF7FF +#define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) +#define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) +#define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF +#define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13) +#define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03) +#define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF +#define V_02800C_FORCE_OFF 0x00 +#define V_02800C_FORCE_ENABLE 0x01 +#define V_02800C_FORCE_DISABLE 0x02 +#define V_02800C_FORCE_RESERVED 0x03 +#define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) +#define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) +#define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF +#define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) +#define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) +#define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF +#define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) +#define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) +#define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18) +#define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1) +#define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF +#define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19) +#define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03) +#define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF +#define V_02800C_FORCE_SUMM_OFF 0x00 +#define V_02800C_FORCE_SUMM_MINZ 0x01 +#define V_02800C_FORCE_SUMM_MAXZ 0x02 +#define V_02800C_FORCE_SUMM_BOTH 0x03 +#define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) +#define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) +#define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF +#define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26) +#define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1) +#define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF +#define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27) +#define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1) +#define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF +#define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28) +#define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1) +#define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF +#define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29) +#define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1) +#define C_02800C_FORCE_Z_VALID 0xDFFFFFFF +#define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30) +#define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1) +#define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF +#define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31) +#define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1) +#define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF +#define R_028010_DB_RENDER_OVERRIDE2 0x028010 +#define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0) +#define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03) +#define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC +#define V_028010_PSLC_AUTO 0x00 +#define V_028010_PSLC_ON_HANG_ONLY 0x01 +#define V_028010_PSLC_ASAP 0x02 +#define V_028010_PSLC_COUNTDOWN 0x03 +#define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2) +#define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07) +#define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3 +#define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) & 0x1) << 5) +#define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO(x) (((x) >> 5) & 0x1) +#define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO 0xFFFFFFDF +#define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6) +#define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1) +#define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF +#define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7) +#define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1) +#define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F +#define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8) +#define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1) +#define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF +#define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9) +#define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1) +#define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF +#define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10) +#define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1) +#define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF +#define R_028014_DB_HTILE_DATA_BASE 0x028014 +#define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020 +#define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024 +#define R_028028_DB_STENCIL_CLEAR 0x028028 +#define S_028028_CLEAR(x) (((x) & 0xFF) << 0) +#define G_028028_CLEAR(x) (((x) >> 0) & 0xFF) +#define C_028028_CLEAR 0xFFFFFF00 +#define R_02802C_DB_DEPTH_CLEAR 0x02802C +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0xFFFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF) +#define C_028030_TL_X 0xFFFF0000 +#define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF) +#define C_028030_TL_Y 0x0000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0xFFFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF) +#define C_028034_BR_X 0xFFFF0000 +#define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF) +#define C_028034_BR_Y 0x0000FFFF +#define R_02803C_DB_DEPTH_INFO 0x02803C +#define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0) +#define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F) +#define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0 +#define R_028040_DB_Z_INFO 0x028040 +#define S_028040_FORMAT(x) (((x) & 0x03) << 0) +#define G_028040_FORMAT(x) (((x) >> 0) & 0x03) +#define C_028040_FORMAT 0xFFFFFFFC +#define V_028040_Z_INVALID 0x00 +#define V_028040_Z_16 0x01 +#define V_028040_Z_24 0x02 /* deprecated */ +#define V_028040_Z_32_FLOAT 0x03 +#define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2) +#define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03) +#define C_028040_NUM_SAMPLES 0xFFFFFFF3 +#define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) +#define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) +#define C_028040_TILE_MODE_INDEX 0xFF8FFFFF +#define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) +#define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) +#define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF +#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) +#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) +#define C_028040_READ_SIZE 0xEFFFFFFF +#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) +#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) +#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF +#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028044_DB_STENCIL_INFO 0x028044 +#define S_028044_FORMAT(x) (((x) & 0x1) << 0) +#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) +#define C_028044_FORMAT 0xFFFFFFFE +#define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) +#define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) +#define C_028044_TILE_MODE_INDEX 0xFF8FFFFF +#define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) +#define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) +#define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF +#define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29) +#define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1) +#define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF +#define R_028048_DB_Z_READ_BASE 0x028048 +#define R_02804C_DB_STENCIL_READ_BASE 0x02804C +#define R_028050_DB_Z_WRITE_BASE 0x028050 +#define R_028054_DB_STENCIL_WRITE_BASE 0x028054 +#define R_028058_DB_DEPTH_SIZE 0x028058 +#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) +#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) +#define C_028058_PITCH_TILE_MAX 0xFFFFF800 +#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) +#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) +#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF +#define R_02805C_DB_DEPTH_SLICE 0x02805C +#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) +#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) +#define C_02805C_SLICE_TILE_MAX 0xFFC00000 +#define R_028080_TA_BC_BASE_ADDR 0x028080 +#define R_028200_PA_SC_WINDOW_OFFSET 0x028200 +#define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_028200_WINDOW_X_OFFSET 0xFFFF0000 +#define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16) +#define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF) +#define C_028200_WINDOW_Y_OFFSET 0x0000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028204_TL_X 0xFFFF8000 +#define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028204_TL_Y 0x8000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028208_BR_X 0xFFFF8000 +#define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028208_BR_Y 0x8000FFFF +#define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C +#define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) +#define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) +#define C_02820C_CLIP_RULE 0xFFFF0000 +#define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 +#define S_028210_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028210_TL_X 0xFFFF8000 +#define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028210_TL_Y 0x8000FFFF +#define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 +#define S_028214_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028214_BR_X 0xFFFF8000 +#define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028214_BR_Y 0x8000FFFF +#define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 +#define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C +#define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 +#define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 +#define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 +#define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C +#define R_028230_PA_SC_EDGERULE 0x028230 +#define S_028230_ER_TRI(x) (((x) & 0x0F) << 0) +#define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F) +#define C_028230_ER_TRI 0xFFFFFFF0 +#define S_028230_ER_POINT(x) (((x) & 0x0F) << 4) +#define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F) +#define C_028230_ER_POINT 0xFFFFFF0F +#define S_028230_ER_RECT(x) (((x) & 0x0F) << 8) +#define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F) +#define C_028230_ER_RECT 0xFFFFF0FF +#define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12) +#define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F) +#define C_028230_ER_LINE_LR 0xFFFC0FFF +#define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18) +#define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F) +#define C_028230_ER_LINE_RL 0xFF03FFFF +#define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24) +#define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F) +#define C_028230_ER_LINE_TB 0xF0FFFFFF +#define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28) +#define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F) +#define C_028230_ER_LINE_BT 0x0FFFFFFF +#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234 +#define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0) +#define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF) +#define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00 +#define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16) +#define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF) +#define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF +#define R_028238_CB_TARGET_MASK 0x028238 +#define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0) +#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F) +#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 +#define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4) +#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F) +#define C_028238_TARGET1_ENABLE 0xFFFFFF0F +#define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8) +#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F) +#define C_028238_TARGET2_ENABLE 0xFFFFF0FF +#define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12) +#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F) +#define C_028238_TARGET3_ENABLE 0xFFFF0FFF +#define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16) +#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F) +#define C_028238_TARGET4_ENABLE 0xFFF0FFFF +#define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20) +#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F) +#define C_028238_TARGET5_ENABLE 0xFF0FFFFF +#define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24) +#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F) +#define C_028238_TARGET6_ENABLE 0xF0FFFFFF +#define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28) +#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F) +#define C_028238_TARGET7_ENABLE 0x0FFFFFFF +#define R_02823C_CB_SHADER_MASK 0x02823C +#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0) +#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F) +#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 +#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4) +#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F) +#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F +#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8) +#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F) +#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF +#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12) +#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F) +#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF +#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16) +#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F) +#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF +#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20) +#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F) +#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF +#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24) +#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F) +#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF +#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28) +#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F) +#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028240_TL_X 0xFFFF8000 +#define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028240_TL_Y 0x8000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028244_BR_X 0xFFFF8000 +#define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028244_BR_Y 0x8000FFFF +#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 +#define S_028250_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028250_TL_X 0xFFFF8000 +#define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028250_TL_Y 0x8000FFFF +#define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 +#define S_028254_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028254_BR_X 0xFFFF8000 +#define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028254_BR_Y 0x8000FFFF +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 +#define R_028350_PA_SC_RASTER_CONFIG 0x028350 +#define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0) +#define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03) +#define C_028350_RB_MAP_PKR0 0xFFFFFFFC +#define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 +#define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 +#define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 +#define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 +#define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2) +#define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03) +#define C_028350_RB_MAP_PKR1 0xFFFFFFF3 +#define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 +#define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 +#define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 +#define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 +#define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4) +#define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03) +#define C_028350_RB_XSEL2 0xFFFFFFCF +#define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00 +#define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01 +#define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02 +#define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03 +#define S_028350_RB_XSEL(x) (((x) & 0x1) << 6) +#define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1) +#define C_028350_RB_XSEL 0xFFFFFFBF +#define S_028350_RB_YSEL(x) (((x) & 0x1) << 7) +#define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1) +#define C_028350_RB_YSEL 0xFFFFFF7F +#define S_028350_PKR_MAP(x) (((x) & 0x03) << 8) +#define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03) +#define C_028350_PKR_MAP 0xFFFFFCFF +#define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00 +#define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01 +#define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02 +#define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03 +#define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10) +#define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03) +#define C_028350_PKR_XSEL 0xFFFFF3FF +#define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00 +#define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01 +#define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02 +#define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03 +#define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12) +#define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03) +#define C_028350_PKR_YSEL 0xFFFFCFFF +#define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00 +#define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01 +#define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02 +#define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03 +#define S_028350_SC_MAP(x) (((x) & 0x03) << 16) +#define G_028350_SC_MAP(x) (((x) >> 16) & 0x03) +#define C_028350_SC_MAP 0xFFFCFFFF +#define V_028350_RASTER_CONFIG_SC_MAP_0 0x00 +#define V_028350_RASTER_CONFIG_SC_MAP_1 0x01 +#define V_028350_RASTER_CONFIG_SC_MAP_2 0x02 +#define V_028350_RASTER_CONFIG_SC_MAP_3 0x03 +#define S_028350_SC_XSEL(x) (((x) & 0x03) << 18) +#define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03) +#define C_028350_SC_XSEL 0xFFF3FFFF +#define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00 +#define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01 +#define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02 +#define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03 +#define S_028350_SC_YSEL(x) (((x) & 0x03) << 20) +#define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03) +#define C_028350_SC_YSEL 0xFFCFFFFF +#define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00 +#define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01 +#define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02 +#define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03 +#define S_028350_SE_MAP(x) (((x) & 0x03) << 24) +#define G_028350_SE_MAP(x) (((x) >> 24) & 0x03) +#define C_028350_SE_MAP 0xFCFFFFFF +#define V_028350_RASTER_CONFIG_SE_MAP_0 0x00 +#define V_028350_RASTER_CONFIG_SE_MAP_1 0x01 +#define V_028350_RASTER_CONFIG_SE_MAP_2 0x02 +#define V_028350_RASTER_CONFIG_SE_MAP_3 0x03 +#define S_028350_SE_XSEL(x) (((x) & 0x03) << 26) +#define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03) +#define C_028350_SE_XSEL 0xF3FFFFFF +#define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00 +#define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01 +#define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02 +#define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03 +#define S_028350_SE_YSEL(x) (((x) & 0x03) << 28) +#define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03) +#define C_028350_SE_YSEL 0xCFFFFFFF +#define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00 +#define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01 +#define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02 +#define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03 +#define R_028400_VGT_MAX_VTX_INDX 0x028400 +#define R_028404_VGT_MIN_VTX_INDX 0x028404 +#define R_028408_VGT_INDX_OFFSET 0x028408 +#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C +#define R_028414_CB_BLEND_RED 0x028414 +#define R_028418_CB_BLEND_GREEN 0x028418 +#define R_02841C_CB_BLEND_BLUE 0x02841C +#define R_028420_CB_BLEND_ALPHA 0x028420 +#define R_02842C_DB_STENCIL_CONTROL 0x02842C +#define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0) +#define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F) +#define C_02842C_STENCILFAIL 0xFFFFFFF0 +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4) +#define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F) +#define C_02842C_STENCILZPASS 0xFFFFFF0F +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8) +#define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F) +#define C_02842C_STENCILZFAIL 0xFFFFF0FF +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12) +#define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F) +#define C_02842C_STENCILFAIL_BF 0xFFFF0FFF +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16) +#define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F) +#define C_02842C_STENCILZPASS_BF 0xFFF0FFFF +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20) +#define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F) +#define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF +#define V_02842C_STENCIL_KEEP 0x00 +#define V_02842C_STENCIL_ZERO 0x01 +#define V_02842C_STENCIL_ONES 0x02 +#define V_02842C_STENCIL_REPLACE_TEST 0x03 +#define V_02842C_STENCIL_REPLACE_OP 0x04 +#define V_02842C_STENCIL_ADD_CLAMP 0x05 +#define V_02842C_STENCIL_SUB_CLAMP 0x06 +#define V_02842C_STENCIL_INVERT 0x07 +#define V_02842C_STENCIL_ADD_WRAP 0x08 +#define V_02842C_STENCIL_SUB_WRAP 0x09 +#define V_02842C_STENCIL_AND 0x0A +#define V_02842C_STENCIL_OR 0x0B +#define V_02842C_STENCIL_XOR 0x0C +#define V_02842C_STENCIL_NAND 0x0D +#define V_02842C_STENCIL_NOR 0x0E +#define V_02842C_STENCIL_XNOR 0x0F +#define R_028430_DB_STENCILREFMASK 0x028430 +#define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0) +#define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF) +#define C_028430_STENCILTESTVAL 0xFFFFFF00 +#define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8) +#define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF) +#define C_028430_STENCILMASK 0xFFFF00FF +#define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16) +#define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF) +#define C_028430_STENCILWRITEMASK 0xFF00FFFF +#define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24) +#define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF) +#define C_028430_STENCILOPVAL 0x00FFFFFF +#define R_028434_DB_STENCILREFMASK_BF 0x028434 +#define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0) +#define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF) +#define C_028434_STENCILTESTVAL_BF 0xFFFFFF00 +#define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8) +#define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF) +#define C_028434_STENCILMASK_BF 0xFFFF00FF +#define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16) +#define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF) +#define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF +#define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24) +#define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF) +#define C_028434_STENCILOPVAL_BF 0x00FFFFFF +#define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C +#define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440 +#define R_028444_PA_CL_VPORT_YSCALE_0 0x028444 +#define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448 +#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C +#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450 +#define R_0285BC_PA_CL_UCP_0_X 0x0285BC +#define R_0285C0_PA_CL_UCP_0_Y 0x0285C0 +#define R_0285C4_PA_CL_UCP_0_Z 0x0285C4 +#define R_0285C8_PA_CL_UCP_0_W 0x0285C8 +#define R_0285CC_PA_CL_UCP_1_X 0x0285CC +#define R_0285D0_PA_CL_UCP_1_Y 0x0285D0 +#define R_0285D4_PA_CL_UCP_1_Z 0x0285D4 +#define R_0285D8_PA_CL_UCP_1_W 0x0285D8 +#define R_0285DC_PA_CL_UCP_2_X 0x0285DC +#define R_0285E0_PA_CL_UCP_2_Y 0x0285E0 +#define R_0285E4_PA_CL_UCP_2_Z 0x0285E4 +#define R_0285E8_PA_CL_UCP_2_W 0x0285E8 +#define R_0285EC_PA_CL_UCP_3_X 0x0285EC +#define R_0285F0_PA_CL_UCP_3_Y 0x0285F0 +#define R_0285F4_PA_CL_UCP_3_Z 0x0285F4 +#define R_0285F8_PA_CL_UCP_3_W 0x0285F8 +#define R_0285FC_PA_CL_UCP_4_X 0x0285FC +#define R_028600_PA_CL_UCP_4_Y 0x028600 +#define R_028604_PA_CL_UCP_4_Z 0x028604 +#define R_028608_PA_CL_UCP_4_W 0x028608 +#define R_02860C_PA_CL_UCP_5_X 0x02860C +#define R_028610_PA_CL_UCP_5_Y 0x028610 +#define R_028614_PA_CL_UCP_5_Z 0x028614 +#define R_028618_PA_CL_UCP_5_W 0x028618 +#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 +#define S_028644_OFFSET(x) (((x) & 0x3F) << 0) +#define G_028644_OFFSET(x) (((x) >> 0) & 0x3F) +#define C_028644_OFFSET 0xFFFFFFC0 +#define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8) +#define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03) +#define C_028644_DEFAULT_VAL 0xFFFFFCFF +#define V_028644_X_0_0F 0x00 +#define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) +#define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) +#define C_028644_FLAT_SHADE 0xFFFFFBFF +#define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13) +#define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F) +#define C_028644_CYL_WRAP 0xFFFE1FFF +#define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) +#define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) +#define C_028644_PT_SPRITE_TEX 0xFFFDFFFF +#define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 +#define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C +#define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 +#define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 +#define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 +#define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C +#define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 +#define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 +#define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 +#define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C +#define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 +#define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 +#define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 +#define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C +#define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 +#define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 +#define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 +#define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C +#define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 +#define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 +#define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 +#define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C +#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 +#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 +#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 +#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC +#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 +#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 +#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 +#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC +#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 +#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 +#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) +#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) +#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 +#define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6) +#define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1) +#define C_0286C4_VS_HALF_PACK 0xFFFFFFBF +#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) +#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) +#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F +#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) +#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) +#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF +#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC +#define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) +#define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) +#define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE +#define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) +#define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) +#define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD +#define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) +#define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) +#define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB +#define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) +#define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) +#define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 +#define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) +#define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) +#define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF +#define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) +#define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) +#define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF +#define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) +#define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) +#define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF +#define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) +#define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) +#define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F +#define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) +#define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) +#define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF +#define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) +#define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) +#define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF +#define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) +#define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) +#define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF +#define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) +#define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) +#define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF +#define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) +#define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) +#define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF +#define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13) +#define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) +#define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF +#define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) +#define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) +#define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF +#define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) +#define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) +#define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF +#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 +#define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) +#define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) +#define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE +#define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) +#define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) +#define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD +#define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) +#define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) +#define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB +#define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) +#define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) +#define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 +#define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) +#define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) +#define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF +#define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) +#define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) +#define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF +#define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) +#define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) +#define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF +#define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) +#define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) +#define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F +#define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) +#define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) +#define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF +#define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) +#define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) +#define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF +#define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) +#define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) +#define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF +#define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) +#define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) +#define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF +#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) +#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) +#define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF +#define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13) +#define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) +#define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF +#define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) +#define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) +#define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF +#define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) +#define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) +#define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF +#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 +#define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) +#define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) +#define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE +#define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) +#define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) +#define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD +#define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2) +#define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07) +#define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 +#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 +#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 +#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 +#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 +#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 +#define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5) +#define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07) +#define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F +#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 +#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 +#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 +#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 +#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 +#define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8) +#define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07) +#define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF +#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 +#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 +#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 +#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 +#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 +#define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11) +#define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07) +#define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF +#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 +#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 +#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 +#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 +#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 +#define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) +#define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) +#define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF +#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 +#define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0) +#define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F) +#define C_0286D8_NUM_INTERP 0xFFFFFFC0 +#define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6) +#define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1) +#define C_0286D8_PARAM_GEN 0xFFFFFFBF +#define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) +#define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) +#define C_0286D8_FOG_ADDR 0xFFFFC07F +#define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14) +#define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1) +#define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF +#define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) +#define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) +#define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF +#define R_0286E0_SPI_BARYC_CNTL 0x0286E0 +#define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0) +#define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1) +#define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE +#define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4) +#define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1) +#define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF +#define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8) +#define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1) +#define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF +#define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12) +#define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1) +#define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF +#define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16) +#define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03) +#define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF +#define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00 +#define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20) +#define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1) +#define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF +#define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24) +#define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1) +#define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF +#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 +#define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0) +#define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF) +#define C_0286E8_WAVES 0xFFFFF000 +#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) +#define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF) +#define C_0286E8_WAVESIZE 0xFE000FFF +#define R_028704_SPI_WAVE_MGMT_1 0x028704 +#define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0) +#define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F) +#define C_028704_NUM_PS_WAVES 0xFFFFFFC0 +#define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6) +#define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F) +#define C_028704_NUM_VS_WAVES 0xFFFFF03F +#define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12) +#define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F) +#define C_028704_NUM_GS_WAVES 0xFFFC0FFF +#define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18) +#define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F) +#define C_028704_NUM_ES_WAVES 0xFF03FFFF +#define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24) +#define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F) +#define C_028704_NUM_HS_WAVES 0xC0FFFFFF +#define R_028708_SPI_WAVE_MGMT_2 0x028708 +#define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0) +#define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F) +#define C_028708_NUM_LS_WAVES 0xFFFFFFC0 +#define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C +#define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) +#define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) +#define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0 +#define V_02870C_SPI_SHADER_NONE 0x00 +#define V_02870C_SPI_SHADER_1COMP 0x01 +#define V_02870C_SPI_SHADER_2COMP 0x02 +#define V_02870C_SPI_SHADER_4COMPRESS 0x03 +#define V_02870C_SPI_SHADER_4COMP 0x04 +#define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) +#define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) +#define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F +#define V_02870C_SPI_SHADER_NONE 0x00 +#define V_02870C_SPI_SHADER_1COMP 0x01 +#define V_02870C_SPI_SHADER_2COMP 0x02 +#define V_02870C_SPI_SHADER_4COMPRESS 0x03 +#define V_02870C_SPI_SHADER_4COMP 0x04 +#define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) +#define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) +#define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF +#define V_02870C_SPI_SHADER_NONE 0x00 +#define V_02870C_SPI_SHADER_1COMP 0x01 +#define V_02870C_SPI_SHADER_2COMP 0x02 +#define V_02870C_SPI_SHADER_4COMPRESS 0x03 +#define V_02870C_SPI_SHADER_4COMP 0x04 +#define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) +#define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) +#define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF +#define V_02870C_SPI_SHADER_NONE 0x00 +#define V_02870C_SPI_SHADER_1COMP 0x01 +#define V_02870C_SPI_SHADER_2COMP 0x02 +#define V_02870C_SPI_SHADER_4COMPRESS 0x03 +#define V_02870C_SPI_SHADER_4COMP 0x04 +#define R_028710_SPI_SHADER_Z_FORMAT 0x028710 +#define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) +#define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) +#define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0 +#define V_028710_SPI_SHADER_ZERO 0x00 +#define V_028710_SPI_SHADER_32_R 0x01 +#define V_028710_SPI_SHADER_32_GR 0x02 +#define V_028710_SPI_SHADER_32_AR 0x03 +#define V_028710_SPI_SHADER_FP16_ABGR 0x04 +#define V_028710_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028710_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028710_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028710_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028710_SPI_SHADER_32_ABGR 0x09 +#define R_028714_SPI_SHADER_COL_FORMAT 0x028714 +#define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) +#define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) +#define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0 +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) +#define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) +#define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) +#define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) +#define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) +#define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) +#define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16) +#define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F) +#define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20) +#define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F) +#define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24) +#define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F) +#define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28) +#define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F) +#define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF +#define V_028714_SPI_SHADER_ZERO 0x00 +#define V_028714_SPI_SHADER_32_R 0x01 +#define V_028714_SPI_SHADER_32_GR 0x02 +#define V_028714_SPI_SHADER_32_AR 0x03 +#define V_028714_SPI_SHADER_FP16_ABGR 0x04 +#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 +#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 +#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 +#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 +#define V_028714_SPI_SHADER_32_ABGR 0x09 +#define R_028780_CB_BLEND0_CONTROL 0x028780 +#define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0) +#define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F) +#define C_028780_COLOR_SRCBLEND 0xFFFFFFE0 +#define V_028780_BLEND_ZERO 0x00 +#define V_028780_BLEND_ONE 0x01 +#define V_028780_BLEND_SRC_COLOR 0x02 +#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 +#define V_028780_BLEND_SRC_ALPHA 0x04 +#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 +#define V_028780_BLEND_DST_ALPHA 0x06 +#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 +#define V_028780_BLEND_DST_COLOR 0x08 +#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 +#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A +#define V_028780_BLEND_CONSTANT_COLOR 0x0D +#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E +#define V_028780_BLEND_SRC1_COLOR 0x0F +#define V_028780_BLEND_INV_SRC1_COLOR 0x10 +#define V_028780_BLEND_SRC1_ALPHA 0x11 +#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 +#define V_028780_BLEND_CONSTANT_ALPHA 0x13 +#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 +#define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5) +#define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07) +#define C_028780_COLOR_COMB_FCN 0xFFFFFF1F +#define V_028780_COMB_DST_PLUS_SRC 0x00 +#define V_028780_COMB_SRC_MINUS_DST 0x01 +#define V_028780_COMB_MIN_DST_SRC 0x02 +#define V_028780_COMB_MAX_DST_SRC 0x03 +#define V_028780_COMB_DST_MINUS_SRC 0x04 +#define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8) +#define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F) +#define C_028780_COLOR_DESTBLEND 0xFFFFE0FF +#define V_028780_BLEND_ZERO 0x00 +#define V_028780_BLEND_ONE 0x01 +#define V_028780_BLEND_SRC_COLOR 0x02 +#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 +#define V_028780_BLEND_SRC_ALPHA 0x04 +#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 +#define V_028780_BLEND_DST_ALPHA 0x06 +#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 +#define V_028780_BLEND_DST_COLOR 0x08 +#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 +#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A +#define V_028780_BLEND_CONSTANT_COLOR 0x0D +#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E +#define V_028780_BLEND_SRC1_COLOR 0x0F +#define V_028780_BLEND_INV_SRC1_COLOR 0x10 +#define V_028780_BLEND_SRC1_ALPHA 0x11 +#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 +#define V_028780_BLEND_CONSTANT_ALPHA 0x13 +#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 +#define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16) +#define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F) +#define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF +#define V_028780_BLEND_ZERO 0x00 +#define V_028780_BLEND_ONE 0x01 +#define V_028780_BLEND_SRC_COLOR 0x02 +#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 +#define V_028780_BLEND_SRC_ALPHA 0x04 +#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 +#define V_028780_BLEND_DST_ALPHA 0x06 +#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 +#define V_028780_BLEND_DST_COLOR 0x08 +#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 +#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A +#define V_028780_BLEND_CONSTANT_COLOR 0x0D +#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E +#define V_028780_BLEND_SRC1_COLOR 0x0F +#define V_028780_BLEND_INV_SRC1_COLOR 0x10 +#define V_028780_BLEND_SRC1_ALPHA 0x11 +#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 +#define V_028780_BLEND_CONSTANT_ALPHA 0x13 +#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 +#define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21) +#define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07) +#define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF +#define V_028780_COMB_DST_PLUS_SRC 0x00 +#define V_028780_COMB_SRC_MINUS_DST 0x01 +#define V_028780_COMB_MIN_DST_SRC 0x02 +#define V_028780_COMB_MAX_DST_SRC 0x03 +#define V_028780_COMB_DST_MINUS_SRC 0x04 +#define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24) +#define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F) +#define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF +#define V_028780_BLEND_ZERO 0x00 +#define V_028780_BLEND_ONE 0x01 +#define V_028780_BLEND_SRC_COLOR 0x02 +#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 +#define V_028780_BLEND_SRC_ALPHA 0x04 +#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 +#define V_028780_BLEND_DST_ALPHA 0x06 +#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 +#define V_028780_BLEND_DST_COLOR 0x08 +#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 +#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A +#define V_028780_BLEND_CONSTANT_COLOR 0x0D +#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E +#define V_028780_BLEND_SRC1_COLOR 0x0F +#define V_028780_BLEND_INV_SRC1_COLOR 0x10 +#define V_028780_BLEND_SRC1_ALPHA 0x11 +#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 +#define V_028780_BLEND_CONSTANT_ALPHA 0x13 +#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 +#define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29) +#define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1) +#define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF +#define S_028780_ENABLE(x) (((x) & 0x1) << 30) +#define G_028780_ENABLE(x) (((x) >> 30) & 0x1) +#define C_028780_ENABLE 0xBFFFFFFF +#define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31) +#define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1) +#define C_028780_DISABLE_ROP3 0x7FFFFFFF +#define R_028784_CB_BLEND1_CONTROL 0x028784 +#define R_028788_CB_BLEND2_CONTROL 0x028788 +#define R_02878C_CB_BLEND3_CONTROL 0x02878C +#define R_028790_CB_BLEND4_CONTROL 0x028790 +#define R_028794_CB_BLEND5_CONTROL 0x028794 +#define R_028798_CB_BLEND6_CONTROL 0x028798 +#define R_02879C_CB_BLEND7_CONTROL 0x02879C +#define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4 +#define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8 +#define R_0287DC_PA_CL_POINT_SIZE 0x0287DC +#define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 +#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 +#define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0) +#define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF) +#define C_0287E4_BASE_ADDR 0xFFFFFF00 +#define R_0287E8_VGT_DMA_BASE 0x0287E8 +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0) +#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03) +#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC +#define V_0287F0_DI_SRC_SEL_DMA 0x00 +#define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 +#define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02 +#define V_0287F0_DI_SRC_SEL_RESERVED 0x03 +#define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2) +#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03) +#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 +#define V_0287F0_DI_MAJOR_MODE_0 0x00 +#define V_0287F0_DI_MAJOR_MODE_1 0x01 +#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) +#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) +#define C_0287F0_NOT_EOP 0xFFFFFFDF +#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) +#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) +#define C_0287F0_USE_OPAQUE 0xFFFFFFBF +#define R_0287F4_VGT_IMMED_DATA 0x0287F4 +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3) +#define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7 +#define S_028800_ZFUNC(x) (((x) & 0x07) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x07) +#define C_028800_ZFUNC 0xFFFFFF8F +#define V_028800_FRAG_NEVER 0x00 +#define V_028800_FRAG_LESS 0x01 +#define V_028800_FRAG_EQUAL 0x02 +#define V_028800_FRAG_LEQUAL 0x03 +#define V_028800_FRAG_GREATER 0x04 +#define V_028800_FRAG_NOTEQUAL 0x05 +#define V_028800_FRAG_GEQUAL 0x06 +#define V_028800_FRAG_ALWAYS 0x07 +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define V_028800_REF_NEVER 0x00 +#define V_028800_REF_LESS 0x01 +#define V_028800_REF_EQUAL 0x02 +#define V_028800_REF_LEQUAL 0x03 +#define V_028800_REF_GREATER 0x04 +#define V_028800_REF_NOTEQUAL 0x05 +#define V_028800_REF_GEQUAL 0x06 +#define V_028800_REF_ALWAYS 0x07 +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define V_028800_REF_NEVER 0x00 +#define V_028800_REF_LESS 0x01 +#define V_028800_REF_EQUAL 0x02 +#define V_028800_REF_LEQUAL 0x03 +#define V_028800_REF_GREATER 0x04 +#define V_028800_REF_NOTEQUAL 0x05 +#define V_028800_REF_GEQUAL 0x06 +#define V_028800_REF_ALWAYS 0x07 +#define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30) +#define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1) +#define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF +#define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31) +#define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1) +#define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF +#define R_028804_DB_EQAA 0x028804 +#define R_028808_CB_COLOR_CONTROL 0x028808 +#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) +#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 +#define S_028808_MODE(x) (((x) & 0x07) << 4) +#define G_028808_MODE(x) (((x) >> 4) & 0x07) +#define C_028808_MODE 0xFFFFFF8F +#define V_028808_CB_DISABLE 0x00 +#define V_028808_CB_NORMAL 0x01 +#define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02 +#define V_028808_CB_RESOLVE 0x03 +#define V_028808_CB_FMASK_DECOMPRESS 0x05 +#define S_028808_ROP3(x) (((x) & 0xFF) << 16) +#define G_028808_ROP3(x) (((x) >> 16) & 0xFF) +#define C_028808_ROP3 0xFF00FFFF +#define V_028808_X_0X00 0x00 +#define V_028808_X_0X05 0x05 +#define V_028808_X_0X0A 0x0A +#define V_028808_X_0X0F 0x0F +#define V_028808_X_0X11 0x11 +#define V_028808_X_0X22 0x22 +#define V_028808_X_0X33 0x33 +#define V_028808_X_0X44 0x44 +#define V_028808_X_0X50 0x50 +#define V_028808_X_0X55 0x55 +#define V_028808_X_0X5A 0x5A +#define V_028808_X_0X5F 0x5F +#define V_028808_X_0X66 0x66 +#define V_028808_X_0X77 0x77 +#define V_028808_X_0X88 0x88 +#define V_028808_X_0X99 0x99 +#define V_028808_X_0XA0 0xA0 +#define V_028808_X_0XA5 0xA5 +#define V_028808_X_0XAA 0xAA +#define V_028808_X_0XAF 0xAF +#define V_028808_X_0XBB 0xBB +#define V_028808_X_0XCC 0xCC +#define V_028808_X_0XDD 0xDD +#define V_028808_X_0XEE 0xEE +#define V_028808_X_0XF0 0xF0 +#define V_028808_X_0XF5 0xF5 +#define V_028808_X_0XFA 0xFA +#define V_028808_X_0XFF 0xFF +#define R_02880C_DB_SHADER_CONTROL 0x02880C +#define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) +#define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) +#define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE +#define S_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) & 0x1) << 1) +#define G_02880C_STENCIL_TEST_VAL_EXPORT_ENAB(x) (((x) >> 1) & 0x1) +#define C_02880C_STENCIL_TEST_VAL_EXPORT_ENAB 0xFFFFFFFD +#define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2) +#define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1) +#define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB +#define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4) +#define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03) +#define C_02880C_Z_ORDER 0xFFFFFFCF +#define V_02880C_LATE_Z 0x00 +#define V_02880C_EARLY_Z_THEN_LATE_Z 0x01 +#define V_02880C_RE_Z 0x02 +#define V_02880C_EARLY_Z_THEN_RE_Z 0x03 +#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) +#define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1) +#define C_02880C_KILL_ENABLE 0xFFFFFFBF +#define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7) +#define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1) +#define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F +#define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8) +#define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1) +#define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF +#define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9) +#define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1) +#define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF +#define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10) +#define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1) +#define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF +#define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11) +#define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1) +#define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF +#define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12) +#define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1) +#define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF +#define R_028810_PA_CL_CLIP_CNTL 0x028810 +#define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0) +#define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1) +#define C_028810_UCP_ENA_0 0xFFFFFFFE +#define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1) +#define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1) +#define C_028810_UCP_ENA_1 0xFFFFFFFD +#define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2) +#define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1) +#define C_028810_UCP_ENA_2 0xFFFFFFFB +#define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3) +#define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1) +#define C_028810_UCP_ENA_3 0xFFFFFFF7 +#define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4) +#define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1) +#define C_028810_UCP_ENA_4 0xFFFFFFEF +#define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5) +#define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1) +#define C_028810_UCP_ENA_5 0xFFFFFFDF +#define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13) +#define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1) +#define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF +#define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14) +#define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03) +#define C_028810_PS_UCP_MODE 0xFFFF3FFF +#define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16) +#define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1) +#define C_028810_CLIP_DISABLE 0xFFFEFFFF +#define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17) +#define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1) +#define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF +#define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18) +#define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1) +#define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF +#define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19) +#define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1) +#define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF +#define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20) +#define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1) +#define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF +#define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) +#define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) +#define C_028810_VTX_KILL_OR 0xFFDFFFFF +#define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) +#define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1) +#define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF +#define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) +#define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) +#define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF +#define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25) +#define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1) +#define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF +#define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26) +#define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1) +#define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF +#define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27) +#define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1) +#define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF +#define R_028814_PA_SU_SC_MODE_CNTL 0x028814 +#define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0) +#define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1) +#define C_028814_CULL_FRONT 0xFFFFFFFE +#define S_028814_CULL_BACK(x) (((x) & 0x1) << 1) +#define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1) +#define C_028814_CULL_BACK 0xFFFFFFFD +#define S_028814_FACE(x) (((x) & 0x1) << 2) +#define G_028814_FACE(x) (((x) >> 2) & 0x1) +#define C_028814_FACE 0xFFFFFFFB +#define S_028814_POLY_MODE(x) (((x) & 0x03) << 3) +#define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03) +#define C_028814_POLY_MODE 0xFFFFFFE7 +#define V_028814_X_DISABLE_POLY_MODE 0x00 +#define V_028814_X_DUAL_MODE 0x01 +#define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5) +#define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07) +#define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F +#define V_028814_X_DRAW_POINTS 0x00 +#define V_028814_X_DRAW_LINES 0x01 +#define V_028814_X_DRAW_TRIANGLES 0x02 +#define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8) +#define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07) +#define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF +#define V_028814_X_DRAW_POINTS 0x00 +#define V_028814_X_DRAW_LINES 0x01 +#define V_028814_X_DRAW_TRIANGLES 0x02 +#define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11) +#define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1) +#define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF +#define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12) +#define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1) +#define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF +#define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13) +#define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1) +#define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF +#define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16) +#define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1) +#define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF +#define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19) +#define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1) +#define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF +#define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20) +#define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1) +#define C_028814_PERSP_CORR_DIS 0xFFEFFFFF +#define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21) +#define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1) +#define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF +#define R_028818_PA_CL_VTE_CNTL 0x028818 +#define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0) +#define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1) +#define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE +#define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1) +#define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1) +#define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD +#define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2) +#define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1) +#define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB +#define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3) +#define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1) +#define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7 +#define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4) +#define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1) +#define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF +#define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5) +#define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1) +#define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF +#define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8) +#define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1) +#define C_028818_VTX_XY_FMT 0xFFFFFEFF +#define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9) +#define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1) +#define C_028818_VTX_Z_FMT 0xFFFFFDFF +#define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10) +#define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1) +#define C_028818_VTX_W0_FMT 0xFFFFFBFF +#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C +#define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0) +#define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1) +#define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE +#define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1) +#define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1) +#define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD +#define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2) +#define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1) +#define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB +#define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3) +#define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1) +#define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7 +#define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4) +#define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1) +#define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF +#define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5) +#define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1) +#define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF +#define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6) +#define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1) +#define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF +#define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7) +#define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1) +#define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F +#define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8) +#define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1) +#define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF +#define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9) +#define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1) +#define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF +#define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10) +#define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1) +#define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF +#define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11) +#define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1) +#define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF +#define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12) +#define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1) +#define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF +#define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13) +#define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1) +#define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF +#define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14) +#define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1) +#define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF +#define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15) +#define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1) +#define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF +#define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16) +#define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1) +#define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF +#define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17) +#define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1) +#define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF +#define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18) +#define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1) +#define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF +#define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19) +#define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1) +#define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF +#define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20) +#define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1) +#define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF +#define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21) +#define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1) +#define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF +#define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22) +#define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1) +#define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF +#define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23) +#define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1) +#define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF +#define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24) +#define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1) +#define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF +#define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25) +#define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1) +#define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF +#define R_028820_PA_CL_NANINF_CNTL 0x028820 +#define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0) +#define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1) +#define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE +#define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1) +#define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1) +#define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD +#define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2) +#define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1) +#define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB +#define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3) +#define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1) +#define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7 +#define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4) +#define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1) +#define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF +#define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5) +#define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1) +#define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF +#define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6) +#define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1) +#define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF +#define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7) +#define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1) +#define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F +#define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8) +#define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1) +#define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF +#define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9) +#define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1) +#define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF +#define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10) +#define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1) +#define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF +#define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11) +#define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1) +#define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF +#define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12) +#define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1) +#define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF +#define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13) +#define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1) +#define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF +#define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14) +#define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1) +#define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF +#define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20) +#define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1) +#define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF +#define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824 +#define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0) +#define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03) +#define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC +#define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2) +#define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1) +#define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB +#define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3) +#define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1) +#define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7 +#define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4) +#define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1) +#define C_028824_DIAMOND_ADJUST 0xFFFFFFEF +#define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828 +#define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C +#define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0) +#define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1) +#define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE +#define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1) +#define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1) +#define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD +#define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2) +#define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1) +#define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB +#define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3) +#define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1) +#define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7 +#define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4) +#define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1) +#define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF +#define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5) +#define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1) +#define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF +#define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6) +#define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1) +#define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF +#define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7) +#define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1) +#define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F +#define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8) +#define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF) +#define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF +#define R_028A00_PA_SU_POINT_SIZE 0x028A00 +#define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0) +#define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF) +#define C_028A00_HEIGHT 0xFFFF0000 +#define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16) +#define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF) +#define C_028A00_WIDTH 0x0000FFFF +#define R_028A04_PA_SU_POINT_MINMAX 0x028A04 +#define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0) +#define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF) +#define C_028A04_MIN_SIZE 0xFFFF0000 +#define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16) +#define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF) +#define C_028A04_MAX_SIZE 0x0000FFFF +#define R_028A08_PA_SU_LINE_CNTL 0x028A08 +#define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0) +#define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF) +#define C_028A08_WIDTH 0xFFFF0000 +#define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C +#define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0) +#define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF) +#define C_028A0C_LINE_PATTERN 0xFFFF0000 +#define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16) +#define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF) +#define C_028A0C_REPEAT_COUNT 0xFF00FFFF +#define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28) +#define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1) +#define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF +#define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29) +#define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03) +#define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF +#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 +#define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0) +#define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07) +#define C_028A10_PATH_SELECT 0xFFFFFFF8 +#define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00 +#define V_028A10_VGT_OUTPATH_TESS_EN 0x01 +#define V_028A10_VGT_OUTPATH_PASSTHRU 0x02 +#define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03 +#define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04 +#define R_028A14_VGT_HOS_CNTL 0x028A14 +#define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0) +#define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03) +#define C_028A14_TESS_MODE 0xFFFFFFFC +#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 +#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C +#define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 +#define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) +#define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) +#define C_028A20_REUSE_DEPTH 0xFFFFFF00 +#define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 +#define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) +#define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) +#define C_028A24_PRIM_TYPE 0xFFFFFFE0 +#define V_028A24_VGT_GRP_3D_POINT 0x00 +#define V_028A24_VGT_GRP_3D_LINE 0x01 +#define V_028A24_VGT_GRP_3D_TRI 0x02 +#define V_028A24_VGT_GRP_3D_RECT 0x03 +#define V_028A24_VGT_GRP_3D_QUAD 0x04 +#define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05 +#define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06 +#define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07 +#define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08 +#define V_028A24_VGT_GRP_2D_FILL_RECT 0x09 +#define V_028A24_VGT_GRP_2D_LINE 0x0A +#define V_028A24_VGT_GRP_2D_TRI 0x0B +#define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C +#define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D +#define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E +#define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F +#define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10 +#define V_028A24_VGT_GRP_3D_PATCH 0x11 +#define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) +#define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) +#define C_028A24_RETAIN_ORDER 0xFFFFBFFF +#define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) +#define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) +#define C_028A24_RETAIN_QUADS 0xFFFF7FFF +#define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16) +#define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07) +#define C_028A24_PRIM_ORDER 0xFFF8FFFF +#define V_028A24_VGT_GRP_LIST 0x00 +#define V_028A24_VGT_GRP_STRIP 0x01 +#define V_028A24_VGT_GRP_FAN 0x02 +#define V_028A24_VGT_GRP_LOOP 0x03 +#define V_028A24_VGT_GRP_POLYGON 0x04 +#define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 +#define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0) +#define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F) +#define C_028A28_FIRST_DECR 0xFFFFFFF0 +#define R_028A2C_VGT_GROUP_DECR 0x028A2C +#define S_028A2C_DECR(x) (((x) & 0x0F) << 0) +#define G_028A2C_DECR(x) (((x) >> 0) & 0x0F) +#define C_028A2C_DECR 0xFFFFFFF0 +#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 +#define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A30_COMP_X_EN 0xFFFFFFFE +#define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A30_COMP_Y_EN 0xFFFFFFFD +#define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A30_COMP_Z_EN 0xFFFFFFFB +#define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A30_COMP_W_EN 0xFFFFFFF7 +#define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A30_STRIDE 0xFFFF00FF +#define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A30_SHIFT 0xFF00FFFF +#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 +#define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A34_COMP_X_EN 0xFFFFFFFE +#define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A34_COMP_Y_EN 0xFFFFFFFD +#define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A34_COMP_Z_EN 0xFFFFFFFB +#define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A34_COMP_W_EN 0xFFFFFFF7 +#define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A34_STRIDE 0xFFFF00FF +#define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A34_SHIFT 0xFF00FFFF +#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 +#define S_028A38_X_CONV(x) (((x) & 0x0F) << 0) +#define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F) +#define C_028A38_X_CONV 0xFFFFFFF0 +#define V_028A38_VGT_GRP_INDEX_16 0x00 +#define V_028A38_VGT_GRP_INDEX_32 0x01 +#define V_028A38_VGT_GRP_UINT_16 0x02 +#define V_028A38_VGT_GRP_UINT_32 0x03 +#define V_028A38_VGT_GRP_SINT_16 0x04 +#define V_028A38_VGT_GRP_SINT_32 0x05 +#define V_028A38_VGT_GRP_FLOAT_32 0x06 +#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4) +#define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F) +#define C_028A38_X_OFFSET 0xFFFFFF0F +#define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8) +#define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F) +#define C_028A38_Y_CONV 0xFFFFF0FF +#define V_028A38_VGT_GRP_INDEX_16 0x00 +#define V_028A38_VGT_GRP_INDEX_32 0x01 +#define V_028A38_VGT_GRP_UINT_16 0x02 +#define V_028A38_VGT_GRP_UINT_32 0x03 +#define V_028A38_VGT_GRP_SINT_16 0x04 +#define V_028A38_VGT_GRP_SINT_32 0x05 +#define V_028A38_VGT_GRP_FLOAT_32 0x06 +#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12) +#define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F) +#define C_028A38_Y_OFFSET 0xFFFF0FFF +#define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16) +#define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F) +#define C_028A38_Z_CONV 0xFFF0FFFF +#define V_028A38_VGT_GRP_INDEX_16 0x00 +#define V_028A38_VGT_GRP_INDEX_32 0x01 +#define V_028A38_VGT_GRP_UINT_16 0x02 +#define V_028A38_VGT_GRP_UINT_32 0x03 +#define V_028A38_VGT_GRP_SINT_16 0x04 +#define V_028A38_VGT_GRP_SINT_32 0x05 +#define V_028A38_VGT_GRP_FLOAT_32 0x06 +#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20) +#define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F) +#define C_028A38_Z_OFFSET 0xFF0FFFFF +#define S_028A38_W_CONV(x) (((x) & 0x0F) << 24) +#define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F) +#define C_028A38_W_CONV 0xF0FFFFFF +#define V_028A38_VGT_GRP_INDEX_16 0x00 +#define V_028A38_VGT_GRP_INDEX_32 0x01 +#define V_028A38_VGT_GRP_UINT_16 0x02 +#define V_028A38_VGT_GRP_UINT_32 0x03 +#define V_028A38_VGT_GRP_SINT_16 0x04 +#define V_028A38_VGT_GRP_SINT_32 0x05 +#define V_028A38_VGT_GRP_FLOAT_32 0x06 +#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28) +#define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F) +#define C_028A38_W_OFFSET 0x0FFFFFFF +#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C +#define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0) +#define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F) +#define C_028A3C_X_CONV 0xFFFFFFF0 +#define V_028A3C_VGT_GRP_INDEX_16 0x00 +#define V_028A3C_VGT_GRP_INDEX_32 0x01 +#define V_028A3C_VGT_GRP_UINT_16 0x02 +#define V_028A3C_VGT_GRP_UINT_32 0x03 +#define V_028A3C_VGT_GRP_SINT_16 0x04 +#define V_028A3C_VGT_GRP_SINT_32 0x05 +#define V_028A3C_VGT_GRP_FLOAT_32 0x06 +#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4) +#define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F) +#define C_028A3C_X_OFFSET 0xFFFFFF0F +#define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8) +#define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F) +#define C_028A3C_Y_CONV 0xFFFFF0FF +#define V_028A3C_VGT_GRP_INDEX_16 0x00 +#define V_028A3C_VGT_GRP_INDEX_32 0x01 +#define V_028A3C_VGT_GRP_UINT_16 0x02 +#define V_028A3C_VGT_GRP_UINT_32 0x03 +#define V_028A3C_VGT_GRP_SINT_16 0x04 +#define V_028A3C_VGT_GRP_SINT_32 0x05 +#define V_028A3C_VGT_GRP_FLOAT_32 0x06 +#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12) +#define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F) +#define C_028A3C_Y_OFFSET 0xFFFF0FFF +#define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16) +#define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F) +#define C_028A3C_Z_CONV 0xFFF0FFFF +#define V_028A3C_VGT_GRP_INDEX_16 0x00 +#define V_028A3C_VGT_GRP_INDEX_32 0x01 +#define V_028A3C_VGT_GRP_UINT_16 0x02 +#define V_028A3C_VGT_GRP_UINT_32 0x03 +#define V_028A3C_VGT_GRP_SINT_16 0x04 +#define V_028A3C_VGT_GRP_SINT_32 0x05 +#define V_028A3C_VGT_GRP_FLOAT_32 0x06 +#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20) +#define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F) +#define C_028A3C_Z_OFFSET 0xFF0FFFFF +#define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24) +#define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F) +#define C_028A3C_W_CONV 0xF0FFFFFF +#define V_028A3C_VGT_GRP_INDEX_16 0x00 +#define V_028A3C_VGT_GRP_INDEX_32 0x01 +#define V_028A3C_VGT_GRP_UINT_16 0x02 +#define V_028A3C_VGT_GRP_UINT_32 0x03 +#define V_028A3C_VGT_GRP_SINT_16 0x04 +#define V_028A3C_VGT_GRP_SINT_32 0x05 +#define V_028A3C_VGT_GRP_FLOAT_32 0x06 +#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 +#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 +#define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28) +#define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F) +#define C_028A3C_W_OFFSET 0x0FFFFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x07) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x07) +#define C_028A40_MODE 0xFFFFFFF8 +#define V_028A40_GS_OFF 0x00 +#define V_028A40_GS_SCENARIO_A 0x01 +#define V_028A40_GS_SCENARIO_B 0x02 +#define V_028A40_GS_SCENARIO_G 0x03 +#define V_028A40_GS_SCENARIO_C 0x04 +#define V_028A40_SPRITE_EN 0x05 +#define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4) +#define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03) +#define C_028A40_CUT_MODE 0xFFFFFFCF +#define V_028A40_GS_CUT_1024 0x00 +#define V_028A40_GS_CUT_512 0x01 +#define V_028A40_GS_CUT_256 0x02 +#define V_028A40_GS_CUT_128 0x03 +#define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11) +#define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1) +#define C_028A40_GS_C_PACK_EN 0xFFFFF7FF +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFDFFF +#define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14) +#define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1) +#define C_028A40_COMPUTE_MODE 0xFFFFBFFF +#define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15) +#define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1) +#define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF +#define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16) +#define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1) +#define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF +#define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17) +#define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1) +#define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF +#define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18) +#define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1) +#define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF +#define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19) +#define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1) +#define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF +#define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20) +#define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1) +#define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF +#define R_028A48_PA_SC_MODE_CNTL_0 0x028A48 +#define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0) +#define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028A48_MSAA_ENABLE 0xFFFFFFFE +#define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1) +#define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD +#define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB +#define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3) +#define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1) +#define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7 +#define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C +#define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0) +#define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1) +#define C_028A4C_WALK_SIZE 0xFFFFFFFE +#define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1) +#define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1) +#define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD +#define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2) +#define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1) +#define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB +#define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3) +#define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7 +#define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4) +#define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07) +#define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F +#define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7) +#define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F +#define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8) +#define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1) +#define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF +#define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9) +#define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1) +#define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF +#define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10) +#define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1) +#define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF +#define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11) +#define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1) +#define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF +#define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12) +#define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1) +#define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF +#define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13) +#define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1) +#define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF +#define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14) +#define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1) +#define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF +#define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15) +#define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1) +#define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF +#define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16) +#define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1) +#define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF +#define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) & 0x1) << 17) +#define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) >> 17) & 0x1) +#define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC 0xFFFDFFFF +#define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25) +#define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1) +#define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF +#define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26) +#define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1) +#define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF +#define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27) +#define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1) +#define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF +#define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28) +#define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07) +#define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF +#define R_028A50_VGT_ENHANCE 0x028A50 +#define R_028A54_VGT_GS_PER_ES 0x028A54 +#define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0) +#define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF) +#define C_028A54_GS_PER_ES 0xFFFFF800 +#define R_028A58_VGT_ES_PER_GS 0x028A58 +#define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0) +#define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF) +#define C_028A58_ES_PER_GS 0xFFFFF800 +#define R_028A5C_VGT_GS_PER_VS 0x028A5C +#define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0) +#define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F) +#define C_028A5C_GS_PER_VS 0xFFFFFFF0 +#define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60 +#define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0) +#define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF) +#define C_028A60_OFFSET 0xFFFF8000 +#define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64 +#define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0) +#define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF) +#define C_028A64_OFFSET 0xFFFF8000 +#define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68 +#define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0) +#define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF) +#define C_028A68_OFFSET 0xFFFF8000 +#define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C +#define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0 +#define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8) +#define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F) +#define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF +#define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16) +#define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F) +#define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF +#define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22) +#define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F) +#define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF +#define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31) +#define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1) +#define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF +#define R_028A70_IA_ENHANCE 0x028A70 +#define R_028A74_VGT_DMA_SIZE 0x028A74 +#define R_028A78_VGT_DMA_MAX_SIZE 0x028A78 +#define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C +#define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0) +#define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03) +#define C_028A7C_INDEX_TYPE 0xFFFFFFFC +#define V_028A7C_VGT_INDEX_16 0x00 +#define V_028A7C_VGT_INDEX_32 0x01 +#define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2) +#define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03) +#define C_028A7C_SWAP_MODE 0xFFFFFFF3 +#define V_028A7C_VGT_DMA_SWAP_NONE 0x00 +#define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01 +#define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02 +#define V_028A7C_VGT_DMA_SWAP_WORD 0x03 +#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 +#define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) +#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) +#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE +#define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) +#define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) +#define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD +#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 +#define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C +#define R_028A90_VGT_EVENT_INITIATOR 0x028A90 +#define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0) +#define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F) +#define C_028A90_EVENT_TYPE 0xFFFFFFC0 +#define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01 +#define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02 +#define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03 +#define V_028A90_CACHE_FLUSH_TS 0x04 +#define V_028A90_CONTEXT_DONE 0x05 +#define V_028A90_CACHE_FLUSH 0x06 +#define V_028A90_CS_PARTIAL_FLUSH 0x07 +#define V_028A90_VGT_STREAMOUT_SYNC 0x08 +#define V_028A90_VGT_STREAMOUT_RESET 0x0A +#define V_028A90_END_OF_PIPE_INCR_DE 0x0B +#define V_028A90_END_OF_PIPE_IB_END 0x0C +#define V_028A90_RST_PIX_CNT 0x0D +#define V_028A90_VS_PARTIAL_FLUSH 0x0F +#define V_028A90_PS_PARTIAL_FLUSH 0x10 +#define V_028A90_FLUSH_HS_OUTPUT 0x11 +#define V_028A90_FLUSH_LS_OUTPUT 0x12 +#define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 +#define V_028A90_ZPASS_DONE 0x15 +#define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16 +#define V_028A90_PERFCOUNTER_START 0x17 +#define V_028A90_PERFCOUNTER_STOP 0x18 +#define V_028A90_PIPELINESTAT_START 0x19 +#define V_028A90_PIPELINESTAT_STOP 0x1A +#define V_028A90_PERFCOUNTER_SAMPLE 0x1B +#define V_028A90_FLUSH_ES_OUTPUT 0x1C +#define V_028A90_FLUSH_GS_OUTPUT 0x1D +#define V_028A90_SAMPLE_PIPELINESTAT 0x1E +#define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F +#define V_028A90_SAMPLE_STREAMOUTSTATS 0x20 +#define V_028A90_RESET_VTX_CNT 0x21 +#define V_028A90_BLOCK_CONTEXT_DONE 0x22 +#define V_028A90_CS_CONTEXT_DONE 0x23 +#define V_028A90_VGT_FLUSH 0x24 +#define V_028A90_SC_SEND_DB_VPZ 0x27 +#define V_028A90_BOTTOM_OF_PIPE_TS 0x28 +#define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A +#define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B +#define V_028A90_FLUSH_AND_INV_DB_META 0x2C +#define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D +#define V_028A90_FLUSH_AND_INV_CB_META 0x2E +#define V_028A90_CS_DONE 0x2F +#define V_028A90_PS_DONE 0x30 +#define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31 +#define V_028A90_THREAD_TRACE_START 0x33 +#define V_028A90_THREAD_TRACE_STOP 0x34 +#define V_028A90_THREAD_TRACE_MARKER 0x35 +#define V_028A90_THREAD_TRACE_FLUSH 0x36 +#define V_028A90_THREAD_TRACE_FINISH 0x37 +#define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18) +#define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF) +#define C_028A90_ADDRESS_HI 0xF803FFFF +#define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27) +#define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) +#define C_028A90_EXTENDED_EVENT 0xF7FFFFFF +#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 +#define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) +#define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) +#define C_028A94_RESET_EN 0xFFFFFFFE +#define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 +#define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 +#define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8 +#define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0) +#define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF) +#define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000 +#define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16) +#define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1) +#define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF +#define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17) +#define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1) +#define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF +#define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18) +#define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1) +#define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF +#define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19) +#define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1) +#define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF +#define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC +#define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028AAC_ITEMSIZE 0xFFFF8000 +#define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0 +#define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028AB0_ITEMSIZE 0xFFFF8000 +#define R_028AB4_VGT_REUSE_OFF 0x028AB4 +#define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) +#define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) +#define C_028AB4_REUSE_OFF 0xFFFFFFFE +#define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 +#define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) +#define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) +#define C_028AB8_VTX_CNT_EN 0xFFFFFFFE +#define R_028ABC_DB_HTILE_SURFACE 0x028ABC +#define S_028ABC_LINEAR(x) (((x) & 0x1) << 0) +#define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1) +#define C_028ABC_LINEAR 0xFFFFFFFE +#define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1) +#define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1) +#define C_028ABC_FULL_CACHE 0xFFFFFFFD +#define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2) +#define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1) +#define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB +#define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3) +#define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1) +#define C_028ABC_PRELOAD 0xFFFFFFF7 +#define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4) +#define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F) +#define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F +#define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10) +#define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F) +#define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF +#define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16) +#define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1) +#define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF +#define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0 +#define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0) +#define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07) +#define C_028AC0_COMPAREFUNC0 0xFFFFFFF8 +#define V_028AC0_REF_NEVER 0x00 +#define V_028AC0_REF_LESS 0x01 +#define V_028AC0_REF_EQUAL 0x02 +#define V_028AC0_REF_LEQUAL 0x03 +#define V_028AC0_REF_GREATER 0x04 +#define V_028AC0_REF_NOTEQUAL 0x05 +#define V_028AC0_REF_GEQUAL 0x06 +#define V_028AC0_REF_ALWAYS 0x07 +#define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4) +#define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF) +#define C_028AC0_COMPAREVALUE0 0xFFFFF00F +#define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12) +#define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF) +#define C_028AC0_COMPAREMASK0 0xFFF00FFF +#define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24) +#define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1) +#define C_028AC0_ENABLE0 0xFEFFFFFF +#define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4 +#define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0) +#define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07) +#define C_028AC4_COMPAREFUNC1 0xFFFFFFF8 +#define V_028AC4_REF_NEVER 0x00 +#define V_028AC4_REF_LESS 0x01 +#define V_028AC4_REF_EQUAL 0x02 +#define V_028AC4_REF_LEQUAL 0x03 +#define V_028AC4_REF_GREATER 0x04 +#define V_028AC4_REF_NOTEQUAL 0x05 +#define V_028AC4_REF_GEQUAL 0x06 +#define V_028AC4_REF_ALWAYS 0x07 +#define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4) +#define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF) +#define C_028AC4_COMPAREVALUE1 0xFFFFF00F +#define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12) +#define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF) +#define C_028AC4_COMPAREMASK1 0xFFF00FFF +#define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24) +#define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1) +#define C_028AC4_ENABLE1 0xFEFFFFFF +#define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8 +#define S_028AC8_START_X(x) (((x) & 0xFF) << 0) +#define G_028AC8_START_X(x) (((x) >> 0) & 0xFF) +#define C_028AC8_START_X 0xFFFFFF00 +#define S_028AC8_START_Y(x) (((x) & 0xFF) << 8) +#define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF) +#define C_028AC8_START_Y 0xFFFF00FF +#define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16) +#define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF) +#define C_028AC8_MAX_X 0xFF00FFFF +#define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24) +#define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF) +#define C_028AC8_MAX_Y 0x00FFFFFF +#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 +#define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4 +#define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0) +#define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF) +#define C_028AD4_STRIDE 0xFFFFFC00 +#define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC +#define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0 +#define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4 +#define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0) +#define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF) +#define C_028AE4_STRIDE 0xFFFFFC00 +#define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC +#define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0 +#define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4 +#define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0) +#define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF) +#define C_028AF4_STRIDE 0xFFFFFC00 +#define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC +#define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00 +#define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04 +#define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0) +#define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF) +#define C_028B04_STRIDE 0xFFFFFC00 +#define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C +#define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28 +#define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C +#define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30 +#define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0) +#define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF) +#define C_028B30_VERTEX_STRIDE 0xFFFFFE00 +#define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38 +#define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0) +#define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF) +#define C_028B38_MAX_VERT_OUT 0xFFFFF800 +#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 +#define S_028B54_LS_EN(x) (((x) & 0x03) << 0) +#define G_028B54_LS_EN(x) (((x) >> 0) & 0x03) +#define C_028B54_LS_EN 0xFFFFFFFC +#define V_028B54_LS_STAGE_OFF 0x00 +#define V_028B54_LS_STAGE_ON 0x01 +#define V_028B54_CS_STAGE_ON 0x02 +#define S_028B54_HS_EN(x) (((x) & 0x1) << 2) +#define G_028B54_HS_EN(x) (((x) >> 2) & 0x1) +#define C_028B54_HS_EN 0xFFFFFFFB +#define S_028B54_ES_EN(x) (((x) & 0x03) << 3) +#define G_028B54_ES_EN(x) (((x) >> 3) & 0x03) +#define C_028B54_ES_EN 0xFFFFFFE7 +#define V_028B54_ES_STAGE_OFF 0x00 +#define V_028B54_ES_STAGE_DS 0x01 +#define V_028B54_ES_STAGE_REAL 0x02 +#define S_028B54_GS_EN(x) (((x) & 0x1) << 5) +#define G_028B54_GS_EN(x) (((x) >> 5) & 0x1) +#define C_028B54_GS_EN 0xFFFFFFDF +#define S_028B54_VS_EN(x) (((x) & 0x03) << 6) +#define G_028B54_VS_EN(x) (((x) >> 6) & 0x03) +#define C_028B54_VS_EN 0xFFFFFF3F +#define V_028B54_VS_STAGE_REAL 0x00 +#define V_028B54_VS_STAGE_DS 0x01 +#define V_028B54_VS_STAGE_COPY_SHADER 0x02 +#define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8) +#define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1) +#define C_028B54_DYNAMIC_HS 0xFFFFFEFF +#define R_028B58_VGT_LS_HS_CONFIG 0x028B58 +#define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0) +#define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF) +#define C_028B58_NUM_PATCHES 0xFFFFFF00 +#define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8) +#define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F) +#define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF +#define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14) +#define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F) +#define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF +#define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C +#define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028B5C_ITEMSIZE 0xFFFF8000 +#define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60 +#define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028B60_ITEMSIZE 0xFFFF8000 +#define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64 +#define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028B64_ITEMSIZE 0xFFFF8000 +#define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68 +#define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_028B68_ITEMSIZE 0xFFFF8000 +#define R_028B6C_VGT_TF_PARAM 0x028B6C +#define S_028B6C_TYPE(x) (((x) & 0x03) << 0) +#define G_028B6C_TYPE(x) (((x) >> 0) & 0x03) +#define C_028B6C_TYPE 0xFFFFFFFC +#define V_028B6C_TESS_ISOLINE 0x00 +#define V_028B6C_TESS_TRIANGLE 0x01 +#define V_028B6C_TESS_QUAD 0x02 +#define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2) +#define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07) +#define C_028B6C_PARTITIONING 0xFFFFFFE3 +#define V_028B6C_PART_INTEGER 0x00 +#define V_028B6C_PART_POW2 0x01 +#define V_028B6C_PART_FRAC_ODD 0x02 +#define V_028B6C_PART_FRAC_EVEN 0x03 +#define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5) +#define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07) +#define C_028B6C_TOPOLOGY 0xFFFFFF1F +#define V_028B6C_OUTPUT_POINT 0x00 +#define V_028B6C_OUTPUT_LINE 0x01 +#define V_028B6C_OUTPUT_TRIANGLE_CW 0x02 +#define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03 +#define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) +#define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) +#define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF +#define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10) +#define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F) +#define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF +#define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14) +#define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1) +#define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF +#define R_028B70_DB_ALPHA_TO_MASK 0x028B70 +#define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0) +#define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE +#define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8) +#define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03) +#define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF +#define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10) +#define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03) +#define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF +#define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12) +#define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03) +#define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF +#define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14) +#define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03) +#define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF +#define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16) +#define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1) +#define C_028B70_OFFSET_ROUND 0xFFFEFFFF +#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78 +#define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0) +#define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF) +#define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00 +#define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8) +#define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1) +#define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF +#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C +#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80 +#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84 +#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88 +#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C +#define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90 +#define S_028B90_ENABLE(x) (((x) & 0x1) << 0) +#define G_028B90_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028B90_ENABLE 0xFFFFFFFE +#define S_028B90_CNT(x) (((x) & 0x7F) << 2) +#define G_028B90_CNT(x) (((x) >> 2) & 0x7F) +#define C_028B90_CNT 0xFFFFFE03 +#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 +#define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0) +#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) +#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE +#define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1) +#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) +#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD +#define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2) +#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) +#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB +#define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3) +#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) +#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 +#define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4) +#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) +#define C_028B94_RAST_STREAM 0xFFFFFF8F +#define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8) +#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) +#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF +#define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31) +#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) +#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF +#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 +#define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0) +#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) +#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 +#define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4) +#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) +#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F +#define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8) +#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) +#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF +#define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12) +#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) +#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF +#define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4 +#define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0) +#define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F) +#define C_028BD4_DISTANCE_0 0xFFFFFFF0 +#define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4) +#define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F) +#define C_028BD4_DISTANCE_1 0xFFFFFF0F +#define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8) +#define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F) +#define C_028BD4_DISTANCE_2 0xFFFFF0FF +#define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12) +#define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F) +#define C_028BD4_DISTANCE_3 0xFFFF0FFF +#define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16) +#define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F) +#define C_028BD4_DISTANCE_4 0xFFF0FFFF +#define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20) +#define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F) +#define C_028BD4_DISTANCE_5 0xFF0FFFFF +#define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24) +#define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F) +#define C_028BD4_DISTANCE_6 0xF0FFFFFF +#define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28) +#define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F) +#define C_028BD4_DISTANCE_7 0x0FFFFFFF +#define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8 +#define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0) +#define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F) +#define C_028BD8_DISTANCE_8 0xFFFFFFF0 +#define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4) +#define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F) +#define C_028BD8_DISTANCE_9 0xFFFFFF0F +#define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8) +#define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F) +#define C_028BD8_DISTANCE_10 0xFFFFF0FF +#define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12) +#define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F) +#define C_028BD8_DISTANCE_11 0xFFFF0FFF +#define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16) +#define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F) +#define C_028BD8_DISTANCE_12 0xFFF0FFFF +#define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20) +#define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F) +#define C_028BD8_DISTANCE_13 0xFF0FFFFF +#define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24) +#define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F) +#define C_028BD8_DISTANCE_14 0xF0FFFFFF +#define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28) +#define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F) +#define C_028BD8_DISTANCE_15 0x0FFFFFFF +#define R_028BDC_PA_SC_LINE_CNTL 0x028BDC +#define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) +#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) +#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF +#define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10) +#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) +#define C_028BDC_LAST_PIXEL 0xFFFFFBFF +#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11) +#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) +#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF +#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12) +#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) +#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF +#define R_028BE0_PA_SC_AA_CONFIG 0x028BE0 +#define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x07) << 0) +#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07) +#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8 +#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) +#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) +#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF +#define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0x0F) << 13) +#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F) +#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF +#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x07) << 20) +#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07) +#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF +#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x03) << 24) +#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03) +#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF +#define R_028BE4_PA_SU_VTX_CNTL 0x028BE4 +#define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0) +#define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1) +#define C_028BE4_PIX_CENTER 0xFFFFFFFE +#define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1) +#define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03) +#define C_028BE4_ROUND_MODE 0xFFFFFFF9 +#define V_028BE4_X_TRUNCATE 0x00 +#define V_028BE4_X_ROUND 0x01 +#define V_028BE4_X_ROUND_TO_EVEN 0x02 +#define V_028BE4_X_ROUND_TO_ODD 0x03 +#define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3) +#define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07) +#define C_028BE4_QUANT_MODE 0xFFFFFFC7 +#define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00 +#define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01 +#define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02 +#define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03 +#define V_028BE4_X_16_8_FIXED_POINT_1 0x04 +#define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05 +#define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06 +#define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07 +#define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8 +#define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC +#define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0 +#define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4 +#define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8 +#define S_028BF8_S0_X(x) (((x) & 0x0F) << 0) +#define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F) +#define C_028BF8_S0_X 0xFFFFFFF0 +#define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4) +#define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F) +#define C_028BF8_S0_Y 0xFFFFFF0F +#define S_028BF8_S1_X(x) (((x) & 0x0F) << 8) +#define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F) +#define C_028BF8_S1_X 0xFFFFF0FF +#define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12) +#define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F) +#define C_028BF8_S1_Y 0xFFFF0FFF +#define S_028BF8_S2_X(x) (((x) & 0x0F) << 16) +#define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F) +#define C_028BF8_S2_X 0xFFF0FFFF +#define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20) +#define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F) +#define C_028BF8_S2_Y 0xFF0FFFFF +#define S_028BF8_S3_X(x) (((x) & 0x0F) << 24) +#define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F) +#define C_028BF8_S3_X 0xF0FFFFFF +#define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28) +#define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F) +#define C_028BF8_S3_Y 0x0FFFFFFF +#define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC +#define S_028BFC_S4_X(x) (((x) & 0x0F) << 0) +#define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F) +#define C_028BFC_S4_X 0xFFFFFFF0 +#define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4) +#define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F) +#define C_028BFC_S4_Y 0xFFFFFF0F +#define S_028BFC_S5_X(x) (((x) & 0x0F) << 8) +#define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F) +#define C_028BFC_S5_X 0xFFFFF0FF +#define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12) +#define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F) +#define C_028BFC_S5_Y 0xFFFF0FFF +#define S_028BFC_S6_X(x) (((x) & 0x0F) << 16) +#define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F) +#define C_028BFC_S6_X 0xFFF0FFFF +#define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20) +#define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F) +#define C_028BFC_S6_Y 0xFF0FFFFF +#define S_028BFC_S7_X(x) (((x) & 0x0F) << 24) +#define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F) +#define C_028BFC_S7_X 0xF0FFFFFF +#define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28) +#define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F) +#define C_028BFC_S7_Y 0x0FFFFFFF +#define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00 +#define S_028C00_S8_X(x) (((x) & 0x0F) << 0) +#define G_028C00_S8_X(x) (((x) >> 0) & 0x0F) +#define C_028C00_S8_X 0xFFFFFFF0 +#define S_028C00_S8_Y(x) (((x) & 0x0F) << 4) +#define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F) +#define C_028C00_S8_Y 0xFFFFFF0F +#define S_028C00_S9_X(x) (((x) & 0x0F) << 8) +#define G_028C00_S9_X(x) (((x) >> 8) & 0x0F) +#define C_028C00_S9_X 0xFFFFF0FF +#define S_028C00_S9_Y(x) (((x) & 0x0F) << 12) +#define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F) +#define C_028C00_S9_Y 0xFFFF0FFF +#define S_028C00_S10_X(x) (((x) & 0x0F) << 16) +#define G_028C00_S10_X(x) (((x) >> 16) & 0x0F) +#define C_028C00_S10_X 0xFFF0FFFF +#define S_028C00_S10_Y(x) (((x) & 0x0F) << 20) +#define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F) +#define C_028C00_S10_Y 0xFF0FFFFF +#define S_028C00_S11_X(x) (((x) & 0x0F) << 24) +#define G_028C00_S11_X(x) (((x) >> 24) & 0x0F) +#define C_028C00_S11_X 0xF0FFFFFF +#define S_028C00_S11_Y(x) (((x) & 0x0F) << 28) +#define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F) +#define C_028C00_S11_Y 0x0FFFFFFF +#define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04 +#define S_028C04_S12_X(x) (((x) & 0x0F) << 0) +#define G_028C04_S12_X(x) (((x) >> 0) & 0x0F) +#define C_028C04_S12_X 0xFFFFFFF0 +#define S_028C04_S12_Y(x) (((x) & 0x0F) << 4) +#define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F) +#define C_028C04_S12_Y 0xFFFFFF0F +#define S_028C04_S13_X(x) (((x) & 0x0F) << 8) +#define G_028C04_S13_X(x) (((x) >> 8) & 0x0F) +#define C_028C04_S13_X 0xFFFFF0FF +#define S_028C04_S13_Y(x) (((x) & 0x0F) << 12) +#define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F) +#define C_028C04_S13_Y 0xFFFF0FFF +#define S_028C04_S14_X(x) (((x) & 0x0F) << 16) +#define G_028C04_S14_X(x) (((x) >> 16) & 0x0F) +#define C_028C04_S14_X 0xFFF0FFFF +#define S_028C04_S14_Y(x) (((x) & 0x0F) << 20) +#define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F) +#define C_028C04_S14_Y 0xFF0FFFFF +#define S_028C04_S15_X(x) (((x) & 0x0F) << 24) +#define G_028C04_S15_X(x) (((x) >> 24) & 0x0F) +#define C_028C04_S15_X 0xF0FFFFFF +#define S_028C04_S15_Y(x) (((x) & 0x0F) << 28) +#define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F) +#define C_028C04_S15_Y 0x0FFFFFFF +#define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08 +#define S_028C08_S0_X(x) (((x) & 0x0F) << 0) +#define G_028C08_S0_X(x) (((x) >> 0) & 0x0F) +#define C_028C08_S0_X 0xFFFFFFF0 +#define S_028C08_S0_Y(x) (((x) & 0x0F) << 4) +#define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F) +#define C_028C08_S0_Y 0xFFFFFF0F +#define S_028C08_S1_X(x) (((x) & 0x0F) << 8) +#define G_028C08_S1_X(x) (((x) >> 8) & 0x0F) +#define C_028C08_S1_X 0xFFFFF0FF +#define S_028C08_S1_Y(x) (((x) & 0x0F) << 12) +#define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F) +#define C_028C08_S1_Y 0xFFFF0FFF +#define S_028C08_S2_X(x) (((x) & 0x0F) << 16) +#define G_028C08_S2_X(x) (((x) >> 16) & 0x0F) +#define C_028C08_S2_X 0xFFF0FFFF +#define S_028C08_S2_Y(x) (((x) & 0x0F) << 20) +#define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F) +#define C_028C08_S2_Y 0xFF0FFFFF +#define S_028C08_S3_X(x) (((x) & 0x0F) << 24) +#define G_028C08_S3_X(x) (((x) >> 24) & 0x0F) +#define C_028C08_S3_X 0xF0FFFFFF +#define S_028C08_S3_Y(x) (((x) & 0x0F) << 28) +#define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F) +#define C_028C08_S3_Y 0x0FFFFFFF +#define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C +#define S_028C0C_S4_X(x) (((x) & 0x0F) << 0) +#define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F) +#define C_028C0C_S4_X 0xFFFFFFF0 +#define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4) +#define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F) +#define C_028C0C_S4_Y 0xFFFFFF0F +#define S_028C0C_S5_X(x) (((x) & 0x0F) << 8) +#define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F) +#define C_028C0C_S5_X 0xFFFFF0FF +#define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12) +#define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F) +#define C_028C0C_S5_Y 0xFFFF0FFF +#define S_028C0C_S6_X(x) (((x) & 0x0F) << 16) +#define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F) +#define C_028C0C_S6_X 0xFFF0FFFF +#define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20) +#define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F) +#define C_028C0C_S6_Y 0xFF0FFFFF +#define S_028C0C_S7_X(x) (((x) & 0x0F) << 24) +#define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F) +#define C_028C0C_S7_X 0xF0FFFFFF +#define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28) +#define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F) +#define C_028C0C_S7_Y 0x0FFFFFFF +#define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10 +#define S_028C10_S8_X(x) (((x) & 0x0F) << 0) +#define G_028C10_S8_X(x) (((x) >> 0) & 0x0F) +#define C_028C10_S8_X 0xFFFFFFF0 +#define S_028C10_S8_Y(x) (((x) & 0x0F) << 4) +#define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F) +#define C_028C10_S8_Y 0xFFFFFF0F +#define S_028C10_S9_X(x) (((x) & 0x0F) << 8) +#define G_028C10_S9_X(x) (((x) >> 8) & 0x0F) +#define C_028C10_S9_X 0xFFFFF0FF +#define S_028C10_S9_Y(x) (((x) & 0x0F) << 12) +#define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F) +#define C_028C10_S9_Y 0xFFFF0FFF +#define S_028C10_S10_X(x) (((x) & 0x0F) << 16) +#define G_028C10_S10_X(x) (((x) >> 16) & 0x0F) +#define C_028C10_S10_X 0xFFF0FFFF +#define S_028C10_S10_Y(x) (((x) & 0x0F) << 20) +#define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F) +#define C_028C10_S10_Y 0xFF0FFFFF +#define S_028C10_S11_X(x) (((x) & 0x0F) << 24) +#define G_028C10_S11_X(x) (((x) >> 24) & 0x0F) +#define C_028C10_S11_X 0xF0FFFFFF +#define S_028C10_S11_Y(x) (((x) & 0x0F) << 28) +#define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F) +#define C_028C10_S11_Y 0x0FFFFFFF +#define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14 +#define S_028C14_S12_X(x) (((x) & 0x0F) << 0) +#define G_028C14_S12_X(x) (((x) >> 0) & 0x0F) +#define C_028C14_S12_X 0xFFFFFFF0 +#define S_028C14_S12_Y(x) (((x) & 0x0F) << 4) +#define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F) +#define C_028C14_S12_Y 0xFFFFFF0F +#define S_028C14_S13_X(x) (((x) & 0x0F) << 8) +#define G_028C14_S13_X(x) (((x) >> 8) & 0x0F) +#define C_028C14_S13_X 0xFFFFF0FF +#define S_028C14_S13_Y(x) (((x) & 0x0F) << 12) +#define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F) +#define C_028C14_S13_Y 0xFFFF0FFF +#define S_028C14_S14_X(x) (((x) & 0x0F) << 16) +#define G_028C14_S14_X(x) (((x) >> 16) & 0x0F) +#define C_028C14_S14_X 0xFFF0FFFF +#define S_028C14_S14_Y(x) (((x) & 0x0F) << 20) +#define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F) +#define C_028C14_S14_Y 0xFF0FFFFF +#define S_028C14_S15_X(x) (((x) & 0x0F) << 24) +#define G_028C14_S15_X(x) (((x) >> 24) & 0x0F) +#define C_028C14_S15_X 0xF0FFFFFF +#define S_028C14_S15_Y(x) (((x) & 0x0F) << 28) +#define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F) +#define C_028C14_S15_Y 0x0FFFFFFF +#define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18 +#define S_028C18_S0_X(x) (((x) & 0x0F) << 0) +#define G_028C18_S0_X(x) (((x) >> 0) & 0x0F) +#define C_028C18_S0_X 0xFFFFFFF0 +#define S_028C18_S0_Y(x) (((x) & 0x0F) << 4) +#define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F) +#define C_028C18_S0_Y 0xFFFFFF0F +#define S_028C18_S1_X(x) (((x) & 0x0F) << 8) +#define G_028C18_S1_X(x) (((x) >> 8) & 0x0F) +#define C_028C18_S1_X 0xFFFFF0FF +#define S_028C18_S1_Y(x) (((x) & 0x0F) << 12) +#define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F) +#define C_028C18_S1_Y 0xFFFF0FFF +#define S_028C18_S2_X(x) (((x) & 0x0F) << 16) +#define G_028C18_S2_X(x) (((x) >> 16) & 0x0F) +#define C_028C18_S2_X 0xFFF0FFFF +#define S_028C18_S2_Y(x) (((x) & 0x0F) << 20) +#define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F) +#define C_028C18_S2_Y 0xFF0FFFFF +#define S_028C18_S3_X(x) (((x) & 0x0F) << 24) +#define G_028C18_S3_X(x) (((x) >> 24) & 0x0F) +#define C_028C18_S3_X 0xF0FFFFFF +#define S_028C18_S3_Y(x) (((x) & 0x0F) << 28) +#define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F) +#define C_028C18_S3_Y 0x0FFFFFFF +#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C +#define S_028C1C_S4_X(x) (((x) & 0x0F) << 0) +#define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F) +#define C_028C1C_S4_X 0xFFFFFFF0 +#define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4) +#define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F) +#define C_028C1C_S4_Y 0xFFFFFF0F +#define S_028C1C_S5_X(x) (((x) & 0x0F) << 8) +#define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F) +#define C_028C1C_S5_X 0xFFFFF0FF +#define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12) +#define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F) +#define C_028C1C_S5_Y 0xFFFF0FFF +#define S_028C1C_S6_X(x) (((x) & 0x0F) << 16) +#define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F) +#define C_028C1C_S6_X 0xFFF0FFFF +#define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20) +#define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F) +#define C_028C1C_S6_Y 0xFF0FFFFF +#define S_028C1C_S7_X(x) (((x) & 0x0F) << 24) +#define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F) +#define C_028C1C_S7_X 0xF0FFFFFF +#define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28) +#define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F) +#define C_028C1C_S7_Y 0x0FFFFFFF +#define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20 +#define S_028C20_S8_X(x) (((x) & 0x0F) << 0) +#define G_028C20_S8_X(x) (((x) >> 0) & 0x0F) +#define C_028C20_S8_X 0xFFFFFFF0 +#define S_028C20_S8_Y(x) (((x) & 0x0F) << 4) +#define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F) +#define C_028C20_S8_Y 0xFFFFFF0F +#define S_028C20_S9_X(x) (((x) & 0x0F) << 8) +#define G_028C20_S9_X(x) (((x) >> 8) & 0x0F) +#define C_028C20_S9_X 0xFFFFF0FF +#define S_028C20_S9_Y(x) (((x) & 0x0F) << 12) +#define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F) +#define C_028C20_S9_Y 0xFFFF0FFF +#define S_028C20_S10_X(x) (((x) & 0x0F) << 16) +#define G_028C20_S10_X(x) (((x) >> 16) & 0x0F) +#define C_028C20_S10_X 0xFFF0FFFF +#define S_028C20_S10_Y(x) (((x) & 0x0F) << 20) +#define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F) +#define C_028C20_S10_Y 0xFF0FFFFF +#define S_028C20_S11_X(x) (((x) & 0x0F) << 24) +#define G_028C20_S11_X(x) (((x) >> 24) & 0x0F) +#define C_028C20_S11_X 0xF0FFFFFF +#define S_028C20_S11_Y(x) (((x) & 0x0F) << 28) +#define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F) +#define C_028C20_S11_Y 0x0FFFFFFF +#define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24 +#define S_028C24_S12_X(x) (((x) & 0x0F) << 0) +#define G_028C24_S12_X(x) (((x) >> 0) & 0x0F) +#define C_028C24_S12_X 0xFFFFFFF0 +#define S_028C24_S12_Y(x) (((x) & 0x0F) << 4) +#define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F) +#define C_028C24_S12_Y 0xFFFFFF0F +#define S_028C24_S13_X(x) (((x) & 0x0F) << 8) +#define G_028C24_S13_X(x) (((x) >> 8) & 0x0F) +#define C_028C24_S13_X 0xFFFFF0FF +#define S_028C24_S13_Y(x) (((x) & 0x0F) << 12) +#define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F) +#define C_028C24_S13_Y 0xFFFF0FFF +#define S_028C24_S14_X(x) (((x) & 0x0F) << 16) +#define G_028C24_S14_X(x) (((x) >> 16) & 0x0F) +#define C_028C24_S14_X 0xFFF0FFFF +#define S_028C24_S14_Y(x) (((x) & 0x0F) << 20) +#define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F) +#define C_028C24_S14_Y 0xFF0FFFFF +#define S_028C24_S15_X(x) (((x) & 0x0F) << 24) +#define G_028C24_S15_X(x) (((x) >> 24) & 0x0F) +#define C_028C24_S15_X 0xF0FFFFFF +#define S_028C24_S15_Y(x) (((x) & 0x0F) << 28) +#define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F) +#define C_028C24_S15_Y 0x0FFFFFFF +#define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28 +#define S_028C28_S0_X(x) (((x) & 0x0F) << 0) +#define G_028C28_S0_X(x) (((x) >> 0) & 0x0F) +#define C_028C28_S0_X 0xFFFFFFF0 +#define S_028C28_S0_Y(x) (((x) & 0x0F) << 4) +#define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F) +#define C_028C28_S0_Y 0xFFFFFF0F +#define S_028C28_S1_X(x) (((x) & 0x0F) << 8) +#define G_028C28_S1_X(x) (((x) >> 8) & 0x0F) +#define C_028C28_S1_X 0xFFFFF0FF +#define S_028C28_S1_Y(x) (((x) & 0x0F) << 12) +#define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F) +#define C_028C28_S1_Y 0xFFFF0FFF +#define S_028C28_S2_X(x) (((x) & 0x0F) << 16) +#define G_028C28_S2_X(x) (((x) >> 16) & 0x0F) +#define C_028C28_S2_X 0xFFF0FFFF +#define S_028C28_S2_Y(x) (((x) & 0x0F) << 20) +#define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F) +#define C_028C28_S2_Y 0xFF0FFFFF +#define S_028C28_S3_X(x) (((x) & 0x0F) << 24) +#define G_028C28_S3_X(x) (((x) >> 24) & 0x0F) +#define C_028C28_S3_X 0xF0FFFFFF +#define S_028C28_S3_Y(x) (((x) & 0x0F) << 28) +#define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F) +#define C_028C28_S3_Y 0x0FFFFFFF +#define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C +#define S_028C2C_S4_X(x) (((x) & 0x0F) << 0) +#define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F) +#define C_028C2C_S4_X 0xFFFFFFF0 +#define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4) +#define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F) +#define C_028C2C_S4_Y 0xFFFFFF0F +#define S_028C2C_S5_X(x) (((x) & 0x0F) << 8) +#define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F) +#define C_028C2C_S5_X 0xFFFFF0FF +#define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12) +#define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F) +#define C_028C2C_S5_Y 0xFFFF0FFF +#define S_028C2C_S6_X(x) (((x) & 0x0F) << 16) +#define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F) +#define C_028C2C_S6_X 0xFFF0FFFF +#define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20) +#define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F) +#define C_028C2C_S6_Y 0xFF0FFFFF +#define S_028C2C_S7_X(x) (((x) & 0x0F) << 24) +#define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F) +#define C_028C2C_S7_X 0xF0FFFFFF +#define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28) +#define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F) +#define C_028C2C_S7_Y 0x0FFFFFFF +#define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30 +#define S_028C30_S8_X(x) (((x) & 0x0F) << 0) +#define G_028C30_S8_X(x) (((x) >> 0) & 0x0F) +#define C_028C30_S8_X 0xFFFFFFF0 +#define S_028C30_S8_Y(x) (((x) & 0x0F) << 4) +#define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F) +#define C_028C30_S8_Y 0xFFFFFF0F +#define S_028C30_S9_X(x) (((x) & 0x0F) << 8) +#define G_028C30_S9_X(x) (((x) >> 8) & 0x0F) +#define C_028C30_S9_X 0xFFFFF0FF +#define S_028C30_S9_Y(x) (((x) & 0x0F) << 12) +#define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F) +#define C_028C30_S9_Y 0xFFFF0FFF +#define S_028C30_S10_X(x) (((x) & 0x0F) << 16) +#define G_028C30_S10_X(x) (((x) >> 16) & 0x0F) +#define C_028C30_S10_X 0xFFF0FFFF +#define S_028C30_S10_Y(x) (((x) & 0x0F) << 20) +#define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F) +#define C_028C30_S10_Y 0xFF0FFFFF +#define S_028C30_S11_X(x) (((x) & 0x0F) << 24) +#define G_028C30_S11_X(x) (((x) >> 24) & 0x0F) +#define C_028C30_S11_X 0xF0FFFFFF +#define S_028C30_S11_Y(x) (((x) & 0x0F) << 28) +#define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F) +#define C_028C30_S11_Y 0x0FFFFFFF +#define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34 +#define S_028C34_S12_X(x) (((x) & 0x0F) << 0) +#define G_028C34_S12_X(x) (((x) >> 0) & 0x0F) +#define C_028C34_S12_X 0xFFFFFFF0 +#define S_028C34_S12_Y(x) (((x) & 0x0F) << 4) +#define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F) +#define C_028C34_S12_Y 0xFFFFFF0F +#define S_028C34_S13_X(x) (((x) & 0x0F) << 8) +#define G_028C34_S13_X(x) (((x) >> 8) & 0x0F) +#define C_028C34_S13_X 0xFFFFF0FF +#define S_028C34_S13_Y(x) (((x) & 0x0F) << 12) +#define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F) +#define C_028C34_S13_Y 0xFFFF0FFF +#define S_028C34_S14_X(x) (((x) & 0x0F) << 16) +#define G_028C34_S14_X(x) (((x) >> 16) & 0x0F) +#define C_028C34_S14_X 0xFFF0FFFF +#define S_028C34_S14_Y(x) (((x) & 0x0F) << 20) +#define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F) +#define C_028C34_S14_Y 0xFF0FFFFF +#define S_028C34_S15_X(x) (((x) & 0x0F) << 24) +#define G_028C34_S15_X(x) (((x) >> 24) & 0x0F) +#define C_028C34_S15_X 0xF0FFFFFF +#define S_028C34_S15_Y(x) (((x) & 0x0F) << 28) +#define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F) +#define C_028C34_S15_Y 0x0FFFFFFF +#define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38 +#define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0) +#define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF) +#define C_028C38_AA_MASK_X0Y0 0xFFFF0000 +#define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16) +#define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF) +#define C_028C38_AA_MASK_X1Y0 0x0000FFFF +#define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C +#define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0) +#define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF) +#define C_028C3C_AA_MASK_X0Y1 0xFFFF0000 +#define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16) +#define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF) +#define C_028C3C_AA_MASK_X1Y1 0x0000FFFF +#define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58 +#define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0) +#define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) +#define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00 +#define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C +#define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0) +#define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F) +#define C_028C5C_DEALLOC_DIST 0xFFFFFF80 +#define R_028C60_CB_COLOR0_BASE 0x028C60 +#define R_028C64_CB_COLOR0_PITCH 0x028C64 +#define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0) +#define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF) +#define C_028C64_TILE_MAX 0xFFFFF800 +#define R_028C68_CB_COLOR0_SLICE 0x028C68 +#define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) +#define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) +#define C_028C68_TILE_MAX 0xFFC00000 +#define R_028C6C_CB_COLOR0_VIEW 0x028C6C +#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028C6C_SLICE_START 0xFFFFF800 +#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028C6C_SLICE_MAX 0xFF001FFF +#define R_028C70_CB_COLOR0_INFO 0x028C70 +#define S_028C70_ENDIAN(x) (((x) & 0x03) << 0) +#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03) +#define C_028C70_ENDIAN 0xFFFFFFFC +#define V_028C70_ENDIAN_NONE 0x00 +#define V_028C70_ENDIAN_8IN16 0x01 +#define V_028C70_ENDIAN_8IN32 0x02 +#define V_028C70_ENDIAN_8IN64 0x03 +#define S_028C70_FORMAT(x) (((x) & 0x1F) << 2) +#define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F) +#define C_028C70_FORMAT 0xFFFFFF83 +#define V_028C70_COLOR_INVALID 0x00 +#define V_028C70_COLOR_8 0x01 +#define V_028C70_COLOR_16 0x02 +#define V_028C70_COLOR_8_8 0x03 +#define V_028C70_COLOR_32 0x04 +#define V_028C70_COLOR_16_16 0x05 +#define V_028C70_COLOR_10_11_11 0x06 +#define V_028C70_COLOR_11_11_10 0x07 +#define V_028C70_COLOR_10_10_10_2 0x08 +#define V_028C70_COLOR_2_10_10_10 0x09 +#define V_028C70_COLOR_8_8_8_8 0x0A +#define V_028C70_COLOR_32_32 0x0B +#define V_028C70_COLOR_16_16_16_16 0x0C +#define V_028C70_COLOR_32_32_32_32 0x0E +#define V_028C70_COLOR_5_6_5 0x10 +#define V_028C70_COLOR_1_5_5_5 0x11 +#define V_028C70_COLOR_5_5_5_1 0x12 +#define V_028C70_COLOR_4_4_4_4 0x13 +#define V_028C70_COLOR_8_24 0x14 +#define V_028C70_COLOR_24_8 0x15 +#define V_028C70_COLOR_X24_8_32_FLOAT 0x16 +#define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7) +#define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1) +#define C_028C70_LINEAR_GENERAL 0xFFFFFF7F +#define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8) +#define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07) +#define C_028C70_NUMBER_TYPE 0xFFFFF8FF +#define V_028C70_NUMBER_UNORM 0x00 +#define V_028C70_NUMBER_SNORM 0x01 +#define V_028C70_NUMBER_UINT 0x04 +#define V_028C70_NUMBER_SINT 0x05 +#define V_028C70_NUMBER_SRGB 0x06 +#define V_028C70_NUMBER_FLOAT 0x07 +#define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11) +#define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03) +#define C_028C70_COMP_SWAP 0xFFFFE7FF +#define V_028C70_SWAP_STD 0x00 +#define V_028C70_SWAP_ALT 0x01 +#define V_028C70_SWAP_STD_REV 0x02 +#define V_028C70_SWAP_ALT_REV 0x03 +#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13) +#define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1) +#define C_028C70_FAST_CLEAR 0xFFFFDFFF +#define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14) +#define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1) +#define C_028C70_COMPRESSION 0xFFFFBFFF +#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15) +#define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1) +#define C_028C70_BLEND_CLAMP 0xFFFF7FFF +#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16) +#define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1) +#define C_028C70_BLEND_BYPASS 0xFFFEFFFF +#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17) +#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1) +#define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF +#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18) +#define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1) +#define C_028C70_ROUND_MODE 0xFFFBFFFF +#define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19) +#define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1) +#define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF +#define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20) +#define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07) +#define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF +#define V_028C70_FORCE_OPT_AUTO 0x00 +#define V_028C70_FORCE_OPT_DISABLE 0x01 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 +#define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23) +#define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07) +#define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF +#define V_028C70_FORCE_OPT_AUTO 0x00 +#define V_028C70_FORCE_OPT_DISABLE 0x01 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 +#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 +#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 +#define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0) +#define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F) +#define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0 +#define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5) +#define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F) +#define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F +#define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12) +#define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07) +#define C_028C74_NUM_SAMPLES 0xFFFF8FFF +#define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15) +#define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03) +#define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF +#define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17) +#define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1) +#define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF +#define R_028C7C_CB_COLOR0_CMASK 0x028C7C +#define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80 +#define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0) +#define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF) +#define C_028C80_TILE_MAX 0xFFFFC000 +#define R_028C84_CB_COLOR0_FMASK 0x028C84 +#define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88 +#define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) +#define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) +#define C_028C88_TILE_MAX 0xFFC00000 +#define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C +#define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90 +#define R_028C9C_CB_COLOR1_BASE 0x028C9C +#define R_028CA0_CB_COLOR1_PITCH 0x028CA0 +#define R_028CA4_CB_COLOR1_SLICE 0x028CA4 +#define R_028CA8_CB_COLOR1_VIEW 0x028CA8 +#define R_028CAC_CB_COLOR1_INFO 0x028CAC +#define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0 +#define R_028CD4_CB_COLOR1_CMASK 0x028CB8 +#define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC +#define R_028CC0_CB_COLOR1_FMASK 0x028CC0 +#define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4 +#define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8 +#define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC +#define R_028CD8_CB_COLOR2_BASE 0x028CD8 +#define R_028CDC_CB_COLOR2_PITCH 0x028CDC +#define R_028CE0_CB_COLOR2_SLICE 0x028CE0 +#define R_028CE4_CB_COLOR2_VIEW 0x028CE4 +#define R_028CE8_CB_COLOR2_INFO 0x028CE8 +#define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC +#define R_028CF4_CB_COLOR2_CMASK 0x028CF4 +#define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8 +#define R_028CFC_CB_COLOR2_FMASK 0x028CFC +#define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00 +#define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04 +#define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08 +#define R_028D14_CB_COLOR3_BASE 0x028D14 +#define R_028D18_CB_COLOR3_PITCH 0x028D18 +#define R_028D1C_CB_COLOR3_SLICE 0x028D1C +#define R_028D20_CB_COLOR3_VIEW 0x028D20 +#define R_028D24_CB_COLOR3_INFO 0x028D24 +#define R_028D28_CB_COLOR3_ATTRIB 0x028D28 +#define R_028D30_CB_COLOR3_CMASK 0x028D30 +#define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34 +#define R_028D38_CB_COLOR3_FMASK 0x028D38 +#define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C +#define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40 +#define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44 +#define R_028D50_CB_COLOR4_BASE 0x028D50 +#define R_028D54_CB_COLOR4_PITCH 0x028D54 +#define R_028D58_CB_COLOR4_SLICE 0x028D58 +#define R_028D5C_CB_COLOR4_VIEW 0x028D5C +#define R_028D60_CB_COLOR4_INFO 0x028D60 +#define R_028D64_CB_COLOR4_ATTRIB 0x028D64 +#define R_028D6C_CB_COLOR4_CMASK 0x028D6C +#define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70 +#define R_028D74_CB_COLOR4_FMASK 0x028D74 +#define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78 +#define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C +#define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80 +#define R_028D8C_CB_COLOR5_BASE 0x028D8C +#define R_028D90_CB_COLOR5_PITCH 0x028D90 +#define R_028D94_CB_COLOR5_SLICE 0x028D94 +#define R_028D98_CB_COLOR5_VIEW 0x028D98 +#define R_028D9C_CB_COLOR5_INFO 0x028D9C +#define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0 +#define R_028DA8_CB_COLOR5_CMASK 0x028DA8 +#define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC +#define R_028DB0_CB_COLOR5_FMASK 0x028DB0 +#define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4 +#define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8 +#define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC +#define R_028DC8_CB_COLOR6_BASE 0x028DC8 +#define R_028DCC_CB_COLOR6_PITCH 0x028DCC +#define R_028DD0_CB_COLOR6_SLICE 0x028DD0 +#define R_028DD4_CB_COLOR6_VIEW 0x028DD4 +#define R_028DD8_CB_COLOR6_INFO 0x028DD8 +#define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC +#define R_028DE4_CB_COLOR6_CMASK 0x028DE4 +#define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8 +#define R_028DEC_CB_COLOR6_FMASK 0x028DEC +#define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0 +#define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4 +#define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8 +#define R_028E04_CB_COLOR7_BASE 0x028E04 +#define R_028E08_CB_COLOR7_PITCH 0x028E08 +#define R_028E0C_CB_COLOR7_SLICE 0x028E0C +#define R_028E10_CB_COLOR7_VIEW 0x028E10 +#define R_028E14_CB_COLOR7_INFO 0x028E14 +#define R_028E18_CB_COLOR7_ATTRIB 0x028E18 +#define R_028E20_CB_COLOR7_CMASK 0x028E20 +#define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24 +#define R_028E28_CB_COLOR7_FMASK 0x028E28 +#define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C +#define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30 +#define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34 + +#endif /* _SID_H */ + |