diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2017-09-08 19:08:21 -0700 |
|---|---|---|
| committer | Rafael Antognolli <rafael.antognolli@intel.com> | 2019-10-30 19:51:03 +0000 |
| commit | f573cd4757355c5ffe66c90ad6e08265865ec730 (patch) | |
| tree | a4735503e4907a52829df187d7fcfaf59f7d9935 | |
| parent | 86786999189c43b4a2c8e1c1a18b55cd2f369fff (diff) | |
intel/genxml: Add gen12 tile cache flush bit
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/intel/genxml/gen12.xml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 98e75c24b43..98fbf7d9180 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6364,6 +6364,7 @@ <value name="GGTT" value="1"/> </field> <field name="Flush LLC" start="58" end="58" type="bool"/> + <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/> <field name="Address" start="66" end="111" type="address"/> <field name="Immediate Data" start="128" end="191" type="uint"/> </instruction> |