diff options
author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2021-09-29 09:46:46 +0200 |
---|---|---|
committer | Marge Bot <eric+marge@anholt.net> | 2021-10-01 07:26:37 +0000 |
commit | f07e67272e8fd9690a7804e9c407a83a7c2b36f4 (patch) | |
tree | d422c79d4e6d1e39288ee2c315435b019bcfa8c6 | |
parent | 16378837db810bbb6b4923ac1016f4ccb43a1a7f (diff) |
radv: fix vk_object_base_init/finish for internal image views
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13102>
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_image.c | 12 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_blit.c | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_blit2d.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_bufimage.c | 7 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 11 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_copy_vrs_htile.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_decompress.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fmask_expand.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve_cs.c | 6 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve_fs.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
14 files changed, 58 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ac745683f00..3cfc12d8582 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2524,6 +2524,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, htile_buffer->bo); radv_emit_fb_ds_state(cmd_buffer, &ds, &iview, layout, false); + + radv_image_view_finish(&iview); } else { if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 6369b08ffe8..57459a36727 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1918,6 +1918,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange; uint32_t plane_count = 1; + vk_object_base_init(&device->vk, &iview->base, VK_OBJECT_TYPE_IMAGE_VIEW); + switch (image->type) { case VK_IMAGE_TYPE_1D: case VK_IMAGE_TYPE_2D: @@ -2053,6 +2055,12 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, } } +void +radv_image_view_finish(struct radv_image_view *iview) +{ + vk_object_base_finish(&iview->base); +} + bool radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image, VkImageLayout layout, bool in_render_loop, unsigned queue_mask) @@ -2302,8 +2310,6 @@ radv_CreateImageView(VkDevice _device, const VkImageViewCreateInfo *pCreateInfo, if (view == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); - vk_object_base_init(&device->vk, &view->base, VK_OBJECT_TYPE_IMAGE_VIEW); - radv_image_view_init(view, device, pCreateInfo, NULL); *pView = radv_image_view_to_handle(view); @@ -2320,7 +2326,7 @@ radv_DestroyImageView(VkDevice _device, VkImageView _iview, const VkAllocationCa if (!iview) return; - vk_object_base_finish(&iview->base); + radv_image_view_finish(iview); vk_free2(&device->vk.alloc, pAllocator, iview); } diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c index 03a4912f033..0c13e158298 100644 --- a/src/amd/vulkan/radv_meta_blit.c +++ b/src/amd/vulkan/radv_meta_blit.c @@ -613,6 +613,9 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, meta_emit_blit(cmd_buffer, src_image, &src_iview, src_image_layout, src_offset_0, src_offset_1, dst_image, &dst_iview, dst_image_layout, dst_offset_0, dst_offset_1, dst_box, sampler); + + radv_image_view_finish(&dst_iview); + radv_image_view_finish(&src_iview); } /* Restore conditional rendering. */ diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c index baa2fc55815..8ebc6c82aca 100644 --- a/src/amd/vulkan/radv_meta_blit2d.c +++ b/src/amd/vulkan/radv_meta_blit2d.c @@ -398,6 +398,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer, if (src_type == BLIT2D_SRC_TYPE_BUFFER) radv_buffer_view_finish(&src_temps.bview); + else + radv_image_view_finish(&dst_temps.iview); + + radv_image_view_finish(&dst_temps.iview); } } } diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index b6e86d490b0..ce13aeea708 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -1463,6 +1463,7 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_b radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } + radv_image_view_finish(&src_view); radv_buffer_view_finish(&dst_view); } @@ -1616,6 +1617,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } + radv_image_view_finish(&dst_view); radv_buffer_view_finish(&src_view); } @@ -1783,6 +1785,9 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } + + radv_image_view_finish(&src_view); + radv_image_view_finish(&dst_view); } } @@ -1911,4 +1916,6 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl push_constants); radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1); + + radv_image_view_finish(&dst_iview); } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 2fd99c0dbb6..ee8aa99abbd 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1617,6 +1617,8 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants); radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, layer_count); + + radv_image_view_finish(&iview); } radv_meta_restore(&saved_state, cmd_buffer); @@ -2259,6 +2261,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false); + radv_image_view_finish(&iview); radv_cmd_buffer_end_render_pass(cmd_buffer); radv_DestroyRenderPass(device_h, pass, &cmd_buffer->pool->alloc); radv_DestroyFramebuffer(device_h, fb, &cmd_buffer->pool->alloc); @@ -2273,6 +2276,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima const VkImageSubresourceRange *range, const VkClearValue *clear_val) { struct radv_image_view iview; + bool fast_cleared = false; radv_image_view_init(&iview, cmd_buffer->device, &(VkImageViewCreateInfo){ @@ -2316,18 +2320,19 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima clear_att.clearValue.color, 0)) { radv_fast_clear_color(cmd_buffer, &iview, &clear_att, clear_att.colorAttachment, NULL, NULL); - return true; + fast_cleared = true; } } else { if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout, in_render_loop, range->aspectMask, &clear_rect, clear_att.clearValue.depthStencil, 0)) { radv_fast_clear_depth(cmd_buffer, &iview, &clear_att, NULL, NULL); - return true; + fast_cleared = true; } } - return false; + radv_image_view_finish(&iview); + return fast_cleared; } static void diff --git a/src/amd/vulkan/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/radv_meta_copy_vrs_htile.c index ad89967b0be..27a6faba537 100644 --- a/src/amd/vulkan/radv_meta_copy_vrs_htile.c +++ b/src/amd/vulkan/radv_meta_copy_vrs_htile.c @@ -303,6 +303,8 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i radv_unaligned_dispatch(cmd_buffer, width, height, 1); + radv_image_view_finish(&vrs_iview); + radv_meta_restore(&saved_state, cmd_buffer); cmd_buffer->state.flush_bits |= diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c index 08c7f2d0a85..91d1d04c6b3 100644 --- a/src/amd/vulkan/radv_meta_decompress.c +++ b/src/amd/vulkan/radv_meta_decompress.c @@ -541,6 +541,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_cmd_buffer_end_render_pass(cmd_buffer); + radv_image_view_finish(&iview); radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h, &cmd_buffer->pool->alloc); } @@ -700,6 +701,9 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad }}}); radv_unaligned_dispatch(cmd_buffer, width, height, 1); + + radv_image_view_finish(&load_iview); + radv_image_view_finish(&store_iview); } } diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index 0c257e8085d..0293a7e63e5 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -622,6 +622,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i radv_cmd_buffer_end_render_pass(cmd_buffer); + radv_image_view_finish(&iview); radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h, &cmd_buffer->pool->alloc); } @@ -895,6 +896,9 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag }}}); radv_unaligned_dispatch(cmd_buffer, width, height, 1); + + radv_image_view_finish(&load_iview); + radv_image_view_finish(&store_iview); } } diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c index a6acfdd8d2a..0ac11d547f3 100644 --- a/src/amd/vulkan/radv_meta_fmask_expand.c +++ b/src/amd/vulkan/radv_meta_fmask_expand.c @@ -165,6 +165,8 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_ radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, layer_count); + radv_image_view_finish(&iview); + radv_meta_restore(&saved_state, cmd_buffer); cmd_buffer->state.flush_bits |= diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index c9ac73eb336..e6b82418dfc 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -600,6 +600,8 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv radv_cmd_buffer_end_render_pass(cmd_buffer); + radv_image_view_finish(&src_iview); + radv_image_view_finish(&dst_iview); radv_DestroyFramebuffer(radv_device_to_handle(device), fb_h, &cmd_buffer->pool->alloc); } diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 65cbc15f9d2..69ecb6cd208 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -758,6 +758,9 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_ emit_resolve(cmd_buffer, &src_iview, &dest_iview, &(VkOffset2D){srcOffset.x, srcOffset.y}, &(VkOffset2D){dstOffset.x, dstOffset.y}, &(VkExtent2D){extent.width, extent.height}); + + radv_image_view_finish(&src_iview); + radv_image_view_finish(&dest_iview); } radv_meta_restore(&saved_state, cmd_buffer); @@ -945,5 +948,8 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer, cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value); } + radv_image_view_finish(&tsrc_iview); + radv_image_view_finish(&tdst_iview); + radv_meta_restore(&saved_state, cmd_buffer); } diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c index 1ff271b567a..4d8d6a17e12 100644 --- a/src/amd/vulkan/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/radv_meta_resolve_fs.c @@ -1053,6 +1053,8 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv radv_cmd_buffer_end_render_pass(cmd_buffer); + radv_image_view_finish(&src_iview); + radv_image_view_finish(&dest_iview); radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc); } @@ -1181,5 +1183,7 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer, radv_cmd_buffer_set_subpass(cmd_buffer, subpass); + radv_image_view_finish(&tsrc_iview); + radv_meta_restore(&saved_state, cmd_buffer); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 1d48461ec30..2b24a69ea8e 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2298,6 +2298,7 @@ struct radv_image_view_extra_create_info { void radv_image_view_init(struct radv_image_view *view, struct radv_device *device, const VkImageViewCreateInfo *pCreateInfo, const struct radv_image_view_extra_create_info *extra_create_info); +void radv_image_view_finish(struct radv_image_view *iview); VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask); 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