diff options
| author | Antia Puentes <apuentes@igalia.com> | 2015-06-16 22:30:16 +0200 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-08-03 09:40:48 -0700 |
| commit | ef1b30ae637e613b384541324c199d2dbe6b44bd (patch) | |
| tree | cc8c7df811f96ce182a69b3b599352689061c4a4 | |
| parent | 168bbfa6ff22a586ad6307c187cfa3b8fff5f227 (diff) | |
i965/nir/vec4: Prepare source and destination registers for ALU operations
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index bc5ebbea98e..46bfd3b81d9 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -646,10 +646,27 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) } } +static unsigned +brw_swizzle_for_nir_swizzle(uint8_t swizzle[4]) +{ + return BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]); +} + void vec4_visitor::nir_emit_alu(nir_alu_instr *instr) { - /* @TODO: Not yet implemented */ + dst_reg dst = get_nir_dest(instr->dest.dest, + nir_op_infos[instr->op].output_type); + dst.writemask = instr->dest.write_mask; + + src_reg op[4]; + for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { + op[i] = get_nir_src(instr->src[i].src, + nir_op_infos[instr->op].input_types[i], 4); + op[i].swizzle = brw_swizzle_for_nir_swizzle(instr->src[i].swizzle); + op[i].abs = instr->src[i].abs; + op[i].negate = instr->src[i].negate; + } } void |