diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2022-02-18 03:02:53 -0800 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-02-24 21:42:16 +0000 |
| commit | e6b7e743083f5f71ff004b3c753e07e482c815d7 (patch) | |
| tree | 6212a53d2021744893200712225f85a93f8a4d9b | |
| parent | c393753daa4de92f3a5937cc4abd53881efa098a (diff) | |
iris: Set MI_FLUSH_DW::PostSyncOperation correctly
The MI_FLUSH_DW post-sync operation uses the same encoding as the
PIPE_CONTROL one so we can use the same helper. Write PS Depth Count
is not supported, of course, as the blitter has no depth pipeline.
This means that we can write the timestamp register from the blitter.
Fixes: 604d97671b6 ("iris: Add support for flushing the blitter (hackily)")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15157>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 5a91d4d55cc..e09f542c090 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -7666,6 +7666,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, batch_mark_sync_for_pipe_control(batch, flags); iris_batch_sync_region_start(batch); + assert(!(flags & PIPE_CONTROL_WRITE_DEPTH_COUNT)); + /* The blitter doesn't actually use PIPE_CONTROL; rather it uses the * MI_FLUSH_DW command. However, all of our code is set up to flush * via emitting a pipe control, so we just translate it at this point, @@ -7674,6 +7676,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, iris_emit_cmd(batch, GENX(MI_FLUSH_DW), fd) { fd.Address = rw_bo(bo, offset, IRIS_DOMAIN_OTHER_WRITE); fd.ImmediateData = imm; + fd.PostSyncOperation = flags_to_post_sync_op(flags); #if GFX_VERx10 >= 125 /* TODO: This may not always be necessary */ fd.FlushCCS = true; |