r600g: use uint64_t instead of unsigned long for proper 32bits cpu support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

5 files changed, 16 insertions, 16 deletions

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index ca4f4b3bdf4..bb4753062e5 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -243,9 +243,9 @@ void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_en
 void evergreen_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
-		unsigned long src_offset,
-		unsigned long size)
+		uint64_t dst_offset,
+		uint64_t src_offset,
+		uint64_t size)
 {
 	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 	unsigned i, ncopy, csize, sub_cmd, shift;
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index be1c427ce29..0a3861f30f3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3481,7 +3481,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
 	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 	unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
 	unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
-	unsigned long base, addr;
+	uint64_t base, addr;
 
 	/* make sure that the dma ring is only one active */
 	rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3625,7 +3625,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
 	}
 
 	if (src_mode == dst_mode) {
-		unsigned long dst_offset, src_offset;
+		uint64_t dst_offset, src_offset;
 		/* simple dma blit would do NOTE code here assume :
 		 *   src_box.x/y == 0
 		 *   dst_x/y == 0
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index a383c908f64..08b77e4fedd 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -174,9 +174,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
 void r600_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
-		unsigned long src_offset,
-		unsigned long size);
+		uint64_t dst_offset,
+		uint64_t src_offset,
+		uint64_t size);
 boolean r600_dma_blit(struct pipe_context *ctx,
 			struct pipe_resource *dst,
 			unsigned dst_level,
@@ -187,9 +187,9 @@ boolean r600_dma_blit(struct pipe_context *ctx,
 void evergreen_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
-		unsigned long src_offset,
-		unsigned long size);
+		uint64_t dst_offset,
+		uint64_t src_offset,
+		uint64_t size);
 boolean evergreen_dma_blit(struct pipe_context *ctx,
 			struct pipe_resource *dst,
 			unsigned dst_level,
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index ebafd9777d8..23f488a5e7c 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1160,9 +1160,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
 void r600_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
-		unsigned long src_offset,
-		unsigned long size)
+		uint64_t dst_offset,
+		uint64_t src_offset,
+		uint64_t size)
 {
 	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 	unsigned i, ncopy, csize, shift;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6b4b2c3819a..c0bc2a5b9c1 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2979,7 +2979,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
 	struct r600_texture *rdst = (struct r600_texture*)dst;
 	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 	unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
-	unsigned long base, addr;
+	uint64_t base, addr;
 
 	/* make sure that the dma ring is only one active */
 	rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3109,7 +3109,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
 	}
 
 	if (src_mode == dst_mode) {
-		unsigned long dst_offset, src_offset, size;
+		uint64_t dst_offset, src_offset, size;
 
 		/* simple dma blit would do NOTE code here assume :
 		 *   src_box.x/y == 0