diff options
| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2021-03-09 03:22:45 +0100 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-04-08 22:29:12 +0000 |
| commit | dece117fdc2d1a1aaa95a9b445dcc214bc017c45 (patch) | |
| tree | 9f6e2b10c523cf0fad65ceb7a09c9a75fcb5e7b7 | |
| parent | b61efd53b464615c084763d9dfff8eda07afbe3a (diff) | |
radv: Support DCC without DCC/FCE predicates.
Imported images can't have this as part of the associated memory.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 11 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 6 |
2 files changed, 12 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3e01bfc63ef..1f98414bae1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2116,13 +2116,14 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, bool value) { + if (!image->fce_pred_offset) + return; + uint64_t pred_val = value; uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel); uint32_t level_count = radv_get_levelCount(image, range); uint32_t count = 2 * level_count; - assert(image->fce_pred_offset != 0); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | @@ -2144,6 +2145,9 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, bool value) { + if (image->dcc_pred_offset == 0) + return; + uint64_t pred_val = value; uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel); uint32_t level_count = radv_get_levelCount(image, range); @@ -2151,9 +2155,6 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, assert(radv_dcc_enabled(image, range->baseMipLevel)); - if (image->dcc_pred_offset == 0) - return; - radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index de86a68b7d0..6c80e66b38c 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2043,6 +2043,8 @@ static inline uint64_t radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level) { + assert(image->fce_pred_offset != 0); + uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->fce_pred_offset + base_level * 8; return va; @@ -2052,6 +2054,8 @@ static inline uint64_t radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level) { + assert(image->dcc_pred_offset != 0); + uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->dcc_pred_offset + base_level * 8; return va; @@ -2061,6 +2065,8 @@ static inline uint64_t radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level) { + assert(image->tc_compat_zrange_offset != 0); + uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->tc_compat_zrange_offset + base_level * 4; return va; |