intel/compiler: Remove surface_idx from brw_image_param

Now that the drivers are lowering to surface indices themselves, we no
longer need to push the surface index into the shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

6 files changed, 9 insertions, 29 deletions

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index c510d34ce2e..d8c9499065f 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -434,18 +434,14 @@ union brw_any_prog_key {
  * entries [most of them except when we're doing untyped surface
  * access] will be removed by the uniform packing pass.
  */
-#define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET      0
-#define BRW_IMAGE_PARAM_OFFSET_OFFSET           4
-#define BRW_IMAGE_PARAM_SIZE_OFFSET             8
-#define BRW_IMAGE_PARAM_STRIDE_OFFSET           12
-#define BRW_IMAGE_PARAM_TILING_OFFSET           16
-#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        20
-#define BRW_IMAGE_PARAM_SIZE                    24
+#define BRW_IMAGE_PARAM_OFFSET_OFFSET           0
+#define BRW_IMAGE_PARAM_SIZE_OFFSET             4
+#define BRW_IMAGE_PARAM_STRIDE_OFFSET           8
+#define BRW_IMAGE_PARAM_TILING_OFFSET           12
+#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        16
+#define BRW_IMAGE_PARAM_SIZE                    20
 
 struct brw_image_param {
-   /** Surface binding table index. */
-   uint32_t surface_idx;
-
    /** Offset applied to the X and Y surface coordinates. */
    uint32_t offset[2];
 
diff --git a/src/intel/compiler/brw_nir_lower_image_load_store.c b/src/intel/compiler/brw_nir_lower_image_load_store.c
index e8e00e1aa19..de6f7683be4 100644
--- a/src/intel/compiler/brw_nir_lower_image_load_store.c
+++ b/src/intel/compiler/brw_nir_lower_image_load_store.c
@@ -91,9 +91,6 @@ _load_image_param(nir_builder *b, nir_deref_instr *deref, unsigned offset)
    nir_intrinsic_set_base(load, offset / 4);
 
    switch (offset) {
-   case BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET:
-      load->num_components = 1;
-      break;
    case BRW_IMAGE_PARAM_OFFSET_OFFSET:
    case BRW_IMAGE_PARAM_SWIZZLING_OFFSET:
       load->num_components = 2;
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 583b5a17cc6..856101cc2ff 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -527,8 +527,6 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       struct anv_push_constants *null_data = NULL;
       const struct brw_image_param *image_param = null_data->images;
       for (uint32_t i = 0; i < map->image_count; i++) {
-         setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
-                                  (uintptr_t)&image_param->surface_idx, 1);
          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
                                   (uintptr_t)image_param->offset, 2);
          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index b7ed817d3a0..16168d415c3 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2109,7 +2109,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
             &cmd_buffer->state.push_constants[stage]->images[image++];
 
          *image_param = desc->image_view->planes[binding->plane].storage_image_param;
-         image_param->surface_idx = bias + s;
          break;
       }
 
@@ -2159,7 +2158,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
             &cmd_buffer->state.push_constants[stage]->images[image++];
 
          *image_param = desc->buffer_view->storage_image_param;
-         image_param->surface_idx = bias + s;
          break;
 
       default:
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 8a560d9bac1..0b028afdce7 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -93,9 +93,6 @@ brw_setup_image_uniform_values(gl_shader_stage stage,
       /* Upload the brw_image_param structure.  The order is expected to match
        * the BRW_IMAGE_PARAM_*_OFFSET defines.
        */
-      setup_vec4_image_param(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
-                             image_idx,
-                             offsetof(brw_image_param, surface_idx), 1);
       setup_vec4_image_param(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
                              image_idx,
                              offsetof(brw_image_param, offset), 2);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 35bb49f30f2..42af41aca32 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1474,11 +1474,9 @@ get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
 static void
 update_default_image_param(struct brw_context *brw,
                            struct gl_image_unit *u,
-                           unsigned surface_idx,
                            struct brw_image_param *param)
 {
    memset(param, 0, sizeof(*param));
-   param->surface_idx = surface_idx;
    /* Set the swizzling shifts to all-ones to effectively disable swizzling --
     * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
     * detailed explanation of these parameters.
@@ -1490,11 +1488,10 @@ update_default_image_param(struct brw_context *brw,
 static void
 update_buffer_image_param(struct brw_context *brw,
                           struct gl_image_unit *u,
-                          unsigned surface_idx,
                           struct brw_image_param *param)
 {
    const unsigned size = buffer_texture_range_size(brw, u->TexObj);
-   update_default_image_param(brw, u, surface_idx, param);
+   update_default_image_param(brw, u, param);
 
    param->size[0] = size / _mesa_get_format_bytes(u->_ActualFormat);
    param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
@@ -1516,7 +1513,6 @@ static void
 update_image_surface(struct brw_context *brw,
                      struct gl_image_unit *u,
                      GLenum access,
-                     unsigned surface_idx,
                      uint32_t *surf_offset,
                      struct brw_image_param *param)
 {
@@ -1538,7 +1534,7 @@ update_image_surface(struct brw_context *brw,
             format, buffer_size, texel_size,
             written ? RELOC_WRITE : 0);
 
-         update_buffer_image_param(brw, u, surface_idx, param);
+         update_buffer_image_param(brw, u, param);
 
       } else {
          struct intel_texture_object *intel_obj = intel_texture_object(obj);
@@ -1575,12 +1571,11 @@ update_image_surface(struct brw_context *brw,
          }
 
          isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view);
-         param->surface_idx = surface_idx;
       }
 
    } else {
       emit_null_surface_state(brw, NULL, surf_offset);
-      update_default_image_param(brw, u, surface_idx, param);
+      update_default_image_param(brw, u, param);
    }
 }
 
@@ -1599,7 +1594,6 @@ brw_upload_image_surfaces(struct brw_context *brw,
          const unsigned surf_idx = prog_data->binding_table.image_start + i;
 
          update_image_surface(brw, u, prog->sh.ImageAccess[i],
-                              surf_idx,
                               &stage_state->surf_offset[surf_idx],
                               &stage_state->image_param[i]);
       }