diff options
| author | Chris Forbes <chrisf@ijw.co.nz> | 2013-11-17 21:47:22 +1300 |
|---|---|---|
| committer | Chris Forbes <chrisf@ijw.co.nz> | 2014-07-13 10:01:17 +1200 |
| commit | d732598b63eb0cd103f06bccd99d13d732028d79 (patch) | |
| tree | ce0f89f49e2f5d8ec49244e717c7c870ef117efe | |
| parent | 0b0572a2ad4c7ca8b437589291e47180c733c371 (diff) | |
i965: add low-level support for send to pixel interpolator
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu.h | 10 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 |
2 files changed, 38 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 3164c80897d..63cb20b1a55 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -372,6 +372,16 @@ brw_untyped_surface_read(struct brw_compile *p, unsigned msg_length, unsigned response_length); +void +brw_pixel_interpolator_query(struct brw_compile *p, + struct brw_reg dest, + struct brw_reg mrf, + bool noperspective, + unsigned mode, + unsigned data, + unsigned msg_length, + unsigned response_length); + /*********************************************************************** * brw_eu_util.c: */ diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 3f00e4dc4a0..12424bde833 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2633,6 +2633,34 @@ brw_untyped_surface_read(struct brw_compile *p, brw_inst_access_mode(brw, insn) == BRW_ALIGN_1); } +void +brw_pixel_interpolator_query(struct brw_compile *p, + struct brw_reg dest, + struct brw_reg mrf, + bool noperspective, + unsigned mode, + unsigned data, + unsigned msg_length, + unsigned response_length) +{ + const struct brw_context *brw = p->brw; + struct brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); + + brw_set_dest(p, insn, dest); + brw_set_src0(p, insn, mrf); + brw_set_message_descriptor(p, insn, GEN7_SFID_PIXEL_INTERPOLATOR, + msg_length, response_length, + false /* header is never present for PI */, + false); + + brw_inst_set_pi_simd_mode( + brw, insn, brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16); + brw_inst_set_pi_slot_group(brw, insn, 0); /* zero unless 32/64px dispatch */ + brw_inst_set_pi_nopersp(brw, insn, noperspective); + brw_inst_set_pi_message_type(brw, insn, mode); + brw_inst_set_pi_message_data(brw, insn, data); +} + /** * This instruction is generated as a single-channel align1 instruction by * both the VS and FS stages when using INTEL_DEBUG=shader_time. |