diff options
| author | Xu,Randy <randy.xu@intel.com> | 2016-10-08 16:15:59 +0800 |
|---|---|---|
| committer | Tapani Pälli <tapani.palli@intel.com> | 2016-10-11 07:44:18 +0300 |
| commit | d11a63d6e69298f34bb08334f637c100f6989ca7 (patch) | |
| tree | cdbe82a5a48fda9b767da15b75bb159f714aac21 | |
| parent | 64435fd888ec5932024292d87b0afcecbe5fb818 (diff) | |
i965: solve cubemap negative x/y/z faces buffer offset issue in dEQP.
Add the miptree level/slice x/y_offset when count the surface offset
in brw_emit_surface_state. The surface offset has two parts, one is
from mt->offset, which should be 32 aligned in width/height for tiled
buffer; another is from mt->level[current_level].slice[current_slice].
x/y_offset.
This fix will solve 12 deqp failure
dEQP-EGL.functional.image.create.gles2_cubemap_negative_*_texture
Signed-off-by: Xu,Randy <randy.xu@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index c84fd5324df..b7742941aca 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -86,7 +86,8 @@ brw_emit_surface_state(struct brw_context *brw, unsigned read_domains, unsigned write_domains) { const struct surface_state_info ss_info = surface_state_infos[brw->gen]; - uint32_t tile_x = 0, tile_y = 0; + uint32_t tile_x = mt->level[0].slice[0].x_offset; + uint32_t tile_y = mt->level[0].slice[0].y_offset; uint32_t offset = mt->offset; struct isl_surf surf; @@ -109,6 +110,7 @@ brw_emit_surface_state(struct brw_context *brw, */ assert(brw->has_surface_tile_offset); assert(view.levels == 1 && view.array_len == 1); + assert(tile_x == 0 && tile_y == 0); offset += intel_miptree_get_tile_offsets(mt, view.base_level, view.base_array_layer, |