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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2022-02-16 17:15:01 -0800
committerMarge Bot <emma+marge@anholt.net>2022-02-22 22:16:57 +0000
commitd10fd5b7c9a695565c009c446882bed49bc20fdd (patch)
tree1c0577a6649335c2635dfb13560fa8b9b45bcdbb
parentc46d3acf0e3624f110c6d49f3eeef70fa1795855 (diff)
iris: fix register spilling on compute shaders on XeHP
XeHP scratch space is handled differently. Commit ae18e1e707c4 implemented support for it, but handled it differently between render and compute shaders: it calculates scratch_addr differently and doesn't pin the buffer on compute. Make it work on compute shaders by calling pin_scratch_space() from iris_compute_walker(), which fixes both the address and the pinning. This commit can be verified by the two-year-old-but-still-unreviewed Piglit MR 234. You can also verify this by running a very simple compute shader with INTEL_DEBUG=spill_fs. References: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/234 Fixes: ae18e1e707c4 ("iris: Add support for scratch on XeHP") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15070>
-rw-r--r--src/gallium/drivers/iris/iris_state.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 18929700014..5a91d4d55cc 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -7087,10 +7087,9 @@ iris_upload_compute_walker(struct iris_context *ice,
iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
cfe.MaximumNumberofThreads =
devinfo->max_cs_threads * devinfo->subslice_total - 1;
- if (prog_data->total_scratch > 0) {
- cfe.ScratchSpaceBuffer =
- iris_get_scratch_surf(ice, prog_data->total_scratch)->offset >> 4;
- }
+ uint32_t scratch_addr = pin_scratch_space(ice, batch, prog_data,
+ MESA_SHADER_COMPUTE);
+ cfe.ScratchSpaceBuffer = scratch_addr >> 4;
}
}