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| author | Marek Olšák <marek.olsak@amd.com> | 2021-03-19 17:41:59 -0400 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-04-02 12:05:00 +0000 |
| commit | cb59cae04c32c9ffaedd16e91d96fabbe7c9e3ea (patch) | |
| tree | aafc5ea1dc21f9f756586afbf7c960049f1c1257 | |
| parent | 8ea685dfc0d31fe0eeb127f3cb13307f34bc163b (diff) | |
radeonsi: set the clear/copy cache policy based on L2 cache size
This matches the intent.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute_blit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 16a8aebd06e..f1b09caaf45 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -37,7 +37,7 @@ static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_co coher == SI_COHERENCY_DB_META || coher == SI_COHERENCY_CP)) || (sctx->chip_class >= GFX7 && coher == SI_COHERENCY_SHADER)) - return size <= 256 * 1024 ? L2_LRU : L2_STREAM; + return size <= sctx->screen->info.l2_cache_size / 8 ? L2_LRU : L2_STREAM; return L2_BYPASS; } |