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authorKenneth Graunke <kenneth@whitecape.org>2014-07-17 14:33:15 -0700
committerKenneth Graunke <kenneth@whitecape.org>2014-08-13 21:19:07 -0700
commitc66d928f2c9fa59e162c391fbdd37df969959718 (patch)
tree83a64895eee0ed06ed5b9aabb6e09246b281f54f
parent24878f31c4287a6cc4cfd0fabc34075f9dad4e03 (diff)
i965: Enable INTDIV in SIMD16 mode.
All we need to do is decompose this to two SIMD8 instructions, like we do in many other cases. We even already have code for that. I apparently just botched this last time I tried, and it was easy. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp12
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp4
2 files changed, 2 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8405502f433..35ada42c508 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1404,18 +1404,6 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
int base_mrf = 2;
fs_inst *inst;
- switch (opcode) {
- case SHADER_OPCODE_INT_QUOTIENT:
- case SHADER_OPCODE_INT_REMAINDER:
- if (brw->gen >= 7)
- no16("SIMD16 INTDIV unsupported\n");
- break;
- case SHADER_OPCODE_POW:
- break;
- default:
- unreachable("not reached: unsupported binary math opcode.");
- }
-
if (brw->gen >= 8) {
inst = emit(opcode, dst, src0, src1);
} else if (brw->gen >= 6) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 9e260a7ffe7..1190f1f7e66 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1620,9 +1620,9 @@ fs_generator::generate_code(exec_list *instructions)
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
assert(brw->gen < 6 || inst->mlen == 0);
- if (brw->gen >= 7) {
+ if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
- } else if (brw->gen == 6) {
+ } else if (brw->gen >= 6) {
generate_math_gen6(inst, dst, src[0], src[1]);
} else {
generate_math_gen4(inst, dst, src[0]);