diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-06-23 19:02:32 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-06-23 19:13:55 +0200 |
| commit | c2f82fc1d3c401cf44fb94aa3ea531ca9cd0cb46 (patch) | |
| tree | cc6fd6926485b5b02503fa3b4ce91be417a301ee | |
| parent | 7f7487f262046616cf99ba665a83d1a8eae46503 (diff) | |
Revert "radeonsi: don't emit partial flushes at the end of IBs (v2)"
This reverts commit c9040dc9e75c81024f88f3f1bab821ad2bc73db3.
People have reported it causes corruption on VI, and I see GPU hangs
on GFX9.
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index 76b295f9ecd..345825af002 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -129,17 +129,13 @@ void si_context_gfx_flush(void *context, unsigned flags, r600_preflush_suspend_features(&ctx->b); + ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | + SI_CONTEXT_PS_PARTIAL_FLUSH; + /* DRM 3.1.0 doesn't flush TC for VI correctly. */ - if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) { - ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | - SI_CONTEXT_CS_PARTIAL_FLUSH | - SI_CONTEXT_INV_GLOBAL_L2 | + if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) + ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 | SI_CONTEXT_INV_VMEM_L1; - } else if (ctx->b.chip_class == SI) { - /* The kernel doesn't wait for idle before doing SURFACE_SYNC. */ - ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | - SI_CONTEXT_CS_PARTIAL_FLUSH; - } si_emit_cache_flush(ctx); |