diff options
| author | Rhys Perry <pendingchaos02@gmail.com> | 2022-02-04 19:02:54 +0000 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2022-02-09 20:07:50 +0000 |
| commit | c185f61e1bba028bd09f377ec72540e7a010f167 (patch) | |
| tree | 2dd5d74a621a3c9f82a275cd521d8bd4628d54b2 | |
| parent | 3cbc17121b72dcde142db25a7aecf5526d875b86 (diff) | |
radv: fix R_02881C_PA_CL_VS_OUT_CNTL with mixed cull/clip distances
Matches radeonsi.
Seems Vulkan CTS doesn't really test cull distances. Removing
VARYING_SLOT_CULL_DIST0/VARYING_SLOT_CULL_DIST1 variables doesn't break
any of dEQP-VK.clipping.*, except for tests which read the variables in
the fragment shader.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5984
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14882>
(cherry picked from commit 7ddad1b93a131df4c3ec86caf7cacd593caef64f)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/.pick_status.json b/.pick_status.json index dd6e1672de6..842b266308e 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -490,7 +490,7 @@ "description": "radv: fix R_02881C_PA_CL_VS_OUT_CNTL with mixed cull/clip distances", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c96fdd80f6a..bd2c3361ce0 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4448,7 +4448,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | - cull_dist_mask << 8 | clip_dist_mask); + total_mask << 8 | clip_dist_mask); if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index); @@ -4568,7 +4568,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | - cull_dist_mask << 8 | clip_dist_mask); + total_mask << 8 | clip_dist_mask); radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, S_028A84_PRIMITIVEID_EN(es_enable_prim_id) | |